CA2270516A1 - Frequency-doubling delay locked loop - Google Patents

Frequency-doubling delay locked loop Download PDF

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Publication number
CA2270516A1
CA2270516A1 CA002270516A CA2270516A CA2270516A1 CA 2270516 A1 CA2270516 A1 CA 2270516A1 CA 002270516 A CA002270516 A CA 002270516A CA 2270516 A CA2270516 A CA 2270516A CA 2270516 A1 CA2270516 A1 CA 2270516A1
Authority
CA
Canada
Prior art keywords
output
delay
clock signal
responsive
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002270516A
Other languages
French (fr)
Other versions
CA2270516C (en
Inventor
Paul Demone
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mosaid Technologies Inc
Original Assignee
Mosaid Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosaid Technologies Inc filed Critical Mosaid Technologies Inc
Priority to CA002270516A priority Critical patent/CA2270516C/en
Priority to KR1020017013919A priority patent/KR100811766B1/en
Priority to CNB008069409A priority patent/CN1190012C/en
Priority to AU42803/00A priority patent/AU4280300A/en
Priority to DE10084500.2T priority patent/DE10084500B3/en
Priority to PCT/CA2000/000468 priority patent/WO2000067381A1/en
Priority to GB0125097A priority patent/GB2363684B/en
Priority to DE2000185617 priority patent/DE10085617A5/en
Priority to JP2000616126A priority patent/JP2002543732A/en
Priority to US09/562,024 priority patent/US6441659B1/en
Publication of CA2270516A1 publication Critical patent/CA2270516A1/en
Priority to US10/227,547 priority patent/US7116141B2/en
Priority to US11/495,212 priority patent/US7456666B2/en
Priority to US12/284,763 priority patent/US7746136B2/en
Application granted granted Critical
Publication of CA2270516C publication Critical patent/CA2270516C/en
Priority to JP2009287078A priority patent/JP4619446B2/en
Priority to US12/784,157 priority patent/US8283959B2/en
Priority to JP2010210865A priority patent/JP4677511B2/en
Priority to US13/607,015 priority patent/US8558593B2/en
Priority to US14/023,047 priority patent/US8754687B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006—Changing the frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/15026—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages
    • H03K5/15046—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages using a tapped delay line
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses

Abstract

This invention relates to a delay locked loop that generates an output clock signal in response to a reference input clock signal comprises several components. A
delay line having a plurality of serially coupled delay stages, provides a delay stage tap output from each of the delay stages.
Each of the delay stage tap outputs is coupled to a one of a plurality of combining circuit cells. The combining cells each have the same predetermined number of inputs and provide a pair of complementary outputs. The outputs of each cell are separated in time in relation to the number of cell inputs. A selector responsive to a selection control signal selects an output from one of a pair of complementary outputs from one of the combining cells, to produce said output clock signal. A phase detector responsive to the output signal and the reference input clock signal to control the selector for selecting an optimum output for synchronizing the reference input clock signal and the said output clock signal.

Claims (6)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A frequency multiplier circuit comprising:
(b) a delay line receiving at one end thereof a reference clock and for generating clock tap outputs from respective ones of a plurality of period matched delay elements;
(b) a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock public from respective to ones of said pairs whereby said output clock period is less than said input clock period.
2. A circuit as defined in claim 1, including a plurality of combing circuits, each generating on output clock pulse.
A circuit as defined in claim 2, each said combing circuits generating a first and second complementary output.
4. A delay locked loop for generating an output clock signal in response to a reference input clock signal comprising:
a) a delay line having a plurality of serially coupled delay stages, each of the delay stages providing a delay stage tap output;
b) a plurality of combining circuit cells, each combining cell having inputs respectively coupled to ones of a predetermined number of delay stage tap outputs, each of the combining cells providing first and second complementary outputs, the outputs of each cell being separated in time by said predetermined number of delay stages;
c) a selector responsive to a selection control signal for selecting an output from one of a pair of complementary outputs of one of the combining cells, to produce said output clock signal;

d) a phase detector responsive to said output signal and said reference input clock signal to control to said selector for selecting an optimum complimentary output for synchronizing the reference input clock signal and the said output clock signal.
5. A delay locked loop as described in claim 4 including N serially coupled delay stages providing N tap outputs to N/4 combining circuit cells and the N/4 combining cells provide N/2 evenly spaced phases of the output clock signal whose frequency is twice that of the reference input clock.
6. A delay locked loop as described in claim 4 wherein each of the combining circuit cells are responsive to a rising edge of a pulse of said input clock for initiating a rising pulse of said output clock and responsive to a delayed version of said input pulse for clearing said pulse and responsive to a falling edge of said input clock pulse to initiate a rising edge of a second output pulse and responsive to a delayed version of said input falling edge for clearing said second output pulse.
CA002270516A 1999-04-30 1999-04-30 Frequency-doubling delay locked loop Expired - Fee Related CA2270516C (en)

Priority Applications (18)

Application Number Priority Date Filing Date Title
CA002270516A CA2270516C (en) 1999-04-30 1999-04-30 Frequency-doubling delay locked loop
KR1020017013919A KR100811766B1 (en) 1999-04-30 2000-05-01 Frequency-multiplying delay locked loop and method for generating an output clock signal using its
CNB008069409A CN1190012C (en) 1999-04-30 2000-05-01 Frequency-multiplying delay locked loop
AU42803/00A AU4280300A (en) 1999-04-30 2000-05-01 Frequency-multiplying delay locked loop
DE10084500.2T DE10084500B3 (en) 1999-04-30 2000-05-01 Frequency multiplying Delay Locked Loop
PCT/CA2000/000468 WO2000067381A1 (en) 1999-04-30 2000-05-01 Frequency-multiplying delay locked loop
GB0125097A GB2363684B (en) 1999-04-30 2000-05-01 Frequency-multiplying delay locked loop
DE2000185617 DE10085617A5 (en) 1999-04-30 2000-05-01 Frequency multiplying Delay Locked Loop (DLL)
JP2000616126A JP2002543732A (en) 1999-04-30 2000-05-01 Frequency multiplication delay lock loop
US09/562,024 US6441659B1 (en) 1999-04-30 2000-05-01 Frequency-doubling delay locked loop
US10/227,547 US7116141B2 (en) 1999-04-30 2002-08-26 Frequency-doubling delay locked loop
US11/495,212 US7456666B2 (en) 1999-04-30 2006-07-28 Frequency-doubling delay locked loop
US12/284,763 US7746136B2 (en) 1999-04-30 2008-09-25 Frequency-doubling delay locked loop
JP2009287078A JP4619446B2 (en) 1999-04-30 2009-12-18 Frequency multiplier circuit
US12/784,157 US8283959B2 (en) 1999-04-30 2010-05-20 Frequency-doubling delay locked loop
JP2010210865A JP4677511B2 (en) 1999-04-30 2010-09-21 Frequency multiplication delay lock loop
US13/607,015 US8558593B2 (en) 1999-04-30 2012-09-07 Frequency-doubling delay locked loop
US14/023,047 US8754687B2 (en) 1999-04-30 2013-09-10 Frequency-doubling delay locked loop

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA002270516A CA2270516C (en) 1999-04-30 1999-04-30 Frequency-doubling delay locked loop

Publications (2)

Publication Number Publication Date
CA2270516A1 true CA2270516A1 (en) 2000-10-30
CA2270516C CA2270516C (en) 2009-11-17

Family

ID=4163496

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002270516A Expired - Fee Related CA2270516C (en) 1999-04-30 1999-04-30 Frequency-doubling delay locked loop

Country Status (9)

Country Link
US (7) US6441659B1 (en)
JP (3) JP2002543732A (en)
KR (1) KR100811766B1 (en)
CN (1) CN1190012C (en)
AU (1) AU4280300A (en)
CA (1) CA2270516C (en)
DE (2) DE10084500B3 (en)
GB (1) GB2363684B (en)
WO (1) WO2000067381A1 (en)

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US20100225370A1 (en) 2010-09-09
US20140009196A1 (en) 2014-01-09
US7456666B2 (en) 2008-11-25
CN1190012C (en) 2005-02-16
US7746136B2 (en) 2010-06-29
JP2011019281A (en) 2011-01-27
CN1349683A (en) 2002-05-15
GB2363684A (en) 2002-01-02
DE10084500T1 (en) 2002-06-27
KR20020018660A (en) 2002-03-08
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AU4280300A (en) 2000-11-17
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US20030042947A1 (en) 2003-03-06
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US20130015898A1 (en) 2013-01-17
CA2270516C (en) 2009-11-17
US6441659B1 (en) 2002-08-27
US7116141B2 (en) 2006-10-03
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US20060261866A1 (en) 2006-11-23
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US8754687B2 (en) 2014-06-17
US8558593B2 (en) 2013-10-15

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