CA2271536A1 - Non-uniform memory access (numa) data processing system that buffers potential third node transactions to decrease communication latency - Google Patents

Non-uniform memory access (numa) data processing system that buffers potential third node transactions to decrease communication latency Download PDF

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Publication number
CA2271536A1
CA2271536A1 CA002271536A CA2271536A CA2271536A1 CA 2271536 A1 CA2271536 A1 CA 2271536A1 CA 002271536 A CA002271536 A CA 002271536A CA 2271536 A CA2271536 A CA 2271536A CA 2271536 A1 CA2271536 A1 CA 2271536A1
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CA
Canada
Prior art keywords
numa
processing node
transaction
interconnect
memory access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002271536A
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French (fr)
Other versions
CA2271536C (en
Inventor
Gary D. Carpenter
Mark E. Dean
David B. Glasco
Richard N. Iachetta, Jr.
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International Business Machines Corp
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International Business Machines Corp
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Publication of CA2271536A1 publication Critical patent/CA2271536A1/en
Application granted granted Critical
Publication of CA2271536C publication Critical patent/CA2271536C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Abstract

A non-uniform memory access (NUMA) computer system includes an interconnect to which multiple processing nodes (including first, second, and third processing nodes) are coupled. Each of the first, second, and third processing nodes includes at least one processor and a local system memory. The NUMA computer system further includes a transaction buffer, coupled to the interconnect, that stores communication transactions transmitted on the interconnect that are both initiated by and targeted at a processing node other than the third processing node. In response to a determination that a particular communication transaction originally targeting another processing node should be processed by the third processing node, buffer control logic coupled to the transaction buffer causes the particular communication transaction to be retrieved from the transaction buffer and processed by the third processing node. In one embodiment, the interconnect includes a broadcast fabric, and the transaction buffer and buffer control logic form a portion of the third processing node.
CA002271536A 1998-06-30 1999-05-12 Non-uniform memory access (numa) data processing system that buffers potential third node transactions to decrease communication latency Expired - Fee Related CA2271536C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/106,945 1998-06-30
US09/106,945 US6067611A (en) 1998-06-30 1998-06-30 Non-uniform memory access (NUMA) data processing system that buffers potential third node transactions to decrease communication latency

Publications (2)

Publication Number Publication Date
CA2271536A1 true CA2271536A1 (en) 1999-12-30
CA2271536C CA2271536C (en) 2002-07-02

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CA002271536A Expired - Fee Related CA2271536C (en) 1998-06-30 1999-05-12 Non-uniform memory access (numa) data processing system that buffers potential third node transactions to decrease communication latency

Country Status (5)

Country Link
US (1) US6067611A (en)
JP (1) JP3470951B2 (en)
KR (1) KR100324975B1 (en)
BR (1) BR9903228A (en)
CA (1) CA2271536C (en)

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US7917646B2 (en) * 2002-12-19 2011-03-29 Intel Corporation Speculative distributed conflict resolution for a cache coherency protocol
US7111128B2 (en) * 2002-12-19 2006-09-19 Intel Corporation Hierarchical virtual model of a cache hierarchy in a multiprocessor system
US7644237B1 (en) * 2003-06-23 2010-01-05 Mips Technologies, Inc. Method and apparatus for global ordering to insure latency independent coherence
US20050262250A1 (en) * 2004-04-27 2005-11-24 Batson Brannon J Messaging protocol
US7822929B2 (en) * 2004-04-27 2010-10-26 Intel Corporation Two-hop cache coherency protocol
US20050240734A1 (en) * 2004-04-27 2005-10-27 Batson Brannon J Cache coherence protocol
US7305524B2 (en) * 2004-10-08 2007-12-04 International Business Machines Corporation Snoop filter directory mechanism in coherency shared memory system
US8332592B2 (en) * 2004-10-08 2012-12-11 International Business Machines Corporation Graphics processor with snoop filter
US7577794B2 (en) * 2004-10-08 2009-08-18 International Business Machines Corporation Low latency coherency protocol for a multi-chip multiprocessor system
US7451231B2 (en) * 2005-02-10 2008-11-11 International Business Machines Corporation Data processing system, method and interconnect fabric for synchronized communication in a data processing system
US7395381B2 (en) * 2005-03-18 2008-07-01 Intel Corporation Method and an apparatus to reduce network utilization in a multiprocessor system
JP5115075B2 (en) * 2007-07-25 2013-01-09 富士通株式会社 Transfer device, information processing device having transfer device, and control method
JP6578992B2 (en) * 2016-03-02 2019-09-25 富士通株式会社 Control circuit, information processing apparatus, and control method for information processing apparatus
CN108123901B (en) 2016-11-30 2020-12-29 新华三技术有限公司 Message transmission method and device
US10579527B2 (en) 2018-01-17 2020-03-03 International Business Machines Corporation Remote node broadcast of requests in a multinode data processing system
US10713169B2 (en) 2018-01-17 2020-07-14 International Business Machines Corporation Remote node broadcast of requests in a multinode data processing system
US10387310B2 (en) 2018-01-17 2019-08-20 International Business Machines Corporation Remote node broadcast of requests in a multinode data processing system
US11068407B2 (en) 2018-10-26 2021-07-20 International Business Machines Corporation Synchronized access to data in shared memory by protecting the load target address of a load-reserve instruction
US10884740B2 (en) 2018-11-08 2021-01-05 International Business Machines Corporation Synchronized access to data in shared memory by resolving conflicting accesses by co-located hardware threads
US11119781B2 (en) 2018-12-11 2021-09-14 International Business Machines Corporation Synchronized access to data in shared memory by protecting the load target address of a fronting load
US11106608B1 (en) 2020-06-22 2021-08-31 International Business Machines Corporation Synchronizing access to shared memory by extending protection for a target address of a store-conditional request
US11693776B2 (en) 2021-06-18 2023-07-04 International Business Machines Corporation Variable protection window extension for a target address of a store-conditional request

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Also Published As

Publication number Publication date
KR20000005690A (en) 2000-01-25
KR100324975B1 (en) 2002-02-20
JP3470951B2 (en) 2003-11-25
CA2271536C (en) 2002-07-02
JP2000112910A (en) 2000-04-21
US6067611A (en) 2000-05-23
BR9903228A (en) 2000-10-03

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