CA2291049A1 - Fair and efficient cell scheduling in input-buffered multipoint switch - Google Patents

Fair and efficient cell scheduling in input-buffered multipoint switch Download PDF

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Publication number
CA2291049A1
CA2291049A1 CA002291049A CA2291049A CA2291049A1 CA 2291049 A1 CA2291049 A1 CA 2291049A1 CA 002291049 A CA002291049 A CA 002291049A CA 2291049 A CA2291049 A CA 2291049A CA 2291049 A1 CA2291049 A1 CA 2291049A1
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CA
Canada
Prior art keywords
input
fair
switch
efficient cell
cell scheduling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002291049A
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French (fr)
Other versions
CA2291049C (en
Inventor
Gunes Aybay
Philip Arnold Ferolito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Riverstone Networks Inc
Original Assignee
Cabletron Systems, Inc.
Gunes Aybay
Philip Arnold Ferolito
Yago Systems, Inc.
Riverstone Networks, Inc.
Enterasys Networks, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cabletron Systems, Inc., Gunes Aybay, Philip Arnold Ferolito, Yago Systems, Inc., Riverstone Networks, Inc., Enterasys Networks, Inc. filed Critical Cabletron Systems, Inc.
Publication of CA2291049A1 publication Critical patent/CA2291049A1/en
Application granted granted Critical
Publication of CA2291049C publication Critical patent/CA2291049C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/50—Overload detection or protection within a single switching element
    • H04L49/505—Corrective measures
    • H04L49/508—Head of Line Blocking Avoidance
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H04L49/1553—Interconnection of ATM switching modules, e.g. ATM switching fabrics
    • H04L49/1576—Crossbar or matrix
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/20—Support for services
    • H04L49/201—Multicast operation; Broadcast operation
    • H04L49/203—ATM switching fabrics with multicast or broadcast capabilities
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
    • H04L49/254—Centralised controller, i.e. arbitration or scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/35—Switches specially adapted for specific applications
    • H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
    • H04L49/352—Gigabit ethernet switching [GBPS]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/60—Software-defined switches
    • H04L49/608—ATM switches adapted to switch variable length packets, e.g. IP packets
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5651—Priority, marking, classes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5679—Arbitration or scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/20—Support for services
    • H04L49/201—Multicast operation; Broadcast operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/40—Constructional details, e.g. power supply, mechanical construction or backplane

Abstract

An input-buffered multipoint switch (60) having input channels (62, 64, 66 and 68) and output channels (72, 74, 76 and 78) includes multi-level request buffers (122, 124, 126 and 128), a data multiplexer (130), and a scheduler (132). The switch (60) has a distinct multi-level request buffer associated with each input channel and each request buffer has multiple request registers (160, 162, 164 and 166) for storing data cell transfer requests of different priorities. The multiple request registers (160, 162, 164 and 166) are linked in parallel to the scheduler (132) to allow arbitration among requests of different input channels and different priority levels.
CA002291049A 1998-03-10 1999-03-03 Fair and efficient cell scheduling in input-buffered multipoint switch Expired - Fee Related CA2291049C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/037,218 1998-03-10
US09/037,218 US6044061A (en) 1998-03-10 1998-03-10 Method and apparatus for fair and efficient scheduling of variable-size data packets in an input-buffered multipoint switch
PCT/US1999/004626 WO1999046903A1 (en) 1998-03-10 1999-03-03 Fair and efficient cell scheduling in input-buffered multipoint switch

Publications (2)

Publication Number Publication Date
CA2291049A1 true CA2291049A1 (en) 1999-09-16
CA2291049C CA2291049C (en) 2004-12-21

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CA002291049A Expired - Fee Related CA2291049C (en) 1998-03-10 1999-03-03 Fair and efficient cell scheduling in input-buffered multipoint switch

Country Status (5)

Country Link
US (1) US6044061A (en)
EP (1) EP0981878B1 (en)
AU (1) AU746166B2 (en)
CA (1) CA2291049C (en)
WO (1) WO1999046903A1 (en)

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Also Published As

Publication number Publication date
AU746166B2 (en) 2002-04-18
EP0981878A4 (en) 2009-07-29
WO1999046903A1 (en) 1999-09-16
CA2291049C (en) 2004-12-21
EP0981878B1 (en) 2011-10-19
AU2980099A (en) 1999-09-27
EP0981878A1 (en) 2000-03-01
US6044061A (en) 2000-03-28

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