CA2298990A1 - Method and system for resistance to power analysis - Google Patents

Method and system for resistance to power analysis Download PDF

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Publication number
CA2298990A1
CA2298990A1 CA002298990A CA2298990A CA2298990A1 CA 2298990 A1 CA2298990 A1 CA 2298990A1 CA 002298990 A CA002298990 A CA 002298990A CA 2298990 A CA2298990 A CA 2298990A CA 2298990 A1 CA2298990 A1 CA 2298990A1
Authority
CA
Canada
Prior art keywords
hamming
information
neutral
bits
execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002298990A
Other languages
French (fr)
Inventor
Zhengchu Xiao
Stanley T. Chow
Harold J. Johnson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cloakware Corp
Original Assignee
Cloakware Corporation
Zhengchu Xiao
Stanley T. Chow
Harold J. Johnson
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cloakware Corporation, Zhengchu Xiao, Stanley T. Chow, Harold J. Johnson filed Critical Cloakware Corporation
Priority to CA002298990A priority Critical patent/CA2298990A1/en
Priority to PCT/CA2001/000201 priority patent/WO2001061916A2/en
Priority to AU2001235280A priority patent/AU2001235280A1/en
Priority to CA002397077A priority patent/CA2397077A1/en
Priority to PCT/CA2001/000200 priority patent/WO2001061915A2/en
Priority to US10/181,942 priority patent/US20040025032A1/en
Priority to AU2001235279A priority patent/AU2001235279A1/en
Priority to CA002397615A priority patent/CA2397615A1/en
Priority to EP01907279A priority patent/EP1256203A2/en
Priority to US10/203,156 priority patent/US20040078588A1/en
Priority to PCT/CA2001/000199 priority patent/WO2001061914A2/en
Priority to EP01907278A priority patent/EP1256202A2/en
Priority to US10/181,452 priority patent/US20040030905A1/en
Priority to AU2001235281A priority patent/AU2001235281A1/en
Priority to CA002398441A priority patent/CA2398441A1/en
Priority to EP01907277A priority patent/EP1256201A2/en
Publication of CA2298990A1 publication Critical patent/CA2298990A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
    • H04L9/0625—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
    • G06K19/07363—Means for preventing undesired reading or writing from or onto record carriers by preventing analysis of the circuit, e.g. dynamic or static power analysis or current analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00—Payment architectures, schemes or protocols
    • G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
    • G06Q20/34—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using cards, e.g. integrated circuit [IC] cards or magnetic cards
    • G06Q20/341—Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
    • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
    • G07F7/0806—Details of the card
    • G07F7/0813—Specific details related to card security
    • G07F7/082—Features insuring the integrity of the data on or in the card
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
    • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
    • G07F7/10—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means together with a coded signal, e.g. in the form of personal identification information, like personal identification number [PIN] or biometric data
    • G07F7/1008—Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/002—Countermeasures against attacks on cryptographic mechanisms
    • H04L9/003—Countermeasures against attacks on cryptographic mechanisms for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
    • G06F2207/7219—Countermeasures against side channel or fault attacks

Claims (18)

1. The Hamming-neutral encoding of data values used during computation for resistance to leaking of secret information during power analysis of sealed platforms, such as smart cards, by means of pre-computing an appropriate Hamming-neutral set or Hamming-neutral assembly as described herein, and encoding of data according to an enumeration of the elements in that set as described herein.
2. The Hamming-neutral addressing of indexed data used during computation for resistance to discovery of indices in indexed tables, by means of pre-computing an appropriate Hamming-neutral set or Hamming-neutral assembly as described herein, and encoding of addresses according to an enumeration of the elements in that set as described herein.
3. The Hamming-neutral addressing of indexed data used during computation for resistance to discovery of indices in indexed tables, by means of pre-computing an appropriate Hamming-neutral set or Hamming-neutral assembly as described herein, and encoding of addresses according to an enumeration of the elements in that set as described herein, using the herein-described representation in which each address element in the set or assembly consists of zero or more fixed prefix bits, one or more groups of varying bits (one per dimension of indexing), and zero or more fixed suffix bits, where the prefix bits select a region in memory and the suffix bits select an offset.
4. Protection of execution from revelation of secrets under power analysis by the method of average-neutral execution, in which initially a hash of information is computed, depending on any initial information which would be provided by an attacker using power analysis, and on any initial information which the attacker using power analysis would guess, such as data to be encrypted or decrypted and the key controlling such encryption or decryption; said hash being used to produce one or more Hamming-neutral encodings of Boolean values used to determine whether execution is normal or bit-complemented ('bit flipped').
5. Protection of execution from revelation of secrets under power analysis by the method of permuted execution, in which initially a hash of information is computed, depending on any initial information which would be provided by an attacker using power analysis, and on any initial information which the attacker using power analysis would guess, such as data to be encrypted or decrypted and the key controlling such encryption or decryption, and on sequencing information during execution, such as encryption round number;
said hash being used to produce one or more Hamming-neutral encodings of sequences of values representing a pseudo-random permutation of a sequence, used to determine in what order steps of execution are performed, thereby mixing averaged information for particular values predicted by an attacker with other, randomly chosen information.
6. The method of performing the protection described in the above claim 5, in which further protection is provided by more finely subdividing the operations to be permuted, thereby mixing averaged information for particular values predicted by an attacker with an increased number of other, randomly chosen information.
7. Protection of execution from revelation of secrets under power analysis by the method of time-shifted execution, in which initially a hash of information is computed, depending on any initial information which would be provided by an attacker using power analysis, and on any initial information which the attacker using power analysis would guess, such as data to be encrypted or decrypted and the key controlling such encryption or decryption, and on sequencing information during execution, such as encryption round number;
said hash being used to produce a sequence of one or more Hamming-neutral of values representing a pseudo-random series of code executions, used to inject spurious computations among the significant computations, thereby making the timing of power features unpredictable and thereby less susceptible to information leakage by timing-based power analysis.
8. The method of performing the protection described above in claims 1 - 7, by combining two or more of these methods either to the same part of a program, or differently to different parts of a program, to achieve a desired level of protection for the program, or a desired level of protection differing among parts of the program, whre the program is to be protected against leakage of information when under attack by power analysis.
9. The method of combining methods described above in claims 1 - 7 in concert with methods from either or both of the co-pending data flow patent application, United States Patent Application No. 09/329,117 and the co-pending control flow patent application as outlined in United States Patent Application Serial No. 09/377,312, by combining two or more of these methods either to the same part of a program, or differently to different parts of a program, to achieve a desired level of protection for the program, or a desired level of protection differing among parts of the program, whre the program is to be protected against leakage of information when under attack by power analysis or by other, more intrusive techniques such as execution tracing, debugging, and graph analysis of the code and data.
10. The method of avoiding transition count and Hamming weight leakage during execution of masking operations by initially setting affected fields to all 0-bits or all 1-bits, thereby preventing power feature distinctions from being observed during transitions from one state to another.
11. The method of shifting quantities without revealing information due to Hamming weight leakage or transition count leakage, by masking out portions which will be shifted end-off during the shifting process, so that only 0-bits (or only 1-bits) will be shifted end-off, thereby not revealing by timing differences or Hamming-weights or transition counts the actual represented values shifted and/or masked.
12. The method of extracting bit-fields without revealing information due to Hamming weight leakage or transition count leakage, by masking out portions which will be shifted end-off during the shifting process, so that only 0-bits (or only 1-bits) will be shifted end-off, thereby not revealing by timing differences or Hamming-weights or transition counts the actual represented values shifted and/or masked.
13. The method of inserting bit-fields without revealing information due to Hamming weight leakage or transition count leakage, by masking out portions which will be shifted end-off during the shifting process, so that only 0-bits (or only 1-bits) will be shifted end-off, thereby not revealing by timing differences or Hamming-weights or transition counts the actual represented values shifted and/or masked.
14. The general method of performing power-analysis-resistant DES as revealed in this disclosure.
15. The detailed layouts and techniques of performing power-analysis-resistant DES as revealed in this disclosure.
16. A system for executing the method of any one of claims 1 through 15.
17. A computer readable memory medium for storing software code executable to perform the method steps of any one of claims 1 through 15.
18. A carrier signal incorporating software code executable to perform the method steps of any one of claims 1 through 15.
CA002298990A 2000-02-18 2000-02-18 Method and system for resistance to power analysis Abandoned CA2298990A1 (en)

Priority Applications (16)

Application Number Priority Date Filing Date Title
CA002298990A CA2298990A1 (en) 2000-02-18 2000-02-18 Method and system for resistance to power analysis
PCT/CA2001/000201 WO2001061916A2 (en) 2000-02-18 2001-02-19 Encoding method and system resistant to power analysis
AU2001235280A AU2001235280A1 (en) 2000-02-18 2001-02-19 Method and system for resistance to statistical power analysis
CA002397077A CA2397077A1 (en) 2000-02-18 2001-02-19 Encoding method and system resistant to power analysis
PCT/CA2001/000200 WO2001061915A2 (en) 2000-02-18 2001-02-19 Method and system for resistance to statistical power analysis
US10/181,942 US20040025032A1 (en) 2000-02-18 2001-02-19 Method and system for resistance to statiscal power analysis
AU2001235279A AU2001235279A1 (en) 2000-02-18 2001-02-19 Method and apparatus for balanced electronic operations
CA002397615A CA2397615A1 (en) 2000-02-18 2001-02-19 Method and system for resistance to statistical power analysis
EP01907279A EP1256203A2 (en) 2000-02-18 2001-02-19 Encoding method and system resistant to power analysis
US10/203,156 US20040078588A1 (en) 2000-02-18 2001-02-19 Method and apparatus for balanced electronic operations
PCT/CA2001/000199 WO2001061914A2 (en) 2000-02-18 2001-02-19 Method and apparatus for balanced electronic operations
EP01907278A EP1256202A2 (en) 2000-02-18 2001-02-19 Method and system for resistance to statistical power analysis
US10/181,452 US20040030905A1 (en) 2000-02-18 2001-02-19 Encoding method and system resistant to power analysis
AU2001235281A AU2001235281A1 (en) 2000-02-18 2001-02-19 Encoding method and system resistant to power analysis
CA002398441A CA2398441A1 (en) 2000-02-18 2001-02-19 Method and apparatus for balanced electronic operations
EP01907277A EP1256201A2 (en) 2000-02-18 2001-02-19 Method and apparatus for balanced electronic operations

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA002298990A CA2298990A1 (en) 2000-02-18 2000-02-18 Method and system for resistance to power analysis

Publications (1)

Publication Number Publication Date
CA2298990A1 true CA2298990A1 (en) 2001-08-18

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CA002298990A Abandoned CA2298990A1 (en) 2000-02-18 2000-02-18 Method and system for resistance to power analysis

Country Status (5)

Country Link
US (3) US20040078588A1 (en)
EP (3) EP1256203A2 (en)
AU (3) AU2001235279A1 (en)
CA (1) CA2298990A1 (en)
WO (3) WO2001061914A2 (en)

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