CA2313139A1 - Receiver with sigma-delta analog-to-digital converter - Google Patents
Receiver with sigma-delta analog-to-digital converter Download PDFInfo
- Publication number
- CA2313139A1 CA2313139A1 CA002313139A CA2313139A CA2313139A1 CA 2313139 A1 CA2313139 A1 CA 2313139A1 CA 002313139 A CA002313139 A CA 002313139A CA 2313139 A CA2313139 A CA 2313139A CA 2313139 A1 CA2313139 A1 CA 2313139A1
- Authority
- CA
- Canada
- Prior art keywords
- sigma
- delta
- receiver
- adc
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005070 sampling Methods 0.000 claims abstract 19
- 241000682622 Andracantha sigma Species 0.000 claims 1
- 238000001914 filtration Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
- H04B1/0028—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at baseband stage
- H04B1/0032—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at baseband stage with analogue quadrature frequency conversion to and from the baseband
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
- H03D3/007—Demodulation of angle-, frequency- or phase- modulated oscillations by converting the oscillations into two quadrature related signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/16—Multiple-frequency-changing
- H03D7/165—Multiple-frequency-changing at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
- H04B1/0028—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at baseband stage
- H04B1/0039—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at baseband stage using DSP [Digital Signal Processor] quadrature modulation and demodulation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
- H04B1/26—Circuits for superheterodyne receivers
Abstract
A receiver comprising a sigma-delta analog-to-digital converter(.SIGMA..DELTA. ADC) can be utilized in one of four configurations, as a subsampling bandpass receiver, a subsampling baseband receiver, a Nyquist sampling bandpass receiver, or a Nyquist sampling baseband receiver. For subsampling .SIGMA..DELTA. receivers, the sampling frequency is less than twice the center frequency of the input signal into the .SIGMA..DELTA. ADC. For Nyquist sampling .SIGMA..DELTA. receivers, the sampling frequency is at least twice the highest frequency of the input signal into the .SIGMA..DELTA. ADC. For baseband .SIGMA..DELTA. receivers, the center frequency of the output signal from the .SIGMA..DELTA. ADC is approximately zero or DC. For bandpass .SIGMA..DELTA. receivers, the center frequency of the output signal from the .SIGMA..DELTA. ADC is greater than zero. The sampling frequency can be selected based on the bandwidth of the input signal to simplify the design of the digital circuits used to process the output samples from the .SIGMA..DELTA. ADC. Furthermore, the center frequency of the input signal can be selected based on the sampling frequency and the bandwidth of the input signal. The .SIGMA..DELTA. ADC within the receiver provides many benefits.
Claims (26)
1. A receiver for demodulating an RF signal comprising :
a front end for receiving said RF signal and downconverting said RF
signal to an intermediate (IF) signal, said IF signal having a center frequency and a two-sided bandwidth;
a .SIGMA..DELTA. ADC connected to said front end for receiving said IF signal and sampling said IF signal to produce IF samples, said .SIGMA..DELTA. ADC being clocked at a sampling frequency;
a digital signal processor connected to said .SIGMA..DELTA. ADC for receiving said IF samples and demodulating said IF samples in accordance with a modulation format used to produce said RF signal.
a front end for receiving said RF signal and downconverting said RF
signal to an intermediate (IF) signal, said IF signal having a center frequency and a two-sided bandwidth;
a .SIGMA..DELTA. ADC connected to said front end for receiving said IF signal and sampling said IF signal to produce IF samples, said .SIGMA..DELTA. ADC being clocked at a sampling frequency;
a digital signal processor connected to said .SIGMA..DELTA. ADC for receiving said IF samples and demodulating said IF samples in accordance with a modulation format used to produce said RF signal.
2. The receiver of claim 1 wherein said .SIGMA..DELTA. ADC is an subsampling bandpass .SIGMA..DELTA. ADC.
3. The receiver of claim 1 wherein said .SIGMA..DELTA. ADC is an subsampling baseband .SIGMA..DELTA. ADC.
4. The receiver of claim 1 wherein said .SIGMA..DELTA. ADC is a Nyquist sampling bandpass .SIGMA..DELTA. ADC.
5. The receiver of claim 1 wherein said .SIGMA..DELTA. ADC is a Nyquist sampling baseband .SIGMA..DELTA. ADC.
6. The receiver of claim 2 wherein said center frequency of said IF
signal is 0.25~(2n+1) times said sampling frequency, where n is an integer greater than one.
signal is 0.25~(2n+1) times said sampling frequency, where n is an integer greater than one.
7. The receiver of claim 6 wherein n is equal to two.
8. The receiver of claim 2 wherein said center frequency of said IF
signal is 0.25~(2n) times said sampling frequency, where n is an integer greater than one.
signal is 0.25~(2n) times said sampling frequency, where n is an integer greater than one.
9. The receiver of claim 8 wherein n is equal to two.
10. The receiver of claim 2 wherein said sampling frequency is selected based on said two-sided bandwidth of said IF signal.
11. The receiver of claim 2 wherein said IF signal comprises a CDMA signal.
12. The receiver of claim 11 wherein said center frequency of said IF signal is at 116.5 MHz.
13. The receiver of claim 12 wherein said sampling frequency is 66.6 MHz.
14. The receiver of claim 1 wherein said demodulator comprises a digital filter for receiving said IF samples and providing filtered samples, said digital filter filtering said IF samples by a frequency response and decimating said filtered samples by a decimation ratio.
15. The receiver of claim 14 wherein said frequency response of said digital filter can be adjusted based on an operating mode of said receiver.
16. The receiver of claim 14 wherein said sampling frequency is selected based on said decimation ratio of said digital filter and said two-sided bandwidth of said IF signal.
17. The receiver of claim 1 wherein said .SIGMA..DELTA. ADC provides four or more bits of resolution.
18. The receiver of claim 1 wherein said .SIGMA..DELTA. ADC comprises multiple loops, each loop can be turned ON or OFF depending on a specified requirement.
19. The receiver of claim 1 wherein said .SIGMA..DELTA. ADC is clocked at an oversampling ratio of sixteen or greater.
20. The receiver of claim 1 wherein said .SIGMA..DELTA. ADC is a single-loop .SIGMA..DELTA. ADC.
21. The receiver of claim 1 wherein said .SIGMA..DELTA. ADC is a MASH
.SIGMA..DELTA.
ADC.
.SIGMA..DELTA.
ADC.
22 22. The receiver of claim 21 wherein said MASH .SIGMA..DELTA. ADC is a MASH 4-4 .SIGMA..DELTA. ADC.
23. A receiver for demodulating an RF signal comprising a front end for receiving said RF signal and downconverting said RF
signal to an intermediate (IF) signal;
a quadrature demodulator connected to said front end for receiving said IF signal and downconverting said IF signal into baseband I and Q
signals;
two .SIGMA..DELTA. ADCs connected to said quadrature demodulator, one .SIGMA..DELTA.
ADC receiving said baseband I signal and one .SIGMA..DELTA. ADC receiving said baseband Q signal, said .SIGMA..DELTA. ADCs sampling said baseband I and Q
signals to produce baseband samples, said .SIGMA..DELTA. ADC being clocked at a sampling frequency;
signal to an intermediate (IF) signal;
a quadrature demodulator connected to said front end for receiving said IF signal and downconverting said IF signal into baseband I and Q
signals;
two .SIGMA..DELTA. ADCs connected to said quadrature demodulator, one .SIGMA..DELTA.
ADC receiving said baseband I signal and one .SIGMA..DELTA. ADC receiving said baseband Q signal, said .SIGMA..DELTA. ADCs sampling said baseband I and Q
signals to produce baseband samples, said .SIGMA..DELTA. ADC being clocked at a sampling frequency;
24. The receiver of claim 23 wherein said .SIGMA..DELTA. ADCs are Nyquist sampling baseband .SIGMA..DELTA. ADCs.
25. The receiver of claim 24 wherein said .SIGMA..DELTA. ADCs are MASH
.SIGMA..DELTA.
ADC.
.SIGMA..DELTA.
ADC.
26. The receiver of claim 25 wherein said .SIGMA..DELTA. ADCs are MASH 4-4 .SIGMA..DELTA. ADC.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/987,306 US6005506A (en) | 1997-12-09 | 1997-12-09 | Receiver with sigma-delta analog-to-digital converter for sampling a received signal |
US08/987,306 | 1997-12-09 | ||
PCT/US1998/026051 WO1999030428A1 (en) | 1997-12-09 | 1998-12-08 | Receiver with sigma-delta analog-to-digital converter |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2313139A1 true CA2313139A1 (en) | 1999-06-17 |
CA2313139C CA2313139C (en) | 2009-12-15 |
Family
ID=25533178
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002313139A Expired - Fee Related CA2313139C (en) | 1997-12-09 | 1998-12-08 | Receiver with sigma-delta analog-to-digital converter |
Country Status (17)
Country | Link |
---|---|
US (1) | US6005506A (en) |
EP (1) | EP1040587B1 (en) |
JP (1) | JP2001526487A (en) |
KR (1) | KR100712412B1 (en) |
CN (1) | CN1178401C (en) |
AR (1) | AR017818A1 (en) |
AU (1) | AU746148B2 (en) |
BR (1) | BR9813414A (en) |
CA (1) | CA2313139C (en) |
DE (1) | DE69839192T2 (en) |
DK (1) | DK1040587T3 (en) |
ES (1) | ES2301217T3 (en) |
IL (1) | IL136403A0 (en) |
MX (1) | MXPA00005773A (en) |
MY (1) | MY114831A (en) |
WO (1) | WO1999030428A1 (en) |
ZA (1) | ZA9811125B (en) |
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-
1998
- 1998-12-03 MY MYPI98005485A patent/MY114831A/en unknown
- 1998-12-04 ZA ZA9811125A patent/ZA9811125B/en unknown
- 1998-12-07 AR ARP980106197A patent/AR017818A1/en active IP Right Grant
- 1998-12-08 KR KR20007006166A patent/KR100712412B1/en not_active IP Right Cessation
- 1998-12-08 BR BR9813414-0A patent/BR9813414A/en not_active IP Right Cessation
- 1998-12-08 CA CA002313139A patent/CA2313139C/en not_active Expired - Fee Related
- 1998-12-08 EP EP98962004A patent/EP1040587B1/en not_active Expired - Lifetime
- 1998-12-08 AU AU17178/99A patent/AU746148B2/en not_active Ceased
- 1998-12-08 MX MXPA00005773A patent/MXPA00005773A/en not_active IP Right Cessation
- 1998-12-08 ES ES98962004T patent/ES2301217T3/en not_active Expired - Lifetime
- 1998-12-08 DK DK98962004T patent/DK1040587T3/en active
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- 1998-12-08 WO PCT/US1998/026051 patent/WO1999030428A1/en active IP Right Grant
- 1998-12-08 IL IL13640398A patent/IL136403A0/en not_active IP Right Cessation
- 1998-12-08 JP JP2000524869A patent/JP2001526487A/en active Pending
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MY114831A (en) | 2003-01-31 |
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DK1040587T3 (en) | 2008-06-02 |
JP2001526487A (en) | 2001-12-18 |
WO1999030428A1 (en) | 1999-06-17 |
AU746148B2 (en) | 2002-04-18 |
EP1040587A1 (en) | 2000-10-04 |
CA2313139C (en) | 2009-12-15 |
ZA9811125B (en) | 2000-10-10 |
CN1281597A (en) | 2001-01-24 |
KR100712412B1 (en) | 2007-04-27 |
US6005506A (en) | 1999-12-21 |
CN1178401C (en) | 2004-12-01 |
IL136403A0 (en) | 2001-06-14 |
AU1717899A (en) | 1999-06-28 |
KR20010032840A (en) | 2001-04-25 |
BR9813414A (en) | 2000-10-10 |
AR017818A1 (en) | 2001-10-24 |
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