CA2409161A1 - Method and apparatus for incorporating a multiplier into an fpga - Google Patents

Method and apparatus for incorporating a multiplier into an fpga Download PDF

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Publication number
CA2409161A1
CA2409161A1 CA002409161A CA2409161A CA2409161A1 CA 2409161 A1 CA2409161 A1 CA 2409161A1 CA 002409161 A CA002409161 A CA 002409161A CA 2409161 A CA2409161 A CA 2409161A CA 2409161 A1 CA2409161 A1 CA 2409161A1
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Prior art keywords
bus
output
ram
data
multiplier
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Granted
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CA002409161A
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French (fr)
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CA2409161C (en
Inventor
Bernard J. New
Steven P. Young
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Xilinx Inc
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Xilinx, Inc.
Bernard J. New
Steven P. Young
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Publication of CA2409161A1 publication Critical patent/CA2409161A1/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17732—Macroblocks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only

Abstract

One or more columns of multi-function tiles are positioned between CLB tiles of the FPGA array. Each multi-function tile includes multiple function elements that share routing resources. In one embodiment, a multi-function tile includes a configurable, dual-ported RAM and a multiplier that share routing resources of the multi-function tile. The RAM includes first and second input ports coupled to first and second input data buses, respectively, and includes first and second output ports coupled to first and second output data buses, respectively. The multiplier includes first and second operand ports coupled to receive operands from the first and second input data buses, and in response thereto provides a product. In one embodiment, the most significant bits (MSBs) of the product are selectively provided to the first output data bus using bus multiplexer logic, and the least significant bits (LSBs) of the product are selectively provided to the second output data bus using bus multiplexer logic.

Claims (7)

1. A field programmable gate array (FPGA), comprising:

one or more columns of mufti-function tiles, each mufti-function tile comprising:

a programmable switch to provide programmable interconnections'to other tiles and other mufti-function blocks, the programmable switch including input (IMUX) and output (OMUX) multiplexers;

an input data bus coupled to the IMUX;

an output data bus coupled to the OMUX;

a memory having an input port coupled to the input data bus and an output port coupled to the output data bus; and a multiplier having an input port coupled to the input data bus and an output port coupled to the output data bus, wherein the first and second function blocks share routing resources of the mufti-function block.
2. The FPGA of Claim 1, wherein the input data bus comprises a first bus to carry a first data signal and second bus to carry a second data signal, wherein:

the RAM includes a first input port coupled to the first bus and a second input port coupled to the second bus; and the multiplier includes a first operand port coupled to the first bus and a second operand port coupled to the second bus.
3. The FPGA of Claim 2, wherein during a write operation to the RAM when the RAM is in a first configuration, the RAM writes a number of least-significant bits (LSBs) from the first data signal and from the second data signal to selected addresses in the RAM while the multiplier simultaneously multiples a number of most significant bits (MSBs) from the first data signal with a number of MSBs from the second data signal to generate a product.
4. The FPGA of Claim 3, wherein during a write operation to the RAM when the RAM is in a second configuration mode, the RAM writes the first and second data signals to selected addresses in the RAM.
5. The FPGA of Claim 1, wherein the output data bus comprises a first output bus and a second output bus coupled between the OMUX and first and second output ports, respectively, of the RAM.
6. A method of sharing routing resources between a multiplier and a memory within a multi-function block of a field programmable gate array (FPGA), comprising:

providing first and second data signals to the multi-function block;

providing a number of bits from the first data signal to the memory as a first data word;

providing a number of bits from the first data signal to the multiplier as a first operand;

providing a number of bits from the second data signal to the memory as a second data word;

providing a number of bits from the second data signal to the memory as a second operand;

writing the first and second data words to the memory; and simultaneously multiplying the first and second operands in the multiplier to generate a product.
7. The method of Claim 6, further comprising:

reading first and second output words from first and second output ports, respectively, of the memory;

and selectively concatenating the MSBs of the product with the first output word and selectively concatenating the LSBs of the product with the second output word to facilitate simultaneous reading of data from the RAM and product information from the multiplier.
CA2409161A 2000-05-18 2001-05-02 Method and apparatus for incorporating a multiplier into an fpga Expired - Lifetime CA2409161C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/574,714 US6362650B1 (en) 2000-05-18 2000-05-18 Method and apparatus for incorporating a multiplier into an FPGA
US09/574,714 2000-05-18
PCT/US2001/014259 WO2001089091A2 (en) 2000-05-18 2001-05-02 Method and apparatus for incorporating a multiplier into an fpga

Publications (2)

Publication Number Publication Date
CA2409161A1 true CA2409161A1 (en) 2001-11-22
CA2409161C CA2409161C (en) 2010-07-13

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CA2409161A Expired - Lifetime CA2409161C (en) 2000-05-18 2001-05-02 Method and apparatus for incorporating a multiplier into an fpga

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US (2) US6362650B1 (en)
EP (1) EP1303912B1 (en)
JP (1) JP4593866B2 (en)
CA (1) CA2409161C (en)
DE (1) DE60140674D1 (en)
WO (1) WO2001089091A2 (en)

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US20020057104A1 (en) 2002-05-16
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US6362650B1 (en) 2002-03-26
US6573749B2 (en) 2003-06-03

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