CA2421047A1 - Method and apparatus for optimized parallel testing and access of electronic circuits - Google Patents

Method and apparatus for optimized parallel testing and access of electronic circuits Download PDF

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Publication number
CA2421047A1
CA2421047A1 CA002421047A CA2421047A CA2421047A1 CA 2421047 A1 CA2421047 A1 CA 2421047A1 CA 002421047 A CA002421047 A CA 002421047A CA 2421047 A CA2421047 A CA 2421047A CA 2421047 A1 CA2421047 A1 CA 2421047A1
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CA
Canada
Prior art keywords
ptb
controller
access
addressable
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002421047A
Other languages
French (fr)
Other versions
CA2421047C (en
Inventor
Michael Ricchetti
Christopher J. Clark
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intellitech Corp
Original Assignee
Intellitech Corporation
Michael Ricchetti
Christopher J. Clark
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intellitech Corporation, Michael Ricchetti, Christopher J. Clark filed Critical Intellitech Corporation
Publication of CA2421047A1 publication Critical patent/CA2421047A1/en
Application granted granted Critical
Publication of CA2421047C publication Critical patent/CA2421047C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G01R31/318563—Multiple simultaneous testing of subparts
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516—Test of programmable logic devices [PLDs]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G11C2029/2602—Concurrent test

Abstract

A Parallel Test Architecture (PTA) is provided that facilitates simultaneous access to multiple electronic circuits (i.e.), in parallel) for optimized testing, debugging, or programmable configuration of the circuits. The PTA
includes a Parallel Test Bus (PTB), a test controller connected to the PTB, and a plurality of addressable PTB controllers connected to the PTB, in which each addressable PTB controller is coupleable to a respective electronic circuit to be accessed. The test controller is configured to send at least one control signal over the PTB to respective addressable PTB controllers to initiate parallel scan access of the electronic circuits coupleable thereto by the respective addressable PTB controllers. Further, each addressable PTB
controller is configured to employ a scan protocol to access the respective electronic circuit coupleable thereto based on the control signal sent over the PTB by the test controller, and send resultant scan data over the PTB to the first controller in response to accessing the respective electronic circuit.
CA002421047A 2001-07-05 2002-06-27 Method and apparatus for optimized parallel testing and access of electronic circuits Expired - Fee Related CA2421047C (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US30305201P 2001-07-05 2001-07-05
US60/303,052 2001-07-05
US10/119,060 US6988232B2 (en) 2001-07-05 2002-04-09 Method and apparatus for optimized parallel testing and access of electronic circuits
US10/119,060 2002-04-09
PCT/US2002/020505 WO2003005050A1 (en) 2001-07-05 2002-06-27 Method and apparatus for optimized parallel testing and access of electronic circuits

Publications (2)

Publication Number Publication Date
CA2421047A1 true CA2421047A1 (en) 2003-01-16
CA2421047C CA2421047C (en) 2005-01-25

Family

ID=26817004

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002421047A Expired - Fee Related CA2421047C (en) 2001-07-05 2002-06-27 Method and apparatus for optimized parallel testing and access of electronic circuits

Country Status (11)

Country Link
US (2) US6988232B2 (en)
EP (1) EP1402278B1 (en)
JP (1) JP4083117B2 (en)
KR (1) KR100623310B1 (en)
CN (1) CN100416288C (en)
AT (1) ATE370423T1 (en)
CA (1) CA2421047C (en)
DE (1) DE60221836T2 (en)
HK (1) HK1064444A1 (en)
TW (1) TWI250293B (en)
WO (1) WO2003005050A1 (en)

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Publication number Publication date
EP1402278A4 (en) 2005-05-18
TWI250293B (en) 2006-03-01
US7574637B2 (en) 2009-08-11
KR20030048024A (en) 2003-06-18
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