CA2458481A1 - Method and apparatus for translating sdh/sonet frames to ethernet frames - Google Patents

Method and apparatus for translating sdh/sonet frames to ethernet frames Download PDF

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Publication number
CA2458481A1
CA2458481A1 CA002458481A CA2458481A CA2458481A1 CA 2458481 A1 CA2458481 A1 CA 2458481A1 CA 002458481 A CA002458481 A CA 002458481A CA 2458481 A CA2458481 A CA 2458481A CA 2458481 A1 CA2458481 A1 CA 2458481A1
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Canada
Prior art keywords
sdh
sonet
ethernet
frames
payload
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Granted
Application number
CA002458481A
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French (fr)
Other versions
CA2458481C (en
Inventor
Rumi S. Gonda
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Individual
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Individual
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Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2458481A1 publication Critical patent/CA2458481A1/en
Application granted granted Critical
Publication of CA2458481C publication Critical patent/CA2458481C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/46—Interconnection of networks
    • H04L12/4604—LAN interconnection over a backbone network, e.g. Internet, Frame Relay
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
    • H04J3/1617—Synchronous digital hierarchy [SDH] or SONET carrying packets or ATM cells
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0073—Services, e.g. multimedia, GOS, QOS
    • H04J2203/0082—Interaction of SDH with non-ATM protocols
    • H04J2203/0085—Support of Ethernet
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET
    • H04J2203/0096—Serial Concatenation

Abstract

A translation engine is provided for efficiently translating SDH/SONET frames (101) to Ethernet frames (105) and vice versa. In accordance with one embodiment, a translation system includes a buffer (103) for holding SDH/SONET
(101) and Ethernet frames (105). An Ethernet Media Access Control (MAC) address for a corresponding SDH/SONET TDM slot (103 E-103 F) further provided.
A translation engine for translating SDH/SONET frames (101) into Ethernet frames (105) is in communication with an output interface. The SDH/SONET
payload (101 A) is sent through a translation engine to translate the SDH /
SONET payload (101 A) into an Ethernet payload (105 A). For translating from Ethernet to SDH / SONET, a reverse process occurs.

Claims (32)

What is claimed is:
1. A translation system for translation between SDH/SONET frames and Ethernet frames, comprising:
a buffer for holding SDH/SONET frames;
a plurality of SDH/SONET TDM slots in communication with the buffer and each having an Ethernet Media Access Control (MAC) address;
a translation engine in communication with the buffer for translating SDH/SONET frames into Ethernet frames; and a plurality of output interfaces in communication with the translation engine.
2. The translation system of claim 1, further comprising an add/drop mechanism in communication with the SDH/SONET frames for adding or dropping frame overhead bytes.
The translation system of claim 2, wherein the add/drop mechanism comprises at least one of an ASIC, a Field Programmable Gate Array (FPGA), and a Network Processor.
4. The translation system of claim 1, wherein the translation engine comprises at least one of an ASIC, an FPGA, and a Network Processor in communication with an SDH/SONET Framer, Ethernet MAC hardware, Ethernet physical hardware, and buffer logic to move the SDH/SONET frames and the Ethernet frames to and from the SDH/SONET Framer and the Ethernet MAC hardware.
5. The translation system of claim 4, wherein the Ethernet MAC hardware is modified to allow for multiple unique Ethernet MAC addresses.
6. The translation system of claim 4, wherein the Ethernet MAC hardware allows frames to travel therethrough without changing Source MAC Address or Destination MAC Address fields.
7. The translation system of claim 1, wherein the payload data comprises SDH/SONET
traffic that is at least one of channelized and concatenated.
8. A translation system for translation between Ethernet frames and SDH/SONET
frames, comprising:
a buffer for holding Ethernet frames;
a plurality of SDH/SONET TDM slots in communication with the buffer and each having an Ethernet MAC address;
a translation engine in communication with the buffer for translating Ethernet frames into SDH/SONET frames; and a plurality of output interfaces in communication with the translation engine.
9. The translation system of claim 8, further comprising an add/drop mechanism in communication with the SDH/SONET frames for adding or dropping frame overhead bytes.
10. The translation system of claim 9, wherein the add/drop mechanism comprises at least one of an ASIC, an FPGA, and a Network Processor.
11. The translation system of claim 8, wherein the translation engine comprises at least one of an ASIC, an FPGA, and a Network Processor in communication with an SDH/SONET Framer, Ethernet MAC hardware, Ethernet physical hardware, and buffer logic to move the SDH/SONET frames and Ethernet frames to and from the SDH/SONET Framer and the Ethernet MAC hardware.
12. The translation system of claim 11, wherein the Ethernet MAC hardware is modified to allow for multiple unique Ethernet MAC addresses.
13. The translation system of claim 11, wherein the Ethernet MAC hardware allows frames to travel therethrough without changing Source MAC Address or Destination MAC Address fields.
14. The translation system of claim 8, wherein the payload data at the SDH/SONET
frames comprises SDH/SONET traffic that is at least one of channelized and concatenated.
15. A method of translating payload data from SDH/SONET frames to Ethernet frames, comprising the steps of:
providing an SDH/SONET payload; and sending the SDH/SONET payload through a translation engine to translate the SDH/SONET payload into an Ethernet payload.
16. The method of claim 15, wherein the SDH/SONET payload passes through a buffer.
17. The method of claim 15, wherein the translation engine comprises at least one of an ASIC, an FPGA, and a Network Processor in communication with an SDH/SONET
Framer, Ethernet MAC hardware, Ethernet physical hardware, and buffer logic to move the payload data to and from the SDH/SONET Framer and the Ethernet MAC
hardware.
18. The method of claim 17, wherein the Ethernet MAC hardware is modified to allow for multiple unique Ethernet MAC addresses.
19. The method of claim 17, wherein the Ethernet MAC hardware allows frames to travel therethrough without changing Source MAC Address or Destination MAC
Address fields.
20. The method of claim 15, wherein the payload comprises SDH/SONET traffic that is at least one of channelized and concatenated.
21. A method of translating payload data Ethernet frames to SDH/SONET frames, comprising the steps of:
providing an Ethernet payload; and sending the Ethernet payload through a translation engine to translate the Ethernet payload into an SDH/SONET payload.
22. The method of claim 21, wherein the Ethernet payload passes through a buffer.
23. The method of claim 21, wherein the translation engine comprises at least one of an ASIC, an FPGA, and a Network Processor in communication with an SDH/SONET
Framer, Ethernet MAC hardware, Ethernet physical hardware, and buffer logic to move the payload data to and from the SDH/SONET Framer and the Ethernet MAC
hardware.
24. The method of claim 23, wherein the Ethernet MAC hardware is modified to allow for multiple unique Ethernet MAC addresses.
25. The method of claim 23, wherein the Ethernet MAC hardware allows frames to travel therethrough without changing Source MAC Address or Destination MAC
Address fields.
26. The method of claim 21, wherein the payload at the SDH/SONET payload destination comprises SDH/SONET traffic that is at least one of channelized and concatenated.
27. A method of translating an SDH/SONET frame to an Ethernet frame, comprising:
the SDH/SONET frame entering a translation system at an SDH/SONET
interface element;
a translation engine within the translation system processing the SDH/SONET
frame to translate the SDH/SONET frame to the Ethernet frame; and transmitting the Ethernet frame from the translation system through an Ethernet interface element.
28. The method of claim 27, wherein the translation engine further comprises a buffer element for storing the Ethernet frame information.
29. The method of claim 27, wherein the SDH/SONET frame comprises payload data in the form of SDH/SONET traffic that is at least one of channelized and concatenated.
30. A method of translating an Ethernet frame to an SDH/SONET frame, comprising:
the Ethernet frame entering a translation system at an Ethernet interface element;
a translation engine within the translation system processing the Ethernet frame to translate the Ethernet frame to the SDH/SONET frame; and transmitting the SDH/SONET frame from the translation system through an SDH/SONET interface element.
31. The method of claim 30, wherein the translation engine further comprises a buffer element for storing the SDH/SONET frame information.
32. The method of claim 30, wherein the SDH/SONET frame comprises payload data in the form of SDH/SONET traffic that is at least one of channelized and concatenated.
CA2458481A 2001-08-24 2002-08-26 Method and apparatus for translating sdh/sonet frames to ethernet frames Expired - Fee Related CA2458481C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US31480101P 2001-08-24 2001-08-24
US60/314,801 2001-08-24
PCT/US2002/027253 WO2003032539A1 (en) 2001-08-24 2002-08-26 Method and apparatus for translating sdh/sonet frames to ethernet frames

Publications (2)

Publication Number Publication Date
CA2458481A1 true CA2458481A1 (en) 2003-04-17
CA2458481C CA2458481C (en) 2010-05-18

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CA2458481A Expired - Fee Related CA2458481C (en) 2001-08-24 2002-08-26 Method and apparatus for translating sdh/sonet frames to ethernet frames

Country Status (8)

Country Link
US (1) US7586941B2 (en)
EP (1) EP1421722B1 (en)
JP (1) JP4224400B2 (en)
CN (1) CN100459465C (en)
AT (1) ATE418821T1 (en)
CA (1) CA2458481C (en)
DE (1) DE60230523D1 (en)
WO (1) WO2003032539A1 (en)

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Also Published As

Publication number Publication date
EP1421722A1 (en) 2004-05-26
EP1421722A4 (en) 2006-05-17
JP4224400B2 (en) 2009-02-12
EP1421722B1 (en) 2008-12-24
ATE418821T1 (en) 2009-01-15
JP2005505987A (en) 2005-02-24
CA2458481C (en) 2010-05-18
WO2003032539A1 (en) 2003-04-17
CN100459465C (en) 2009-02-04
US7586941B2 (en) 2009-09-08
DE60230523D1 (en) 2009-02-05
US20030056017A1 (en) 2003-03-20
CN1575560A (en) 2005-02-02

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