CA2467112A1 - Semiconductor texturing process - Google Patents

Semiconductor texturing process Download PDF

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Publication number
CA2467112A1
CA2467112A1 CA002467112A CA2467112A CA2467112A1 CA 2467112 A1 CA2467112 A1 CA 2467112A1 CA 002467112 A CA002467112 A CA 002467112A CA 2467112 A CA2467112 A CA 2467112A CA 2467112 A1 CA2467112 A1 CA 2467112A1
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CA
Canada
Prior art keywords
semiconductor material
layer
process according
protective substance
etchant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002467112A
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French (fr)
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CA2467112C (en
Inventor
Klaus Johannes Weber
Andrew William Blakers
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Australian National University
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Individual
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Filing date
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Priority claimed from PCT/AU2001/001546 external-priority patent/WO2002045143A1/en
Application filed by Individual filed Critical Individual
Publication of CA2467112A1 publication Critical patent/CA2467112A1/en
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Publication of CA2467112C publication Critical patent/CA2467112C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Abstract

The invention provides a process for texturing a surface of a semiconductor material, the process comprising: applying a layer of a protective substance on said surface wherein said layer is sufficiently thin that it has a plurality of apertures therethrough; and contacting said layer and said semiconductor material with an etchant capable of etching said semiconductor material faster than said protective substance, said etchant making contact with said semiconductor material at least through said apertures, for a time and under conditions in which said semiconductor material is etched by said etchant in the vicinity of said apertures to produce a textured surface on said semiconductor material, but said protective substance is substantially unetched.

Claims (22)

1. A process for texturing a surface of a semiconductor material, the process comprising:
applying a layer of a protective substance on said surface wherein said layer is sufficiently thin that it has a plurality of apertures therethrough; and contacting said layer and said semiconductor material with an etchant capable of etching said semiconductor material faster than said protective substance, said etchant making contact with said semiconductor material at least through said apertures, for a time and under conditions in which said semiconductor material is etched by said etchant in the vicinity of said apertures to produce a textured surface on said semiconductor material, but said protective substance is substantially unetched.
2. A process according to claim 1, wherein said semiconductor material is silicon and said protective substance is silicon nitride.
3. A process according to claim 1, wherein said protective substance is a polymer.
4. A process according to claim 1, wherein said layer is applied to said surface by low pressure chemical vapour deposition, chemical vapour deposition, spray pyrolysis, evaporation, sputtering, thermal oxidation, thermal nitridation or spin coating.
5. A process according to claim 2, wherein said layer is applied to said surface by low pressure chemical vapour deposition.
6. A process according to claim 5, wherein said layer is about 2nm thick.
7, A process according to claim 2, wherein a layer of silicon dioxide is present between said silicon and said silicon nitride.
8. A process according to claim 3, wherein said etchant is a plasma.
9. A process for texturing a surface of a semiconductor material, the process comprising:
creating a layer of a protective substance on said surface;
substantially uniformly thinning said layer of protective substance until at least some apertures are formed through said layer; and contacting said layer and said semiconductor material with an etchant capable of etching said semiconductor material faster than said protective substance, said etchant making contact with said semiconductor material at least through said apertures, for a time and under conditions in which said semiconductor material is etched by said etchant in the vicinity of said apertures to produce a textured surface on said semiconductor material, but said protective substance is substantially unetched.
10. A process according to claim 9, wherein said semiconductor material is silicon and said protective substance is silicon nitride.
11. A process according to claim 9, wherein said protective substance is a polymer.
12. A process according to claim 9, wherein said layer is applied to said surface by low pressure chemical vapour deposition, chemical vapour deposition, spray pyrolysis, evaporation, sputtering, thermal oxidation, thermal nitridation or spin coating.
13. A process according to claim 10, wherein said layer is applied to said surface by low pressure chemical vapour deposition.
14. A process according to claim 10, wherein a layer of silicon dioxide is present between said silicon and said silicon nitride.
15. A process according to claim 11, wherein said etchant is a plasma.
16. A semiconductor material, at least part of at least one surface of which has a plurality of pits therein wherein said pits are substantially randomly arranged over said part of said at least one surface, and have an interior surface which is at least partially rounded.
17. A semiconductor material, at least part of at least one surface of which has a plurality of pits therein wherein said pits are substantially randomly arranged over said part of said at least one surface, and have a width of up to 10 µm.
18. A semiconductor material according to claim 17, wherein said pits have an interior surface which is at least partially rounded.
19. A semiconductor material according to claim 17, wherein said pits have a width of up to 5 µm.
20. A semiconductor material according to claim 16 or claim 17, which is silicon.
21. A semiconductor material according to claim 20, and having an antireflective coating applied to said at least one surface.
22. A strip of silicon having a thickness of less than 100 µm and a width of up to about 3 mm and wherein each of at least one opposite pair of surfaces has a plurality of pits therein wherein the pits are substantially randomly distributed over said surfaces, and have an interior surface which is at least partially rounded, and/or have a width of up to 10 µm.
CA2467112A 2001-11-29 2002-11-29 Semiconductor texturing process Expired - Fee Related CA2467112C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
AUPCT/AU01/01546 2001-11-29
PCT/AU2001/001546 WO2002045143A1 (en) 2000-11-29 2001-11-29 Semiconductor wafer processing to increase the usable planar surface area
PCT/AU2002/001625 WO2003047004A1 (en) 2001-11-29 2002-11-29 Semiconductor texturing process

Publications (2)

Publication Number Publication Date
CA2467112A1 true CA2467112A1 (en) 2003-06-05
CA2467112C CA2467112C (en) 2010-07-27

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CA2467112A Expired - Fee Related CA2467112C (en) 2001-11-29 2002-11-29 Semiconductor texturing process

Country Status (10)

Country Link
US (1) US7828983B2 (en)
EP (1) EP1461834A4 (en)
JP (1) JP4530662B2 (en)
KR (1) KR20040068928A (en)
CN (1) CN1613155B (en)
CA (1) CA2467112C (en)
IL (1) IL162190A0 (en)
MY (1) MY144264A (en)
WO (1) WO2003047004A1 (en)
ZA (1) ZA200405144B (en)

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IL162190A0 (en) 2005-11-20
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ZA200405144B (en) 2006-03-29
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US20050104163A1 (en) 2005-05-19
JP4530662B2 (en) 2010-08-25
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EP1461834A1 (en) 2004-09-29

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