CA2538610A1 - Wireless receiver with stacked, single chip architecture - Google Patents
Wireless receiver with stacked, single chip architecture Download PDFInfo
- Publication number
- CA2538610A1 CA2538610A1 CA002538610A CA2538610A CA2538610A1 CA 2538610 A1 CA2538610 A1 CA 2538610A1 CA 002538610 A CA002538610 A CA 002538610A CA 2538610 A CA2538610 A CA 2538610A CA 2538610 A1 CA2538610 A1 CA 2538610A1
- Authority
- CA
- Canada
- Prior art keywords
- receiver
- analog
- system bus
- processor
- acquisition module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
- H04B1/26—Circuits for superheterodyne receivers
- H04B1/28—Circuits for superheterodyne receivers the receiver comprising at least one semiconductor device having three or more electrodes
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/24—Acquisition or tracking or demodulation of signals transmitted by the system
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/34—Power consumption
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/35—Constructional details or hardware or software details of the signal processing chain
- G01S19/36—Constructional details or hardware or software details of the signal processing chain relating to the receiver frond end
Abstract
A monolithic wireless receiver (100) suitable for use in a global positioning system (GPS) or other radio frequency (RF) application suitably includes a mixed-mode integrated circuit and a stacked memory device. The mixed mode integrated circuit appropriately includes a digital portion (104) and an analog portion (106) on a common die. The analog portion implements an RF
receiver circuit, and the digital portion includes a signal processor that communicates with the RF receiver. The memory device appropriately communicates with the integrated circuit to store electronic instructions and data for the signal processor. The monolithic receiver may be conveniently integrated into a portable electronics device such as a camera, personal digital assistant (PDA), portable phone or the like to provide location sensing or other RF functionality.
receiver circuit, and the digital portion includes a signal processor that communicates with the RF receiver. The memory device appropriately communicates with the integrated circuit to store electronic instructions and data for the signal processor. The monolithic receiver may be conveniently integrated into a portable electronics device such as a camera, personal digital assistant (PDA), portable phone or the like to provide location sensing or other RF functionality.
Claims (9)
1. A monolithic wireless device, the wireless device comprising:
a mixed-mode integrated circuit having a digital portion and an analog portion on a common die, wherein the analog portion comprises a radio frequency (RF) receiver circuit and wherein the digital portion comprises a signal processor in communication with the RF receiver circuit; and a memory device in electronic communication with the mixed-mode integrated circuit, wherein the memory device is configured to store electronic instructions and data for the signal processor.
a mixed-mode integrated circuit having a digital portion and an analog portion on a common die, wherein the analog portion comprises a radio frequency (RF) receiver circuit and wherein the digital portion comprises a signal processor in communication with the RF receiver circuit; and a memory device in electronic communication with the mixed-mode integrated circuit, wherein the memory device is configured to store electronic instructions and data for the signal processor.
2. The wireless device of claim 1 wherein the RF receiver circuit operates within a frequency band and wherein the digital portion comprises a clock signal having a clock frequency that is provided to the signal processor.
3. The wireless device of claim 5 wherein the clock frequency is configured such that neither the clock frequency nor any harmonics of the clock frequency lie within the frequency band.
4. The wireless device of claim 6 wherein the RF receiver circuit comprises a filter tuned to remove a harmonic of the clock frequency from an analog signal propagating in the analog portion.
5. A monolithic receiver for a global positioning system (GPS), the receiver comprising:
a substrate;
a mixed-mode integrated circuit coupled to the substrate and having a digital portion and an analog portion on a common die, wherein the analog portion comprises an RF receiver circuit operating within a frequency band and wherein the digital portion comprises a signal processor in communication with the RF receiver circuit, wherein the digital portion comprises a clock signal having a clock frequency provided to the signal processor, and wherein the clock frequency is selected such that neither the clock frequency nor any harmonics of the clock frequency lie within the frequency band; and a memory device stacked with the mixed-mode integrated circuit opposite the substrate and configured in electronic communication with the mixed-mode integrated circuit, wherein the memory device is configured to store electronic instructions and data for the signal processor.
a substrate;
a mixed-mode integrated circuit coupled to the substrate and having a digital portion and an analog portion on a common die, wherein the analog portion comprises an RF receiver circuit operating within a frequency band and wherein the digital portion comprises a signal processor in communication with the RF receiver circuit, wherein the digital portion comprises a clock signal having a clock frequency provided to the signal processor, and wherein the clock frequency is selected such that neither the clock frequency nor any harmonics of the clock frequency lie within the frequency band; and a memory device stacked with the mixed-mode integrated circuit opposite the substrate and configured in electronic communication with the mixed-mode integrated circuit, wherein the memory device is configured to store electronic instructions and data for the signal processor.
6. A wireless receiver provided on a common die in communication with an antenna, the wireless receiver comprising:
a system bus disposed on the common die;
an analog portion coupled to the system bus and comprising a radio frequency (RF) receiver circuit configured to receive an analog signal from the antenna and to provide a digital representation of the analog signal therefrom;
an acquisition module configured to communicate with the RF receiver circuit via the system bus and to thereby receive the digital representation of the analog signal, wherein the acquisition module is further configured to process the digital representation to thereby extract data from the analog signal;
a processor coupled to the system bus, wherein the processor is configured to control the RF receiver and the acquisition module, and to process the data from the acquisition module to thereby provide an output of the wireless receiver.
a system bus disposed on the common die;
an analog portion coupled to the system bus and comprising a radio frequency (RF) receiver circuit configured to receive an analog signal from the antenna and to provide a digital representation of the analog signal therefrom;
an acquisition module configured to communicate with the RF receiver circuit via the system bus and to thereby receive the digital representation of the analog signal, wherein the acquisition module is further configured to process the digital representation to thereby extract data from the analog signal;
a processor coupled to the system bus, wherein the processor is configured to control the RF receiver and the acquisition module, and to process the data from the acquisition module to thereby provide an output of the wireless receiver.
7. The wireless receiver of claim 6 further comprising an automatic level control (ALC) module coupling the analog portion to the system bus, wherein the ALC
module is configured to providing blanking and level control to the RF
receiver in response to signals received from the processor via the system bus.
module is configured to providing blanking and level control to the RF
receiver in response to signals received from the processor via the system bus.
8. The wireless receiver of claim 6 further comprising clock generating circuitry configured to produce a system clock signal for the processor and the acquisition module as a function of a selected one of a plurality of external references.
9. A monolithic die for a wireless receiver stacked with a memory and electrically coupled to an antenna, the monolithic die comprising:
a system bus disposed on the die;
an analog portion coupled to the system bus and comprising a radio frequency (RF) receiver circuit configured to receive an analog signal from the antenna and to provide a digital representation of the analog signal therefrom;
an acquisition module configured to communicate with the RF receiver circuit via the system bus and to thereby receive the digital representation of the analog signal, wherein the acquisition module is further configured to process the digital representation to thereby extract data from the analog signal;
a processor coupled to the system bus, wherein the processor is configured to control the RF receiver and the acquisition module, and to process the data from the acquisition module to thereby provide an output of the wireless receiver.
a system bus disposed on the die;
an analog portion coupled to the system bus and comprising a radio frequency (RF) receiver circuit configured to receive an analog signal from the antenna and to provide a digital representation of the analog signal therefrom;
an acquisition module configured to communicate with the RF receiver circuit via the system bus and to thereby receive the digital representation of the analog signal, wherein the acquisition module is further configured to process the digital representation to thereby extract data from the analog signal;
a processor coupled to the system bus, wherein the processor is configured to control the RF receiver and the acquisition module, and to process the data from the acquisition module to thereby provide an output of the wireless receiver.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/665,954 US6952573B2 (en) | 2003-09-17 | 2003-09-17 | Wireless receiver with stacked, single chip architecture |
| US10/665,954 | 2003-09-17 | ||
| PCT/US2004/029488 WO2005029718A1 (en) | 2003-09-17 | 2004-09-09 | Wireless receiver with stacked, single chip architecture |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2538610A1 true CA2538610A1 (en) | 2005-03-31 |
| CA2538610C CA2538610C (en) | 2010-11-16 |
Family
ID=34274693
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2538610A Expired - Fee Related CA2538610C (en) | 2003-09-17 | 2004-09-09 | Wireless receiver with stacked, single chip architecture |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US6952573B2 (en) |
| EP (1) | EP1665555B1 (en) |
| JP (1) | JP2007506363A (en) |
| KR (1) | KR100805090B1 (en) |
| CN (1) | CN1853354A (en) |
| BR (1) | BRPI0414452A (en) |
| CA (1) | CA2538610C (en) |
| MX (1) | MXPA06003114A (en) |
| WO (1) | WO2005029718A1 (en) |
Families Citing this family (28)
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| US7626958B2 (en) * | 2002-12-05 | 2009-12-01 | The Boeing Company | Serial port multiplexing protocol |
| TWM262853U (en) * | 2004-09-07 | 2005-04-21 | Inpaq Technology Co Ltd | Integrated active satellite antenna module |
| US7502625B2 (en) * | 2005-01-20 | 2009-03-10 | Skyworks Solutions, Inc. | Integrated multi-band transceiver for use in mobile communication device |
| GB2422483B (en) * | 2005-01-21 | 2008-04-16 | Artimi Ltd | Integrated circuit die connection methods and apparatus |
| JP2009515247A (en) * | 2005-11-02 | 2009-04-09 | エヌエックスピー ビー ヴィ | System on chip device having time shareable memory and control method thereof |
| JP4534962B2 (en) * | 2005-11-16 | 2010-09-01 | ソニー株式会社 | Information recording apparatus, non-contact recording medium and recording method therefor |
| US7352602B2 (en) * | 2005-12-30 | 2008-04-01 | Micron Technology, Inc. | Configurable inputs and outputs for memory stacking system and method |
| US20070231970A1 (en) * | 2006-03-31 | 2007-10-04 | Tsuyoshi Fukuo | Cured mold compound spacer for stacked-die package |
| US8326242B2 (en) * | 2006-12-20 | 2012-12-04 | Broadcom Corporation | On-chip power management for a mobile communication device and method for use therewith |
| US20090154615A1 (en) * | 2007-02-16 | 2009-06-18 | Katsumasa Hijikata | Integrated circuit for processing multi-channel radio signal |
| US8351982B2 (en) * | 2007-05-23 | 2013-01-08 | Broadcom Corporation | Fully integrated RF transceiver integrated circuit |
| US7743177B2 (en) * | 2007-06-29 | 2010-06-22 | Sirf Technology Holdings, Inc. | High sensitivity global navigation satellite system (GNSS) receiver platform having DMA controller for transferring between internal and external memory |
| US8005444B2 (en) * | 2007-08-02 | 2011-08-23 | Broadcom Corporation | Multiple die integrated circuit assembly |
| JP4569609B2 (en) | 2007-08-22 | 2010-10-27 | 株式会社デンソー | Wireless receiver |
| US8106505B2 (en) * | 2007-10-31 | 2012-01-31 | International Business Machines Corporation | Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly |
| US8250441B2 (en) | 2007-12-11 | 2012-08-21 | Wi-Lan Inc. | Outer coding framework for application packet error rate minimization |
| US8145171B2 (en) * | 2008-10-08 | 2012-03-27 | Qualcomm Incorporated | Clock clean-up phase-locked loop (PLL) |
| US8224279B2 (en) | 2009-12-18 | 2012-07-17 | Silicon Laboratories, Inc. | Radio frequency (RF) receiver with dynamic frequency planning and method therefor |
| US8874060B2 (en) * | 2009-12-18 | 2014-10-28 | Silicon Laboratories Inc. | Radio frequency (RF) receiver with frequency planning and method therefor |
| US8736306B2 (en) | 2011-08-04 | 2014-05-27 | Micron Technology, Inc. | Apparatuses and methods of communicating differential serial signals including charge injection |
| EP2984762A4 (en) * | 2013-04-09 | 2016-12-07 | Sierra Wireless Inc | Integrated radio communication module |
| US10228469B2 (en) * | 2014-02-24 | 2019-03-12 | Sony Semiconductor Solutions Corporation | Reception device |
| JP2021501543A (en) * | 2017-10-30 | 2021-01-14 | ビーエイイー・システムズ・インフォメーション・アンド・エレクトロニック・システムズ・インテグレイション・インコーポレーテッド | Dual band GPS / IFF antenna |
| WO2019151960A1 (en) * | 2018-01-30 | 2019-08-08 | Aselsan Elektroni̇k Sanayi̇ Ve Ti̇caret Anoni̇m Şi̇rketi̇ | A chip structure |
| US10782759B1 (en) | 2019-04-23 | 2020-09-22 | Arbor Company, Lllp | Systems and methods for integrating batteries with stacked integrated circuit die elements |
| US10802735B1 (en) | 2019-04-23 | 2020-10-13 | Arbor Company, Lllp | Systems and methods for reconfiguring dual-function cell arrays |
| JP7064060B1 (en) * | 2019-04-23 | 2022-05-09 | アーバー・カンパニー・エルエルエルピイ | Systems and methods for reconstructing dual-function cell array |
| WO2022005743A1 (en) | 2020-06-29 | 2022-01-06 | Arbor Company, Lllp | Mobile iot edge device using 3d-die stacking re-configurable processor module with 5g processor-independent modem |
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-
2003
- 2003-09-17 US US10/665,954 patent/US6952573B2/en not_active Expired - Lifetime
-
2004
- 2004-09-09 CN CNA2004800268043A patent/CN1853354A/en active Pending
- 2004-09-09 WO PCT/US2004/029488 patent/WO2005029718A1/en active Application Filing
- 2004-09-09 CA CA2538610A patent/CA2538610C/en not_active Expired - Fee Related
- 2004-09-09 KR KR1020067005473A patent/KR100805090B1/en active IP Right Grant
- 2004-09-09 JP JP2006526941A patent/JP2007506363A/en active Pending
- 2004-09-09 BR BRPI0414452-0A patent/BRPI0414452A/en not_active IP Right Cessation
- 2004-09-09 MX MXPA06003114A patent/MXPA06003114A/en not_active Application Discontinuation
- 2004-09-09 EP EP04816213.5A patent/EP1665555B1/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| EP1665555A1 (en) | 2006-06-07 |
| KR20060064677A (en) | 2006-06-13 |
| KR100805090B1 (en) | 2008-02-20 |
| JP2007506363A (en) | 2007-03-15 |
| CA2538610C (en) | 2010-11-16 |
| EP1665555B1 (en) | 2018-12-05 |
| EP1665555A4 (en) | 2013-07-10 |
| BRPI0414452A (en) | 2006-11-14 |
| CN1853354A (en) | 2006-10-25 |
| US6952573B2 (en) | 2005-10-04 |
| US20050059377A1 (en) | 2005-03-17 |
| WO2005029718A1 (en) | 2005-03-31 |
| MXPA06003114A (en) | 2006-06-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |
Effective date: 20210909 |