CN100355058C - 具有连续沉积和蚀刻的电离pvd - Google Patents

具有连续沉积和蚀刻的电离pvd Download PDF

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CN100355058C
CN100355058C CNB02812085XA CN02812085A CN100355058C CN 100355058 C CN100355058 C CN 100355058C CN B02812085X A CNB02812085X A CN B02812085XA CN 02812085 A CN02812085 A CN 02812085A CN 100355058 C CN100355058 C CN 100355058C
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ipvd
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图鲁尔·雅萨尔
格林·雷诺兹
弗兰克·切里奥
布鲁斯·吉托曼
迈克尔·格拉佩豪斯
罗德尼·罗比森
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Tokyo Electron Ltd
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Abstract

一种iPVD设备(20)通过在真空室(30)内循环执行沉积和蚀刻模式，将材料(10)沉积到半导体基片(21)上高形状比的亚微米结构(11)中。这些模式工作在不同的功率和压力参数下。例如大于50mTorr的压力用于从靶上溅射材料，而小于几mTorr的压力例如用于蚀刻。蚀刻时对基片的偏压功率要高一个数量级，蚀刻时产生几百伏偏压而沉积时仅有几十伏。交替执行的蚀刻模式去除基片上结构突出边缘的沉积材料，去除结构底部(15)一些沉积材料，将去除的沉积材料重新溅射到结构的侧壁(16)上。基片(21)在沉积和蚀刻过程中冷却，特别是蚀刻过程中冷却到明显低于0℃。RF能量耦合到室(30)内形成高密度等离子体，沉积期间耦合的RF功率明显高于蚀刻期间的。基片(21)在蚀刻过程比在沉积过程更靠近等离子体源。

Description

具有连续沉积和蚀刻的电离PVD
本发明要求2001年5月4日提交的美国临时专利申请No.60/288952的优先权，该申请在下面引用作为参考文献。
发明领域
本发明涉及半导体晶片上通过和线槽结构的金属化。更具体地，本发明涉及硅片上高形状比通过和线槽结构的金属化，其中利用离子溅射材料形成阻挡层和种子层。
背景技术
对于半导体晶片高形状比通孔和线槽的金属化，需要阻挡层和种子层具有好的侧壁和底面覆盖。阻挡层在不牺牲阻挡性能的条件下应尽可能的薄。阻挡层必须薄，因为其电阻与沟道结构的电阻迭加在一起，必须达到最小。阻挡层需要保持形状并且连续，用以防止种子层材料扩散到介电层以及其它层中，从而防止与可靠性有关的问题。这需要很好地控制阻挡层的厚度并且特别是在沟道结构的底部达到最小程度。沟道结构底部的厚的阻挡层，会对互连金属化物质的电阻明显增加不希望的电阻。高的接触电阻导致差的IC性能。在阻挡层沉积期间，在沟道结构入口的顶边缘，由于较厚的材料堆积在此而形成突出。这种突出干扰种子层在侧壁和沟道结构底部上的沉积。在种子层沉积期间，必须防止种子层材料本身形成突出。
种子层必须是连续的并且对侧壁和沟道结构底部有好的覆盖。这对于阻挡层和种子层沉积后的电镀步骤是关键的。沟道结构入口被突出闭合将导致差的侧壁覆盖、差的电镀填充和低的装置产量。
电离PVD(物理汽相沉积)沉积用于先进IC晶片的阻挡层和种子层金属化。电离PVD使通过和线槽结构形成好的侧壁和底部覆盖。但是，随着几何收缩以及通孔尺寸小于0.15微米，电离沉积的需求变得更迫切。因此，非常需要电离PVD工艺，使底部和侧壁覆盖很好平衡并使突出最小。
连续沉积和蚀刻工艺先前已经提出了。在美国专利6100200中，Van Buskirk等人给出了一种连续执行的加热沉积和蚀刻工艺，对通过或线槽结构提供保形覆盖。但是，他们提出的沉积和蚀刻工艺在300-600℃的高基片温度下，通常是500-450℃。不幸的是，当前半导体工艺中所用的新型现代低K电介质需要温度＜200℃。Cu种子层的沉积需要＜0℃，通常是-20℃到-50℃，用以防止铜聚合。Van Buskirk等人给出的温度将导致Cu种子层的全部聚合、通过和线槽结构的突出和闭合，出现大岛状的Cu和不连续的Cu层。Van Buskirk等人还给出低功率溅射，通常小于1kW，特别是小于0.5kW。这严重影响了工艺的沉积速率和产量。
并且，Van Buskirk等人提出了在一个单独真空系统中，通过在专门的沉积和蚀刻组件之间输送晶片，执行连续沉积和蚀刻步骤；或者在一个单独的真空系统中使用多面沉积和反应离子蚀刻组件。另外，Van Buskirk等人建议上述可以在独立的沉积和蚀刻系统中进行。晶片从一个蚀刻室输送到另一个沉积室，或者在相同组件中从一个蚀刻站输送到另一个沉积站，具有工艺成本高和工艺质量问题的缺点。通过将晶片从一个室输送到另一个室或者在相同室内从一个站输送到另一个站，导致生产量降低，从而工艺成本高。有些工艺对输送期间气体分子或其它污染物的吸附敏感，这损坏正在建造的装置的质量和可靠性。Van Buskirk等人的另一项建议是在独立系统中执行沉积和蚀刻步骤，在步骤之间将暴露在空气中，这对于大多数现代阻挡层/种子层金属化工艺是完全不能接受的。Van Buskirk等人也没有给出沉积步骤中任何的基片选择。
在美国专利4999096中，Nikel等人给出在相同室中进行连续沉积和蚀刻时用于溅射的方法和设备。Nikel等人对靶和基片施加负电压，执行薄膜沉积和反溅射。他们在处理模块内部、靶与基片之间提供一个RF线圈，在蚀刻步骤产生等离子体。这种结构的明显不足在于，内部线圈是一个污染源，因为处理空间中存在的高能离子和中子也将线圈的材料去除，即蚀刻，并污染基片上沉积或蚀刻的薄膜，这在本领域内是公知的。在其它先前技术中，线圈由与沉积的材料相同的材料制成的，但这对工艺产生过高的成本和硬件的难度。并不是每种沉积材料都能制成线圈，大多数情况下成本成为阻碍因素。并且，Nikel等人的建议将导致不均匀等离子体的产生以及基片的不均匀蚀刻。在连续蚀刻和沉积工艺中关键是两个步骤在整个晶片上均匀进行，从而在工艺结束后得到均匀处理的晶片。
Nikel等人严格地提出并强调低压沉积和蚀刻工艺，防止杂质进入沉积的薄膜中。这是通过在蚀刻和沉积过程中在低压下产生等离子体实现的，例如10-3torr或更低。在蚀刻过程，内线圈需要RF供电完成放电，这与他们希望防止基片的污染是相反的，现在却成了基片的污染源。Nikel等人严格地提出并限制他们的发明在低压下(10-3torr或更低)操作。
美国专利6274008提出一个集成的铜填充工艺，其中同时执行清洁-沉积步骤。此发明在铜种子层沉积之前使用铜离子清洁和/或蚀刻沟道结构的底部。
发明内容
根据本发明原理，提供一种工艺和设备，其中使用连续沉积和蚀刻步骤解决上述问题。本发明的工艺包括首先沉积一薄层金属，例如钽(Ta)、氮化钽(TaN)或铜(Cu)，接着，优选地，在沉积停止后执行离子蚀刻步骤，优选地是通过电离的气体，如氩气(Ar)。
根据本发明的一方面，提供了一种iPVD(电离物理气相沉积)工艺，包括：在一iPVD设备的室内将一基片密封，并且不打开室执行iPVD工艺，通过操作设备工作在沉积模式、接着工作在蚀刻模式下，在基片上具有直径0.15微米或更小直径以及纵横比为3或更大的半导体结构的表面上沉积一层导电材料，所述模式的改变是通过控制所述设备工作的功率，使该功率在沉积模式中与在蚀刻模式中不同，其特征在于蚀刻模式之后执行另一个沉积模式，并且两个沉积模式都沉积导电材料，还控制所述设备操作的压力参数，使压力在沉积模式与在蚀刻模式不同。
根据本发明的另一方面，提供了一种iPVD设备，包括：真空室，用于在从0.1mTorr到100mTorr以上的压力范围内，在基片上进行电离物理气相沉积；位于室一个末端的环形靶和位于室另一端的基片支承台；位于靶中央的三维线圈，与RF能量源耦合并有效地将RF能量感应耦合到室内，从而在其中形成高密度等离子体；及编程后操作设备的控制器，其特征在于控制器编程后操作设备在以下步骤之间切换：操作设备工作在足够高的压力，使从靶溅射到等离子体内的材料热能化，并将材料从溅射靶溅射到等离子体中使材料电离，并以垂直于晶片的方向将材料沉积在晶片上；以及操作设备工作在比等离子体中粒子热能化的压力低的压力，并且不从靶上溅射材料，从基片上蚀刻沉积的材料，使基片上结构的突出边缘沉积的材料去除，将结构底部的材料重新溅射到结构侧壁上。
蚀刻步骤在晶片顶面和沟道结构底部的场区上去除的材料，比沉积过程沉积的材料少。这样，在此工艺循环结束时有净沉积产生。沉积/蚀刻循环可以重复所需的次数，直到达到所需的结果。通过平衡沉积和蚀刻时间、速率和其它沉积和蚀刻参数，可以消除突出的生长或使其最小化。突出和底部沉积被蚀刻并且至少部分重新分配到侧壁上。
在根据本发明一个实施例的工艺中，材料沉积在小的、具有高形状比特征的晶片上，例如直径为0.15微米或更小的孔或沟道结构，其形状比从3或5到15或更高的。沉积使用电离物理气相沉积(iPVD)工艺和设备，它们具有如美国专利5287435、6080287、6197165、6132564、5948215和5800688以及PCT申请PCT/US00/31756所述的特征，至少是部分根据它们。所有这些在此引用作为参考文献。
本发明的一个实施例利用图1所示美国专利6287435和PCT申请PCT/US00/31756详细描述的电离PVD设备的独特优点。这种设备特别适合连续沉积和蚀刻工艺。连续沉积和蚀刻工艺可以在同一个工艺室中应用到基片上，而不必去除真空或将晶片从一个室输送到另一个室。设备的结构允许从电离PVD沉积模式快速切换到蚀刻模型，或者从蚀刻模式切换到电离PVD沉积模式。设备的结构还允许即时优化沉积模式中的电离PVD沉积工艺控制参数和蚀刻模式中的蚀刻工艺控制参数。这些优点使得晶片产量高，并使晶片具有优异的沟道结构金属化和随后的电镀填充操作。
本发明除了基片温度低外，还具有高的DC靶功率，例如8～19kW，通常为11kW。高的功率不但使工艺的产量高，而且优化电离和金属物质的电离沉积，例如Cu或Ta。
本发明通过在同一室中原位的连续蚀刻和沉积步骤，得到高的产量并没有Van Buskirk等人的工艺中出现的界面层，由此本发明解决了先前技术的问题。
本发明的处理组件的结构适应宽范围的压力，在高晶片产量水平下得到保形的通过和线槽覆盖。本发明没有Nikel等人的低压限制，并利用设备能力提供对工艺的溅射和蚀刻步骤优化的处理压力。并且，先前技术没有对每个步骤提供优化的源-基片距离的沉积-蚀刻循环，用以增大最终薄膜的均匀性。
美国专利6247008没有提供连续蚀刻和沉积方案，并限制金属离子作为清洁元素。
从本发明图示实施例的详细描述中，本发明的上述和其它目的和优点将更加清晰。
附图说明
图1是半导体晶片一部分的剖视图，表示iPVD金属沉积的机理；
图2是图1中半导体晶片一部分的剖视图，表示通过蚀刻沉积金属重新溅射的机理；
图3是本发明使用的iPVD设备的一个实施例的剖视图；
图3A是与图3相似的、本发明使用的iPVD设备的另一个实施例的剖视图；
图3B是与图3和图3A相似的、本发明使用的iPVD设备的又一个实施例的剖视图；
图4是根据本发明一个实施例在连续沉积和蚀刻工艺过程中参数转换的曲线；
图5是根据本发明一个实施例在连续沉积和蚀刻工艺过程中参数变化的曲线；
图5A和5B是详细表示图5中选出的一部分的曲线；
图6表示图3、3A或3B设备的一部分控制系统；
图7和7A表示图3、3A或3B设备的部分备选的气流控制系统。
具体实施方式
图1表示通过iPVD在半导体晶片12的介电中间层13中的沟道结构11中沉积金属膜10。随着金属离子18沉积在晶片12上，金属沉积易于在沟道结构入口增厚，形成突出结构14。同样地，金属在沟道结构11底部15比侧壁16沉积得厚。随着沟道结构尺寸减小到0.15微米以下，而介电中间层13的厚度并不减小时，沟道结构11的形状比将明显增大，限制了到达沟道结构11的侧壁16上的金属离子流14。对于小于100的较薄沉积，在沟道结构11的侧壁16上沉积的薄膜，特别是对于诸如铜的金属种子层，趋于形成团聚的岛状结构。铜种子层中的间隙和不连续性导致侧壁16上，尤其是侧壁底部，形成电镀空隙，在此处金属覆盖最少。
图2表示蚀刻循环，从沟道结构11的底部16以及从沟道结构11顶部的突出结构14上重新溅射金属沉积10。在蚀刻循环中，氩离子(Ar+)冲击沉积层10上的物质并将其溅射，如箭头19所示。溅射在沟道结构底部16和突出14上去除过剩物质。当金属层是铜时，蚀刻通过将沟道结构底部16和沟道结构入口的突出14上溅射的Cu重新沉积，提高铜在底部16和侧壁16顶部的连续性。如果被蚀刻的金属是阻挡层，则沟道结构底部16厚度的减小使沟道结构的总接触电阻减小，并提高装置的性能。
沉积和蚀刻循环参考图3所示的iPVD设备20进行说明。对于电离PVD，晶片21固定在温控的静电卡盘22的顶部。溅射气体由源23进入真空处理室30，其压力通过泵29保持真空并被调节到适当的iPVD的电离沉积范围。DC电源从电源24提供到靶25，RF电源通过天线26由RF发生器27提供。这些电源24和27设定到适于iPVD沉积的功率大小。晶片RF偏压通过RF偏压发生器28施加在卡盘22上，这也可以在沉积过程中设定到适当大小，对晶片21输出净的负偏压，改善和影响过程。天线26位于室30的外部，在室壁32上介电窗口31的后面。窗口沉积挡板33，优选地由槽形金属材料制成，位于室30内部，紧靠窗口31，防止窗口31被沉积。永磁块34位于靶25后面，为靶25提供磁通道用于磁控溅射。
为使沟道结构最好地金属化，应控制晶片21的温度。晶片台22装有Z运动驱动器35，用于调节基片-源距离得到最好的沉积均匀性、沟道结构11侧壁16和底部15的最好覆盖和对称性。表1列出一些典型的电离PVD沉积参数。
表1
典型的电离PVD沉积参数
材料  DC功率(kW)  ICP功率(kW)  RF晶片偏压功率(W)  压力(mT)  N2流量(总流量的百分数，％)  晶片台温度(℃)
 Ta  8-19  1-7  0-200  50-120  -  25-100
 TaNx  8-19  1-7  0-200  50-120  3-50  25-100
 Cu  8-19  1-7  0-100  50-100  -  -50-0
对于表1列出的工艺，基片-源距离通常是150～275mm。氩气是典型的溅射气体。为了沉积金属氮化物如TaNx的阻挡层，在溅射沉积过程中，除了氩气以外还需要氮气。
在沉积到所需数量后，减小或关闭供给靶25的DC电源24，明显降低或停止沉积过程。本领域一般技术人员意识到，通过将DC电源24降低到非常低的程度而不是完全关闭，可以显著减小和/或停止沉积过程。保持ICP天线的RF激励，用于连续产生氩气等离子体。此时，调节室内氩气压力、ICP功率、RF基片偏压功率和基片-源距离，从而达到最佳的蚀刻条件。如果先前沉积步骤用于金属氮化物，则可以关闭或减小室的氮气流量。晶片台22的温度对于蚀刻步骤也要修改，但通常不是必需的。典型的蚀刻条件列于表2。
表2
金属和金属氮化物的典型蚀刻工艺参数
    ICP功率(W)     RF晶片偏压功率(W)     压力(mT)
    50-3000     100-1000     0.1-2
在先前技术的工艺中，种子金属层的团聚是常见的，这将导致在种子层上沉积的电镀填充物中出现空隙，由此生产出不能令人接受的、具有可靠性问题的产品。
根据本发明，在连续沉积和蚀刻步骤中都控制晶片温度。这些过程可以在美国专利6287435中描述的设备中实现，其中提供的静电卡盘22具有冷却液通道和恰当的温度控制。卡盘22与晶片21之间好的热接触可以通过在晶片21与卡盘22之间提供背面气体传导来实现。背面气体压力在沉积和蚀刻步骤都得到控制，以保证薄的金属沉积不发生团聚，特别是在沟道结构的侧壁上。
在蚀刻步骤，特别是对于铜沉积-蚀刻工艺，铜膜必须保持冷态，在蚀刻步骤不允许加热，其中高能离子在较高基片偏压的影响下撞击到基片上。蚀刻步骤的目的是减小对成功制成沟道结构或线槽填充有害的突出的数量，以及减小底部覆盖的厚度。蚀刻步骤的目的还在于，使沟道结构的侧壁和线槽重新沉积更多的材料，从而使此处的膜更加连续。如果在蚀刻步骤不控制基片21的温度并允许升高，则铜原子的运动能力增大并且它们扩散到基片21的表面，导致在沟道结构和线槽11的侧壁16聚集大的铜核，而不是形成连续铜膜。因此，在蚀刻步骤应控制基片温度并保持冷态。
例如，在蚀刻期间，来自偏压源发生器28的晶片台22的功率保持在约500W，使得约-300V偏压施加在晶片台22上。这种蚀刻步骤在基片21上产生的热量被晶片台22有效地吸收，保持晶片21的温度明显低于室温，优选地低于0℃，优选地为-30℃。
蚀刻步骤之后，可以执行另一个沉积步骤。沉积后接着蚀刻的循环可以重复一次，或者重复所需的次数。在另一个实施例中，在整个工艺中可以至少使用一次蚀刻步骤。例如，这个蚀刻过程出现于两次沉积步骤之间。在本发明工艺的一个实施例中，典型的阻挡过程可以包括氮化钽的沉积，接着是一个蚀刻步骤，然后是另一个金属钽沉积步骤，再是另一个蚀刻步骤。沉积步骤得到的沉积材料厚度大于蚀刻期间去除的厚度，从而获得净的沉积。
在一个序列的操作中，每个循环可以具有固定的沉积参数和固定的蚀刻参数，例如每个沉积步骤和蚀刻步骤具有固定的时间、压力、DC和RF功率以及源-基片距离。这种操作序列的一个例子表示在图4中，其中打开从电源24到靶25的DC电源用于沉积，关闭用于蚀刻。通过控制泵29和气流入口23，氩气真空压力在沉积的较高压力与蚀刻的较低压力之间切换。从RF发生器27到天线26的ICP电源在沉积的较高功率与蚀刻的较低功率之间切换。从发生器28到台22的RF偏压源在沉积的较低偏压与蚀刻的较高偏压之间切换。Z驱动器35移动台22，使晶片蚀刻时比沉积时更靠近源(包括靶25和天线26)。
在执行本发明工艺的系统的另一个操作序列中，相对部分的沉积和蚀刻步骤，以及它们的各个工艺参数，可以在各个循环的循环期间进行改变，用于达到最佳的综合结果。图5表示这种序列的一个例子，其中各条曲线相互迭加，以便更好地表示其时间关系。执行这个工艺实施例的系统的优点在于，它允许从沉积模式快速切换到蚀刻模式。设备能在高压下获得均匀沉积(这具有其本身的优点)以及在低压下获得均匀蚀刻的能力，便于在高产量下达到所需的结果。美国专利6287435和PCT申请PCT/US00/31756中给出的设备的iPVD源，表现出达到晶片的均匀的或较高方向性的金属流。这种的源包括截头圆锥靶或环形靶，RF线圈在介电窗口后方在靶的中心上。使用这种源，在某些情况下，到达晶片的正氩离子流可以是不均匀的，并且中央较弱，围绕垂直基片的线出现宽的环形分布。这适合于较高压力的沉积。但在循环的沉积部分过程中沉积的材料的蚀刻部分期间的重新溅射，晶片中央比边缘强，这对于所执行的蚀刻是不希望的。在溅射蚀刻步骤过程中降低压力将导致到达晶片的正氩离子流变得更加均匀，并且在晶片偏压的帮助下，更加指向并垂直基片。为控制等离子源-晶片距离调节Z距离，能产生最佳的蚀刻和沉积均匀性。
在蚀刻步骤过程中降低压力具有另外的优点。在较高压力下，例如在具有上述iPVD源的循环的沉积部分通常使用的压力，从晶片上溅入等离子体中的物质，经过多次碰撞并可能以电离态反射回到晶片上。这种热能化的物质流能增大突出。这种突出通过沉积-蚀刻iPVD工艺减小，因为在较低压力下，从晶片上溅射的物质的平均自由程较长，在其电离或撞击到室30的壁31之前不大可能反射回到晶片上。理想地，沉积-蚀刻循环应当快速，从而在典型的60秒处理时间内有更多次数的循环。具有可变工作循环的脉冲DC电源很理想地适合于这个目的。基片-源距离与图4中所示的相似。
在图5中，“ICP电源”是指来自发生器27的RF感应耦合电源，用于形成稠密等离子体，而“RF基片偏压源”是指从发生器28应用到台22的RF电源，便于对基片21产生负偏压。“DC电源”是指从电源或源24施加到靶25上的DC电源，用于使材料溅射。参数是可以控制的，从而在较高压力沉积步骤中点燃的等离子体，在整个蚀刻步骤中保持连续。图5表示系统操作的实际数据，其中不是这种情况，并且在蚀刻步骤之前增大氩气流，重新点燃等离子体。等离子体的重新点燃对应于图5中RF基片偏压源的明显尖峰。图5A和5B是为了清晰起见，将图5的参数曲线分开显示。
系统控制器40编程后达到图4和图5所示的参数控制，并示于图6中。
本发明的工艺在应用于上述的设备20时特别有优势，其中在宽压力范围内沉积物质，特别是金属，这包括沉积压力的范围为1-150mTorr或更高，并且当压力处于50-150mTorr的范围内时特别有用，或者在其它压力下溅射物质在靶和基片之间经历很多次碰撞，或者被“热能化”。
设备20的优点还在于能在宽RF台功率范围内沉积，这允许在非常高的台功率下沉积。在所有侧壁和底部物质(至少对于阻挡层)被去除之前，低的台功率处理与蚀刻结合仅能去除部分突出。高的台功率沉积工艺得到高的底部覆盖和厚的底部侧壁沉积，以及较好的沟道结构其余部分的侧壁覆盖，从而允许蚀刻步骤一直执行到突出被更彻底地去除。这些优点的出现是由于在晶片21上形成充分高的DC偏压，在更垂直于晶片21的方向上沉积并影响离子轨迹的同时重新溅射。这增强了底部15的覆盖，并允许在底部物质去除之前更多蚀刻突出。利用优化台功率和沉积压力的能力，由重新溅射物质重新沉积而在高台功率沉积过程中造成的突出增大可以减小到最低程度，允许通过蚀刻过程将突出全部减小。
沉积/蚀刻循环的进行，优选地是通过在高沉积压力和低于10mTorr的较低蚀刻压力之间快速和重复切换，特别是从几mTorr下降到0.1mTorr或更低的蚀刻压力。压力切换执行的同时，将溅射电源切换到靶上，并将基片上的偏压源在不同大小之间切换。基片偏压可以通过基片上RF电源的脉动进行转移或切换。优选地，基片偏压可以在两种大小的RF电源之间切换。基片偏压切换在基片上产生相对等离子体的负电势，在沉积期间为几十伏，在蚀刻期间超过100伏，同时靶DC偏压在沉积期间的负靶溅射电压与蚀刻期间的零或接近零伏之间切换。蚀刻期间的偏压源优选地是沉积期间的数量级大小或大于沉积期间。
切换优选地在每个循环约1秒的循环中，或者在每个循环0.1～20秒的范围内，使每个晶片的处理时间优选地在1分钟或小于1分钟的范围内，但是也存在一些处理时间较长的工艺。
根据本发明的另一个实施例，在循环的蚀刻过程中到达晶片的正氩离子流是均匀的或有方向性的，如同循环的沉积过程中来自iPVD源的金属流。这是通过用另一个螺线管线圈41环绕上述室达到的，其中线圈41可以位于室30的内部，如图3A所示；或者等离子体的外部。使用这种线圈41，正氩离子流能更加均匀地垂直基片21。这种包括线圈41和天线26的双线圈系统可输入脉冲，使沉积过程中在基片表面上沉积少到几个单层，接着中断沉积，产生从沟道结构11的顶角14和底部15溅射物质的作用，在这些部位沉积了较多的物质，溅射的物质沉积到侧壁16上，侧壁16沉积的物质少，但此处的覆盖是最关键的(见图1)。
另一个可供选择的结构40包括圆锥形的ICP源44，在其中心具有常规的平面磁控管。中心包括靶45，在其后面是磁体组件46，如图3B所示。源44包括室43外部的圆锥形线圈47，它位于室壁42中的介电窗口48后面，圆锥形沉积挡板49用于避免窗口48产生沉积。
上述结构运行时，沉积金属时的压力可以高于蚀刻时的压力。对于这种可能性，可以从室输出快速波。这可以利用图7所示的抽吸方案。
图3、3A和3B所示的室可以装有节流闸阀50和涡轮泵，如图7所示。对于节流闸阀50不能控制所需传导范围的情况下，图7A的泵结构可以用于并行的旁路52，用于增大传导范围。
溅射沉积和蚀刻之间的压力差异也通过改变气体流入溅射室的流速来达到。也可以综合使用气流变化或泵速变化。
气体可以是氩气，这通常是优选的气体，也可以是任何其它惰性气体，或者其它适合于工艺的非惰性气体。
溅射材料可以是铜、钽或任何其它金属、介电材料，对于不导电的靶或半导体材料，还需使用RF电源。
为了克服高的接触电阻，重新溅射沟道结构底部的阻挡层的厚沉积，例如Ta、TaN、TiN和Ti，是非常有用的，因为高的接触电阻是由底部这些材料的厚沉积引起的。
使用导体材料，例如铜，沉积在阻挡层材料上时，从边缘重新溅射物质，避免这些突出物造成的、对沟道结构内部的遮挡，有效防止在随后的电镀过程中沟道结构的颠倒填充。
蚀刻过程中氩离子的方向性可以控制，从而便于将沟道结构边缘重新溅射到沟道结构上半部或部分的侧壁上，从沟道结构底部溅射到沟道结构下半部或部分的侧壁上。
本发明可以应用于沉积过程是反应过程的情况下，例如，用于沉积化合物膜的过程，如TiN、TaN、SiN等。在这些情况下，在沉积过程中，除了氩气以外，还将N2或其它一些反应气体通入室内。
RF电源频率可以选择，以使系统和工艺得到最佳结果。典型的频率可以是13.56MHz或2MHz，但不限于这些频率。
本领域的一般技术人员将会认识到，在不偏离本发明原理的条件下，可以对上述实施例做出删节、增添或修改。

Claims (17)

1.一种iPVD工艺，包括：在一iPVD设备的室内将一基片密封，并且不打开室执行iPVD工艺，通过操作设备工作在沉积模式、接着工作在蚀刻模式下，在基片上具有直径0.15微米或更小直径以及纵横比为3或更大的半导体结构的表面上沉积一层导电材料，所述模式的改变是通过控制所述设备工作的功率，使该功率在沉积模式中与在蚀刻模式中不同，其特征在于蚀刻模式之后执行另一个沉积模式，并且两个沉积模式都沉积导电材料，还控制所述设备操作的压力参数，使压力在沉积模式与在蚀刻模式不同。
2.如权利要求1所述的iPVD工艺，其中执行iPVD工艺包括：在室内形成高密度等离子体并产生离子，用于将材料沉积到基片上以及用于蚀刻基片；操作设备工作在沉积模式下，其中压力至少50mTorr，同时将材料从靶上溅射到高密度等离子体中以便将材料电离，并将电离的材料以垂直于基片的方向沉积到基片上；操作设备工作在蚀刻模式下，压力小于10mTorr，基片的偏压大小超过100V，不从基片上溅射材料。
3.如权利要求2所述的iPVD工艺，还包括操作设备工作在沉积模式同时对基片施加偏压，其中所述偏压的大小小于蚀刻模式期间对基片施加的偏压。
4.如任何一项上述权利要求所述的iPVD工艺，还包括：当从沉积模式切换到蚀刻模式时，增大对基片的偏压功率，以便通过等离子体中的气体离子，使沉积材料的蚀刻模式过程中对基片产生净的蚀刻作用；以及当从蚀刻模式切换到沉积模式时，减小对基片的偏压功率，从等离子体中吸引电离的材料，在基片上形成净的材料涂层。
5.如权利要求4所述的iPVD工艺，其中：蚀刻模式期间的基片偏压功率的数量级大小等于或大于沉积模式期间的基片偏压功率的数量级大小。
6.如权利要求1-3中任一项所述的iPVD工艺，其中：蚀刻模式执行时是通过使用等离子体中的离子溅射，溅射的参数产生如下一组效果中选择的至少一种效果，所述组主要包括：至少部分去除基片结构上的突出边缘的沉积材料；至少部分去除结构底部的沉积材料；以及将沉积的材料从基片上重新溅射到结构的侧壁。
7.如权利要求6所述的iPVD工艺，其中：蚀刻模式执行时是通过使用等离子体中的离子溅射，溅射的参数产生所述效果中的至少两种。
8.如权利要求6所述的iPVD工艺，其中：蚀刻模式执行时是通过使用等离子体中的离子溅射，溅射的参数产生所有三种所述效果。
9.如权利要求1-3中任一项所述的iPVD工艺，还包括：在沉积和蚀刻期间冷却基片。
10.如权利要求9所述的iPVD工艺，还包括：在蚀刻期间将基片冷却到低于0℃。
11.如权利要求1-3中任一项所述的iPVD工艺，还包括：在沉积期间打开溅射靶的DC电源，并在蚀刻期间关闭。
12.如权利要求1-3中任一项所述的iPVD工艺，还包括：由室外部的RF发生器输出的RF能量在室内形成高密度等离子体。
13.如权利要求1-3中任一项所述的iPVD工艺，还包括：在室内一个空间形成高密度等离子体，产生在沉积模式沉积到基片上的涂层材料的离子，以及产生在蚀刻模式蚀刻基片的离子；并在沉积模式将基片定位在相对于所述空间的一个位置上，在蚀刻模式将基片重新定位在相对于所述空间的另一个位置上。
14.如权利要求13所述的iPVD工艺，包括：在蚀刻模式期间将基片重新定位在比沉积模式期间更靠近所述空间的位置上。
15.如权利要求1-3中任一项所述的iPVD工艺，还包括：通过将RF能量耦合到室内的一个空间，在空间形成高密度等离子体，用于在沉积模式产生沉积到基片上的涂层材料的离子，在蚀刻模式产生蚀刻基片的离子；以及在沉积模式将RF能量以一功率电平耦合到空间内，而在蚀刻模式则以不同的功率电平耦合到空间内。
16.如权利要求15所述的iPVD工艺，包括：在蚀刻模式以比沉积模式更低的功率将RF能量耦合到空间内。
17.一种iPVD设备，包括：真空室，用于在从0.1mTorr到100mTorr以上的压力范围内，在基片上进行电离物理气相沉积；位于室一个末端的环形靶和位于室另一端的基片支承台；位于靶中央的三维线圈，与RF能量源耦合以将RF能量感应耦合到室内，从而在其中形成高密度等离子体；及编程后操作设备的控制器，其特征在于控制器编程后操作设备在以下步骤之间切换：操作设备工作在足够高的压力，使从靶溅射到等离子体内的材料热能化，并将材料从溅射靶溅射到等离子体中使材料电离，并以垂直于晶片的方向将材料沉积在晶片上；以及操作设备工作在比等离子体中粒子热能化的压力低的压力，并且不从靶上溅射材料，从基片上蚀刻沉积的材料，使基片上结构的突出边缘沉积的材料去除，将结构底部的材料重新溅射到结构侧壁上。
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