CN100372102C - 多芯片互连系统 - Google Patents
多芯片互连系统 Download PDFInfo
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Abstract
一种多集成电路(IC)芯片组件包括基底IC芯片(82)与安装在基底IC芯片(82)表面上的次级IC芯片(84-86)。一组形成于基底IC芯片(82)表面上且延伸超出次级IC芯片的突出触点将基底IC芯片(82)的表面连接到印刷电路板(PCB)基板(98),其中次级IC芯片(84-86)存在于基底IC(82)芯片与PCB基板(98)之间。
Description
技术领域
本发明涉及一种用于将多芯片组件互连到印刷电路板或其他基板的系统。
背景技术
图1是现有技术多芯片电器系统10的简化截视立面图,所述系统包括安装于印刷电路板(PCB)或其他基板14上的多芯片组件12。多芯片组件12包括一组直接安装于集成电路(IC)封包28内的基底芯片20上的次级芯片16-18。焊料22将芯片16-18上的结合衬垫24导电地连接到芯片20上的结合衬垫26。
安装于基板14上之IC插槽36通过触点37与焊料球38可释放地将每一封包销34固定并互连至PCB 14上的一组迹线39中的一个。结合线30将基底芯片20上的各种结合衬垫32连接到封包销34。为说明目的起见,图示焊料22比它在熔化后并重新固化以结合衬垫24和衬垫26之后应有的厚度厚的多。虽然图1中仅展示了两个封包销34,但是一个典型的IC封包将会具有许多封包销。
经常将包括直接安装于基底芯片上的一个或多个次级芯片的多芯片组件用在芯片之间需要高频率通信的地方,因为在次级与基底芯片之间的相对短的信号通路可以传送高频率信号。举例而言,多芯片组件已经用来将实施随机存取存储器(RAM)的芯片连接到一个实施微处理器的芯片,因此所述微处理器可以读取和写入存取在所述RAM最高速率处的RAM,而不会受到互连的带宽的限制。
图2是现有技术计算机系统40的简化方块图,此系统包括处理器芯片42、随机存取存储器(RAM)芯片44和只读存储器(ROM)芯片46。处理器芯片42包含处理器48、总线接口电路50和将处理器48连接到总线接口电路50的内部总线52。总线接口电路50通过平行存储器总线54将处理器48连接到RAM芯片44和ROM芯片46,并通过并行输入/输出(I/O)总线58将处理器48连接到其他IC设备56。处理器48与RAM芯片44、ROM芯片46和其他设备56进行通信的速度是由总线54和58所传送的信号频率的函数;信号频率越高,通信就越快。然而,总线54和58的并联电容和串联电感使信号衰减并使其失真;信号频率越高,信号衰减和失真就越大。因此,我们必须将总线54和58上的信号频率限制为信号衰减和失真保持在可接受的限制内的级别。
因为总线的并联电容和串联电感为总线长度的递增函数,所以我们可通过减少总线的长度来增加总线运行频率限制。为了减少总线54的信号通路距离,可以将实施RAM和ROM的芯片44与46直接安装在处理器芯片42上。因此,举例而言,图1的次级芯片16-18中的一个或多个可以实施RAM和ROM,而基底芯片20可以实施处理器芯片。
在通过测试探针使用测试装备存取衬垫32将图1的多芯片组件12封包之前来对其进行测试是可能的。然而,由于所述探针可能不具有与结合线30和封包销34相同的阻抗特性,因而当稍后将组件12安装在封包28中并用结合线30和封包销34与PCB 14互连时,测试互连环境可能不能精确地芯片拟组件12的运行互连环境。因此,所述测试可能会高估或低估由结合线30和封包销34所导致的信号衰减和失真的效果。
虽然图1的多芯片组件架构可以通过短信号通路将RAM和ROM芯片44和46″连接到处理器芯片42,但是处理器芯片42通过由结合线30、封包销34和插槽36所形成的相对长的信号通路必须仍然与其他可能安装于图3的PCB基板14上的I/O设备56进行通信。一种减少基底芯片20与PCB基板14之间的信号通路长度的方式已经为将所述基底芯片直接安装在所述基板上,并通过垂直通过基底芯片的通道将所述基底芯片的顶面上的电路连接到所述基板。
图3是现有技术多芯片组件60的简化截视立面图,此多芯片组件60包括安装在基底芯片66上并与其连接的次级芯片62-64,所述基底芯片一般与图1的多芯片组件12相似。然而,虽然图1的系统将多芯片组件12封包并使用结合线30、封包销34和连接器37,以将基底芯片20上的衬垫32连接到PCB基板14上的迹线39,但是图3的系统将基底芯片66直接安装于PCB基板68上并使用通过基底芯片66的导电通道70和焊料72,以将基底芯片顶面上的衬垫74连接到基板68上的迹线76。通道70提供比系统10(图1)的结合线30和封包销34短的信号通路。然而,通道70难以制造且制造费用昂贵。
因此,需要一种可以减少多芯片组件的基底芯片与PCB或其他基板间的信号通路长度而不必通过基底芯片形成通道的系统。所述系统同样应该允许IC测试器通过信号通道存取基底芯片和次级芯片,所述信号通路的阻抗特性与稍后用于互连基底芯片和次级芯片并与PCB或其他基板互连的通路类似。
发明内容
多芯片组件包括基底集成电路(IC)芯片和至少一个次级IC芯片,所述次级IC芯片具有电连接到所述基底IC芯片表面的I/O衬垫以使得基底芯片可以与次级芯片通信的输入/输出(I/O)衬垫。
根据本发明的实施例,形成于基底IC芯片表面上且向外延伸超出次级芯片的突出触点将基底IC芯片的I/O衬垫直接互连到基板表面上的导体,其中所述基底IC芯片与所述基板彼此面对,次级IC在其之间。由于突出触点相对短,因而其在基底芯片与基板之间提供相对低的阻抗信号通路。
本说明书的权利要求部分特别指出且清楚主张本发明的主题。然而,通过读取本说明书的剩余部分以及参看附图,所属技术领域的技术人员将最好地了解申请人认为是实施本发明的最好芯片式之运行的组织与方法两者,连同本发明的另外优点和目的,在所述附图中,相同的参考符号指的是相同的元件。
附图说明
图1是安装于电路板上的现有技术封包的多芯片组件的截视立面图;
图2以简化方块图的形式说明了现有技术计算机系统;
图3是安装于电路板上的未封包的现有技术多芯片组件的截视立面图;
图4是根据本发明的实施例连接到基板的多芯片组件的截视立面图;
图5是图4的系统的截视平面图;
图6是根据本发明的实施例说明了用于形成多芯片组件并将其安装到基板上之方法中的基本步骤的流程图;
图7A-7C根据本发明的实施例以方块图的形式说明了实施多芯片组件的若干实例;
图8A和8B是适用于互连图4的多芯片组件的触点类型的截视立面图;
图9A和9B是一种适用于互连图4的多芯片组件的平板弹簧触点类型之形成的截视立面图;
图10是另一种适用于互连图4的多芯片组件的平板弹簧触点类型的截视立面图;
图11是根据本发明的另一个实施例具有安装于基底芯片两侧上的次级芯片的多芯片电气系统的截视立面图;
图12是根据本发明的另外一个实施例可释放地安装于弹簧触点插槽中的多芯片组件的截视立面图;
图13是根据本发明的再一个实施例的多级多芯片组件的截视立面图;
图14A和14B是包含图4的若干处理器IC由两个不同探针基板测试之晶片的截视立面图;
图15是由探针基板测试的图4的多芯片组件的截视立面图;
图16是图15的半导体晶片的截视平面图;和
图17是说明了一种用于制造并测试图4之系统的方法的流程图。
具体实施方式
本发明是针对多芯片组件,且本说明书描述了本发明的若干例示性实施例和应用。然而,本发明并不限于此等例示性实施例和应用,或所述例示性实施例和应用运行方式,或被描述于本文中的实施例和应用的特定方式。
图4是根据本发明的例示性实施例的用于在多芯片组件89与基板98之间提供信号通路的互连系统80的截视立面图。图5是沿着图4切割线5-5处的截视平面图。在本发明的较佳实施例中,基板98是用于固定集成电路或与多芯片组件89内电路进行通信的其他设备(未图示)的印刷电路板(PCB)。然而,基板98可能是其他类型基板:用于固定诸如(举例而言)半导体基板的设备,在所述半导体基板上形成与多芯片组件89通信的集成电路。组件89包括一个基底集成电路(IC)芯片82和三个安装于基底芯片上的较小的次级IC芯片84-86。焊料90(图4所示,厚度经过夸大)导电性地将芯片84-86上的结合衬垫81连接到基底IC芯片82上的结合衬垫83。虽然图4和5说明了包括三个安装于基底芯片82上的次级芯片84-86的多芯片组件89,但是本发明的替代实施例可能包括少于或多于三个安装于基底芯片上的次级芯片。
如图4所说明,一组有弹性的弹簧触点92直接形成于基底IC芯片82的另一组结合衬垫94上。每一个弹簧触点92的自由端93延伸超出次级IC芯片84-86,以与基板98上的一组导电性迹线96、触点衬垫或其他导体配合。弹簧触点92在基板98上的衬垫96与基底芯片82上的衬垫94之间传送数据、动力和地面信号。(在本发明的替代实施例中,弹簧触点92可形成于基板98上并向上延伸,以与芯片82上的触点衬垫配合。)一组夹片100靠着基板98夹持组件89,且弹簧触点92弯曲以适应在衬垫94与迹线96之间的空间中的任何不均匀性。
尽管对准机制不为本发明所需,但是其可以用来确保组件89与基板98适当地对准。举例而言,嵌入PCB基板98中的对准销(未图示)可与形成于基底IC芯片82中的孔配合,或可导引基底IC 82的周长。或者,可以提供一个适当的框架组件(未图示)将组件89与基板98对准。
图6是说明了一种用于形成图4和5的多芯片组件89并将其安装到基板98上的方法的流程图。在步骤110处提供具有形成于其上的弹簧触点92的基底IC芯片82,并在步骤112处提供次级IC芯片84-86。接着,将次级IC芯片84-86安装于基底芯片上(步骤114)以形成多芯片组件。在步骤116处提供基板,并将所述多芯片组件安装于所述基板上(步骤118)以完成组件处理。
应用
采用弹簧触点92以将多芯片组件89的基底芯片82连接到PCB或其他类型的基板98的互连系统具有许多应用。将通过非常高的频率信号与实施于基底芯片中的电路进行通信的电路被适当地实施为次级芯片,因为在所述基底与次级芯片之间的焊料连接较短、具有非常小的阻抗,且可以传送具有小失真的非常高的频率信号。将以稍微较低的频率与实施于基底芯片上的电路进行通信的电路可以被实施于安装至基板98上的IC中。
举例而言,图7A以方块图的形式说明了计算机系统120,其中多芯片组件124的基底芯片122实施处理器,且所述组件的次级芯片126-128实施高速随机存取和只读存储器。弹簧触点129将基底芯片122上的衬垫130连接到PCB 134上的衬垫132,在所述PCB 134上安装了计算机存取的其他资源136。因此,基底处理器IC芯片122能够通过焊料连接138以非常高的频率与RAM和ROM IC芯片126-128进行通信,且通过短弹簧触点129和将资源136连接到处理器IC 150的PCB 134上的迹线(未图示)以尽管稍微较低(尽管仍然相对高)频率与安装于PCB 134上的其他资源136进行通信。
图7B说明了另一个实例计算机系统140,其中多芯片组件142、低速RAM和ROM IC 143和144以及其他I/O设备146安装于PCB 148上。多芯片组件142包括实施处理器IC的基底芯片150和实施高速的快取存储器的次级芯片152和154。在此实例中,基底处理器IC芯片150通过焊料连接156以高频率与高速的快取存储器芯片152和154进行通信,且通过短弹簧触点158和PCB 148上的迹线(未图示)以稍微较低的频率与RAM 143、ROM 144以及其他资源146进行通信。
图7C以方块图的形式说明了一个包括通过弹簧触点166连接到PCB 164的多芯片组件162的数字信号处理系统160。组件162的基底芯片168实施数字信号处理器(DSP)172,而次级IC 170-172实施基底DSP芯片168需要以高频率存取的资源,例如(举例而言)A/D转换器IC、射频IC以及声频放大器IC。DSP IC 168可能经由弹簧触点166和PCB164上的迹线以较低频率存取的其他资源174安装于所述PCB上。
虽然图7A-7C说明了本发明的有利应用,但是本发明并不限于此等应用。
互连结构
虽然为简单起见图4仅展示了小数目的厚弹簧触点92,但是实际上,可能采用许多小的弹簧触点来在基底IC芯片82与基板98之间传送数据、控制、动力和/或地面信号。弹簧触点92可能为各种适当形状的任何一种,且虽然弹簧触点92较佳用于将基底芯片82连接到PCB或其他基板98,但是可以使用任何其他类型的为次级芯片84-86提供足够空间以使其存在于基底芯片82与基板98之间的突出导体。
1999年6月29日发表的美国专利第5,917,707号(以引用的方式并入本文中)描述了一种用于形成适用于用作为图4的弹簧触点的柱触点的方法。如图8A中所说明,结合线180附着于基底芯片82上的一个衬垫94,并用诸如镍的有弹性的导电材料层182覆盖所述结合线180,形成直柱状的触点184。或者,如图8B中所说明,可以在镍覆盖之前将结合线180弯成悬臂形状,使得所得的弹簧触点186具有额外的弹性。在弹簧触点核心处的结合线180较佳由软的可容易成形的材料形成,且覆盖层182较佳用强度和弹性给予弹簧触点结构的较硬材料形成。
2001年2月6日发表的美国专利第6,184,053号(以引用的方式并入本文中)教示了一种用于使用平板技术形成适用于用作为图4的弹簧触点92的弹簧触点的方法。如图9A中所说明,基底芯片82连续地覆盖有很多遮蔽层190-192,这些遮蔽层经过平板图案化和蚀刻以暴露出衬垫94。接着,在层192上形成诸如钛/钨的导电性晶种材料(seed material)并被图案化,形成界定弹簧触点形状的薄晶种层194。接着,将诸如镍的导电性材料196电镀到晶种层194上,并接着移除遮蔽层190-192的剩余部分以暴露悬臂弹簧触点198,如图9B中所说明。
1998年12月2日申请的美国专利申请案第09/205,022号(以引用的方式并入本文中)描述了另一种用于制造弹簧触点200的方法,如图10中所说明,所述弹簧触点200适用于用作为图4的弹簧触点92。弹簧触点200包括从IC衬垫94上升的导电性柱202、从柱202水平向外延伸的横杆204以及形成于横杆204远端上的导电性触点206。通过平板地图案化并蚀刻形成于基底芯片82表面上的导电性材料的连续层形成柱202、横杆204和触点206。
虽然图4说明了具有三个安装在基底芯片82下部的次级芯片84-86的芯片组件89,但是在本发明的范畴内的替代实施例可能包括一个、两个或三个以上的次级芯片。也可能将额外的次级芯片安装在基底芯片的顶面上而非底面上。虽然焊料90用来将次级芯片84-86的结合衬垫81连接到基底芯片82的衬垫83,但是可采用其他诸如弹簧触点、凸块、衬垫用于在基底与次级芯片之间提供信号通路的构件。同样,虽然图4的互连系统80采用夹片100来将组件89固定于基板98上的原地,但是可采用其他用于将组件89固定于基板98上的原地的构件。
举例而言,图11说明了包括基底芯片212和次级芯片214的多芯片组件210,所述次级芯片214由焊料215连接到被实施于基底芯片212底面216上的集成电路的衬垫。将一组形成于两个其他次级芯片220和221表面上的弹簧触点218的自由端217焊接到基底芯片212的顶面223上的衬垫222。一组垂直通过或环绕基底芯片212的边缘的导电性通道224将衬垫222连接到形成于基底芯片212底面216上的衬垫225。将另一组形成于基底IC 212的底面216上的弹簧触点227的自由端226焊接到PCB229的顶面上的衬垫228。因此,形成于基底IC 212的底面216上的集成电路通过焊料连接215与次级IC 214进行通信、通过弹簧触点218和通道224与次级IC220和221进行通信、以及通过弹簧触点227与PCB 229上的衬垫228进行通信。2001年3月27日申请的美国专利申请案第09/819,181号(以引用的方式并入本文中)描述了各种用于在半导体晶片中形成通道的方法。
在图4中,夹片100对弹簧触点92施加压力,以将其固定于PCB基板98表面上的衬垫93上的原地,而在图11中,将弹簧触点227的自由端226焊接到PCB 229的衬垫228。然而,本发明的替代实施例可采用弹簧触点插槽以将基底IC芯片的弹簧触点连接到基板。2000年3月7日发表的美国专利第6,033,935号(以引用的方式并入本文中)详细描述了弹簧触点插槽。举例而言,图12是一个可释放地安装于弹簧触点插槽232中的多芯片组件230的截视立面图。一组夹片234下推到组件230上,以固定组件230的一组弹簧触点238的自由端236靠着弹簧触点插槽232的触点240。插槽232内的信号通路242将弹簧触点238连接到另一组弹簧触点244,所述另一组弹簧触点244在插槽232下方延伸并具有被焊接到基板248上的迹线247的自由端246。
虽然图4的弹簧触点92将多芯片组件89的基底芯片82连接到PCB基板98,但是其或者可将基底芯片连接到另一个IC芯片,以形成具有两个以上的芯片级的分级芯片组件。举例而言,图13展示了安装于基板PCB 254上的“二级”多芯片组件250和“三级”多芯片组件252。二级多芯片组件250包括通过弹簧触点258连接到PCB基板254的衬垫257。将一对次级芯片260和261焊接到基底芯片256。三级多芯片组件252包括一个基底芯片262、一对“第二级”芯片264和265以及一对“第三级”芯片266和267。一组形成于基底芯片262的衬垫270上的弹簧触点268将基底芯片262连接到PCB基板254。将弹簧触点268焊接到PCB基板254顶面上的衬垫272。将第二级芯片264焊接到基底芯片262的底面274,而通过一组形成于基底芯片262底面上的信号衬垫277上的弹簧触点276将第二级芯片265连接到基底芯片262。将弹簧触点276焊接到次级芯片265的顶面279上的信号衬垫278。
由于形成于半导体芯片上的IC仅存在于所述芯片的最上部分,因而可以通过从芯片的较低侧移除半导体而不损害形成于所述芯片中的IC来使所述芯片变薄。因此,可以通过使芯片260、261、264、265、266以及267变薄,而将图13的弹簧触点258、268和276的长度最小化。
制造和测试
在将图4的基底芯片82和次级芯片84-86与其在上面形成的半导体晶片分离之前,可以对其进行测试。由于在将芯片与其晶片分离之前弹簧触点92形成于基底芯片82上,因而此等弹簧触点可以用来将所述基底芯片连接到测试装备。因此,所述测试装备能够通过一个具有与稍后将基底芯片82连接到基板98(在其预期的运行环境中)的通路相同的阻抗特性的信号通路存取基底芯片82。
图14A描绘了包含一组基底芯片82的IC晶片280,所述基底芯片82接近一个通过电缆284连接到外部测试装备(未图示)的探针基板282。所述外部测试装备将测试信号供应给芯片82,并接收且处理由所述芯片产生的响应信号,以判定芯片82是否适当地响应测试信号。当晶片280接近基板282时,在基板282下表面上的衬垫286与形成于基底IC晶片280上的弹簧触点92的自由端93配合。形成于基板282底面上的衬垫289上的另一组弹簧触点288的自由端287与芯片82表面上的结合衬垫83配合。通过基板282和基板282表面上的迹线(未图示)的通道290将衬垫286和289连接到电缆连接器292。外部测试装备通过电缆284、连接器292、通道290以及弹簧触点92和288连接到正被测试的IC 82。弹簧触点92中的某些从基板282将动力和地面信号传递到IC 82。
图14B描绘了包含接近探针基板300的基底芯片82的IC晶片280。将一组安装于基板300上的IC 302和经由电缆284连接到基板的外部测试装备(未图示)提供到测试芯片82。当晶片280接近基板300时,在基板300下表面上的衬垫304与形成于基底IC晶片280上的弹簧触点92的自由端93配合。形成于基板300底面上的衬垫310上的另一组弹簧触点308的自由端306与芯片82表面上的结合衬垫83配合。通过基板300的通道312将测试IC 302连接到衬垫304和310。测试和响应信号在测试IC302与正被测试的芯片82之间通过通道312和弹簧触点92和308。弹簧触点92中的某些从基板300也将动力和地面信号传递到芯片82。将测试函数分配在安装于基板300上的测试IC 302与外部测试装备之间。举例而言,测试IC 302可仅包括用于将由外部测试装备所产生的测试信号转发给芯片82和用于将由所述芯片产生的响应信号转发回至所述外部测试装备的缓冲器。或者,作为另一个实例,测试IC可包括通过在内部产生测试信号并处理响应信号和将测试结果转发回至外部测试装备来独立测试IC的电路。
图14A、14B和15中说明的测试系统是例示性的;可采用其他测试系统配置。举例而言,可将测试IC 302安装到图14B的基板300外部。相反地,可以将测试IC安装于图14A和15的基板282和320上。
在测试次级芯片84-86之后,将其与其晶片分离并将其安装于晶片280的每一适当起作用的基底芯片82上,并可以测试所得的多芯片组件89,如图15和16所说明。
图15展示了接近探针基板320的晶片280。图16是沿着图15的线16-16的截视平面图。探针基板320包括用于将其下表面上的衬垫324连接到与被连接到外部测试装备的电缆328和连接器326相连接的其顶面上的迹线(未图示)的通道322。当晶片280接近接近测试基板320时,衬垫324与基底IC晶片280的弹簧触点92的自由端93配合。接着,测试和响应信号在测试装备与芯片82之间通过电缆328、连接器326、通道322、衬垫324以及弹簧触点92。弹簧触点92也将动力和地面信号传送到IC 82。
图17是根据本发明的实施例说明了用于形成和测试图4的多芯片组件89的方法的流程图。从步骤330开始,以常规方式制造包含次级IC芯片84-86的次级IC晶片,并经受常规晶片级测试程序(步骤332)。接着,用焊料90将次级IC晶片图案化(步骤334),并切割所述次级IC晶片以对其次级IC芯片进行切单(步骤336),其中抛弃非功能的次级IC芯片。在步骤338处,制造包含多基底IC芯片82的基底IC晶片,并将弹簧触点92形成于所述基底IC晶片(步骤340)。接着,如图14A或14B所说明测试基底IC(步骤342)。
在步骤344处,将次级IC芯片84-86放置于在步骤342处通过测试的基底IC晶片的此等基底IC芯片82。接着加热所得的组件,以使弹簧触点92退火并回流焊料90的球使得其稳固地将个别次级IC芯片结合到每一相关的基底IC芯片(步骤346)。在所得的多芯片组件89经受如图15所说明的最后晶片级测试(步骤348)之后,接着切割基底IC晶片以分离多芯片组件89(步骤350)。在步骤352处制造基板98或多芯片组件89将被安装于其上的其他基板,并在步骤354处将夹片100(图4)添加到PCB。接着,将多芯片组件89夹至基板98上以形成图4的系统80(步骤356)。
由此已经展示和描述了一种用于以下列方式将多芯片组件互连到PCB或其他基板的系统:所述方式减少信号通路长度且允许所述组件的每一部分在其预期互连环境中于晶片级被分别测试。
虽然上述说明书已经描述了申请人认为是实施本发明的最好芯片式的内容,但是所属技术领域的技术人员将了解到可以改变的方式来实施本发明。随附的权利要求意欲涵盖采用叙述于所述权利要求之任何一个中的元件或步骤之组合的所有芯片式,包括采用是如在上文描述的元件或步骤的功能等价物的元件或步骤的芯片式。
Claims (54)
1.一种用于将一IC多芯片组件互连到一基板上的导体用于在其之间传送信号的方法,其中所述多芯片组件包括一具有一表面的第一IC芯片,并包括安装于所述第一IC芯片的所述表面上的至少一个次级IC芯片,所述基底IC芯片与所述次级IC芯片之间提供信号通路,所述方法包含以下步骤:
a.提供直接附在所述第一IC芯片的所述表面上导电性触点,每一导电性触点具有一从所述第一IC芯片的所述表面向外延伸超出所述次级IC芯片的自由端;和
b.将所述多芯片组件安装于所述基板上,使得每一触点的所述自由端与所述基板上的所述导体接触,并使得所述次级IC芯片存在于所述第一IC芯片的所述表面与所述基板之间,其中所述触点在所述第一IC芯片与所述基板上的所述导体之间传送所述信号,
其中所述导电性触点为伸长且柔性的,且在所述多芯片组件的所述基底IC芯片与所述基板之间提供柔性电接触。
2.根据权利要求1所述的方法,其中所述安装进一步包含将所述导电性触点的所述自由端焊接到所述基板上的所述导体和所述基板的一表面。
3.根据权利要求1所述的方法,其中所述导电性触点是有弹性的弹簧触点。
4.根据权利要求3所述的方法,其中所述安装进一步包含:
将所述多芯片组件夹持到所述基板,使得所述弹簧触点靠着所述基板的一表面上的所述导体被压缩。
5.根据权利要求1所述的方法,其中所述基底IC芯片包含一处理器。
6.根据权利要求3所述的方法,其中所述安装包括将所述多芯片组件可移除地安装在所述基板上。
7.根据权利要求6所述的方法,其中所述安装包括将所述弹簧触点压靠在所述基板的所述表面上的所述导体上,且借此在所述弹簧触点和所述导体之间建立电连接。
8.根据权利要求7所述的方法,其中所述弹簧触点和所述导电之间的所述电连接不包括焊接。
9.根据权利要求1所述的方法,其中所述第一IC芯片包括一处理器电路且所述次级IC芯片包括一存储器电路。
10.根据权利要求1所述的方法,其中所述第一IC芯片为一基底IC芯片。
11.根据权利要求10所述的方法,其中所述基底IC芯片为一半导体IC芯片。
12.根据权利要求1所述的方法,其中所述导电性触点大体位于所述第一IC芯片的所述表面和所述基板之间。
13.根据权利要求1所述的方法,其中所述导电性触点全部地位于所述第一IC芯片的所述表面和所述基板之间。
14.根据权利要求1所述的方法,其中所述次级IC芯片全部地位于所述第一IC芯片的所述表面和所述基板之间。
15.根据权利要求1所述的方法,其中所述第一IC芯片的所述表面包括多个终端,且所述导电性触点直接附接至所述多个终端。
16.根据权利要求1所述的方法,其中所述至少一个次级IC芯片直接安装在所述第一IC芯片的所述表面上。
17.根据权利要求16所述的方法,其中所述第一IC芯片的所述表面包括多个终端,且所述至少一个次级IC芯片直接安装在所述多个终端上。
18.根据权利要求1所述的方法,其中多个次级IC芯片直接安装在所述第一IC芯片的所述表面上。
19.根据权利要求18所述的方法,其中所述多个次级IC芯片全部地位于所述第一IC芯片的所述表面和所述基板之间。
20.一种用于制造并测试一多芯片组件的方法,所述方法包含以下步骤:
a.提供一具有导体形成于其上的基板;
b.提供一包括多个基底IC芯片的基底IC晶片,所述多个基底IC芯片的每一个均具有一第一表面和一平行于所述第一表面的第二表面;
c.将伸长的弹簧导电性触点形成于所述基底IC芯片的每一个的所述第一表面上,每一导电性触点具有一从所述基底IC芯片的所述第一表面向外延伸的自由端;
d.提供多个第一次级IC芯片;
e.通过第一导电性信号通路将所述第一次级IC芯片中的至少一个连接到所述基底IC芯片的每一个的所述第一表面;
f.将所述基底IC芯片中的几个与所述基底IC晶片的其他部分分离;和
g.定位所述分离的基底IC芯片中的一个,使得其第一表面朝向所述基板,使得所述导电性触点的自由端与所述基板上的所述导体接触,并使得所述第一次级IC芯片中的至少一个连接到所述分离的基底IC芯片的第一次级IC芯片存在于所述分离的基底IC芯片的所述第一表面与所述基板之间,其中所述导电性触点在所述分离的基底IC芯片与所述基板上的所述导体之间传送信号。
21.根据权利要求20所述的方法,其中所述导电性触点是有弹性的弹簧触点。
22.根据权利要求20所述的方法,其中所述第一导电性信号通路由焊料形成。
23.根据权利要求20所述的方法,其中步骤d包含以下子步骤:
d1.提供一具有所述次级IC芯片形成于其上的次级IC晶片;
d2.测试所述次级IC芯片;和接着
d3.切割所述次级IC晶片以对所述次级IC芯片进行切单。
24.根据权利要求20所述的方法,其进一步包含以下步骤:
h.在步骤e之前,通过所述导电性触点将所述基底IC芯片连接到一用于测试所述基底IC芯片的装置。
25.根据权利要求20所述的方法,其进一步包含以下步骤:
i.在步骤f之前,通过所述导电性触点将所述多芯片组件连接到一用于测试所述多芯片组件的装置。
26.根据权利要求24所述的方法,其进一步包含以下步骤:
i.在步骤g之前,通过所述导电性触点将所述多芯片组件连接到一用于测试所述多芯片组件的装置。
27.根据权利要求20所述的方法,其进一步包含以下步骤:
h.提供一第二次级IC芯片;
i.通过第二导电性信号通路将所述第二次级IC芯片连接到所述基底IC芯片的所述第二表面。
28.根据权利要求27所述的方法,其进一步包含以下步骤:
j.通过所述基底IC晶片形成导电性通道,用于在所述基底IC芯片的所述第一表面与所述第二表面之间提供信号通路。
29.根据权利要求27所述的方法,其中所述第二导电性信号通路包含弹簧触点。
30.根据权利要求27所述的方法,其中焊料形成所述第二导电性信号通路。
31.根据权利要求27所述的方法,其中所述基板是一印刷电路板基板。
32.根据权利要求20所述的方法,其中所述基板是一半导体基板。
33.根据权利要求21所述的方法,其中所述第一导电性信号通路由焊料形成,且其中步骤d包含以下子步骤:
d1.提供一具有所述次级IC芯片形成于其上的次级IC晶片;
d2.测试所述次级IC芯片;和接着
d3.切割所述次级IC晶片以对所述次级IC芯片进行切单。
34.根据权利要求33所述的方法,其进一步包含以下步骤:
h.在步骤e之前,通过所述弹簧触点将所述基底IC芯片连接到一用于测试所述基底IC芯片的装置;和
i.在步骤f之前,通过所述弹簧触点将所述多芯片组件连接到一用于测试所述多芯片组件的装置。
35.根据权利要求34所述的方法,其进一步包含以下步骤:
j.提供一第二次级IC芯片;
k.通过第二导电性信号通路将所述第二次级IC芯片连接到所述基底IC芯片的所述第二表面;和
l.通过所述基底IC晶片形成导电性通道,用于在所述基底IC芯片的所述第一表面与所述第二表面之间提供信号通路。
36.一种多芯片电子系统,其包含:
一基板,其具有形成于其上的导体;
一基底IC芯片,其具有一朝向所述基板的第一表面和一平行于所述第一表面的第二表面;
一第一次级IC芯片,其存在于所述基底IC芯片的所述第一表面与所述基板之间,并通过第一导电性信号通路被连接到所述基底IC芯片的所述第一表面;和
导电性触点,其在所述基底IC芯片的所述第一表面与所述基板上的所述导体之间延伸,用于在所述基底IC芯片与所述基板上的所述导体之间传送第一信号,其中提供在所述第一次级IC芯片和所述基底IC芯片之间的第二信号中的至少一个比提供在所述基底IC芯片和所述基板之间的所述第一信号具有一更高频率。
37.根据权利要求36所述的多芯片电子系统,其中焊料形成所述第一导电性信号通路。
38.根据权利要求36所述的多芯片电子系统,其中所述基板是一印刷电路板基板。
39.根据权利要求36所述的多芯片电子系统,其中所述基板是一半导体基板。
40.根据权利要求36所述的多芯片电子系统,其中所述导电性触点包含有弹性的弹簧触点。
41.根据权利要求36所述的多芯片电子系统,其中所述弹簧触点形成于所述基底IC芯片的所述第一表面上,并被焊接到所述基板的所述导体。
42.根据权利要求36所述的多芯片电子系统,其中所述导电性触点包含:
形成于所述基底IC芯片的所述第一表面上的有弹性的弹簧触点,和一在所述弹簧触点与所述基板上的所述导体之间提供信号通路的弹簧触点插槽。
43.根据权利要求36所述的多芯片电子系统,其进一步包括:一第三级IC芯片,其位于所述基底IC芯片的所述第一表面和所述第一次级IC芯片的一第三表面之间,其中所述第一次级IC芯片位于所述基底IC芯片的所述第一表面和所述基板之间,所述第三级IC芯片通过导电性信号通路连接到所述第二级IC芯片的所述第三表面。
44.一种多芯片电子系统,其包含:
一基板,其具有形成于其上的导体;
一基底IC芯片,其具有一朝向所述基板的第一表面和一平行于所述第一表面的第二表面;
一第一次级IC芯片,其位于所述基底IC芯片的所述第一表面与所述基板的之间,并通过第一导电性信号通路被连接到所述基底IC芯片的所述第一表面;
导电性触点,其包括所述基板IC芯片的所述第一表面和所述基板上的所述导体之间延伸的弹性弹簧,所述弹性弹簧用于在所述基板IC芯片和所述基板上的所述导体之间传送信号;和
用于将所述基底IC芯片固定至最近所述基板使得所述弹簧触点靠着所述基板的所述表面上的所述导体被压缩的构件。
45.一种多芯片电子系统,其包含:
一基板,其具有形成于其上的导体;
一基底IC芯片,其具有一朝向所述基板的第一表面和一平行于所述第一表面的第二表面;
一第一次级IC芯片,其存在于所述基底IC芯片的所述第一表面与所述基板的之间,并通过第一导电性信号通路被连接到所述基底IC芯片的所述第一表面;
第一导电性触点,其在所述基底IC芯片的所述第一表面和所述基板上的所述导体之间延伸,用于在所述基底IC芯片与所述基板上的所述导体之间传送第一信号;
一第二次级IC芯片;和
第二导电性通路,其将所述第二次级IC芯片连接到所述基底IC芯片的所述第二表面。
46.根据权利要求45所述的多芯片电子系统,其进一步包含:
用于在所述基底IC芯片的所述第一表面与所述第二表面之间提供信号通路的导电性通道。
47.根据权利要求45所述的多芯片电子系统,其中所述第二导电性通路包含弹簧触点。
48.一种多芯片电子系统,其包含:
一基板,其具有形成于其上的导体;
一基底IC芯片,其具有一朝向所述基板的第一表面和一平行于所述第一表面的第二表面;
一第二级IC芯片,其具有一第三表面并存在于所述基底IC芯片的所述第一表面与所述基板之间,并通过第一导电性触点被直接连接到所述基底IC芯片的所述第一表面,用于在所述基底IC芯片与所述第二级IC芯片之间传送信号;
一第三级IC芯片,其存在于所述基底IC芯片的所述第一表面与所述第二级IC芯片的所述第三表面之间,并通过导电性信号通路被直接连接到所述第二级IC芯片的所述第三表面;和
第二导电性触点,其在所述基底IC芯片的所述第一表面与所述基板上的所述导体之间直接延伸,用于在所述基底IC芯片与所述基板上的所述导体之间传送信号。
49.根据权利要求48所述的多芯片电子系统,其中焊料形成所述导电性信号通路。
50.根据权利要求48所述的多芯片电子系统,其中所述基板是一印刷电路板基板。
51.根据权利要求48所述的多芯片电子系统,其中所述基板是一半导体基板。
52.根据权利要求48所述的多芯片电子系统,其中所述第一和第二导电性触点包含有弹性的第一和第二弹簧触点。
53.根据权利要求52所述的多芯片电子系统,其中所述第一弹簧触点形成于所述基底IC芯片的所述第一表面上,并被焊接到所述第二级IC芯片的所述第三表面。
54.根据权利要求52所述的多芯片电子系统,其中所述第二弹簧触点形成于所述基底IC芯片的所述第一表面上,并被焊接到所述基板的所述导体。
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US09/970,749 | 2001-10-03 | ||
US09/970,749 US6882546B2 (en) | 2001-10-03 | 2001-10-03 | Multiple die interconnect system |
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CN1565055A CN1565055A (zh) | 2005-01-12 |
CN100372102C true CN100372102C (zh) | 2008-02-27 |
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EP (1) | EP1438745B1 (zh) |
JP (1) | JP4402954B2 (zh) |
KR (1) | KR100935838B1 (zh) |
CN (1) | CN100372102C (zh) |
DE (1) | DE60208579T2 (zh) |
TW (1) | TW561800B (zh) |
WO (1) | WO2003030255A2 (zh) |
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WO2003030255A2 (en) | 2003-04-10 |
DE60208579T2 (de) | 2006-10-19 |
KR100935838B1 (ko) | 2010-01-08 |
US7681309B2 (en) | 2010-03-23 |
JP2005505923A (ja) | 2005-02-24 |
US20050161797A1 (en) | 2005-07-28 |
DE60208579D1 (de) | 2006-03-30 |
CN1565055A (zh) | 2005-01-12 |
EP1438745A2 (en) | 2004-07-21 |
WO2003030255A3 (en) | 2003-10-30 |
KR20040041656A (ko) | 2004-05-17 |
EP1438745B1 (en) | 2006-01-04 |
TW561800B (en) | 2003-11-11 |
US20030063450A1 (en) | 2003-04-03 |
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US6882546B2 (en) | 2005-04-19 |
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