CN100385635C - 用来提高晶体管沟道中的应变效应的方法和设备 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 51
- 230000000694 effects Effects 0.000 title description 5
- 150000004767 nitrides Chemical class 0.000 claims abstract description 82
- 239000000758 substrate Substances 0.000 claims abstract description 53
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 32
- 239000010703 silicon Substances 0.000 claims abstract description 32
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims description 21
- 230000015572 biosynthetic process Effects 0.000 claims description 18
- 230000008021 deposition Effects 0.000 claims description 9
- 238000001020 plasma etching Methods 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 claims description 2
- 239000005368 silicate glass Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 2
- 239000000654 additive Substances 0.000 claims 1
- 230000000996 additive effect Effects 0.000 claims 1
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 238000005498 polishing Methods 0.000 claims 1
- 238000005019 vapor deposition process Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 24
- 229920005591 polysilicon Polymers 0.000 description 24
- 229910021332 silicide Inorganic materials 0.000 description 19
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 19
- 238000005516 engineering process Methods 0.000 description 14
- 230000006835 compression Effects 0.000 description 6
- 238000007906 compression Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 6
- 238000012797 qualification Methods 0.000 description 6
- 229910019001 CoSi Inorganic materials 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229910005883 NiSi Inorganic materials 0.000 description 2
- JUJWROOIHBZHMG-UHFFFAOYSA-N Pyridine Chemical compound C1=CC=NC=C1 JUJWROOIHBZHMG-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000035772 mutation Effects 0.000 description 1
- UMJSCPRVCHMLSP-UHFFFAOYSA-N pyridine Natural products COC1=CC=CN=C1 UMJSCPRVCHMLSP-UHFFFAOYSA-N 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
本发明公开了一种用来提高晶体管沟道中的应变效应的方法和设备，并提供了一种具有增大应力的晶体管沟道的半导体器件。为了得到增大了应力的晶体管沟道，氮化物膜被择优地形成在器件衬底上，而在栅叠层部分上很少有或没有氮化物。氮化物膜可以被择优地仅仅淀积在硅衬底上成为不共形层，其中，很少或没有氮化物被淀积在栅叠层的上部上。氮化物膜也可以被均匀地淀积在硅衬底和栅叠层上成为共形层，而在稍后的步骤中择优地清除栅叠层上部附近的氮化物膜。在某些实施方案中，借助于清除栅叠层的上部而清除栅叠层顶部附近的氮化物。在任何方法中，借助于最小化淀积在栅叠层上的氮化物，同时保留淀积在衬底上的氮化物，增大了晶体管沟道中的应力。
Description
技术领域
本发明一般涉及到晶体管性能的提高，更确切地说是涉及到借助于在晶体管沟道区中产生所希望的应力而提高晶体管性能。
背景技术
随着半导体器件的缩小，载流子迁移率已经成为改善器件速度的障碍。研究已经表明，借助于在晶体管沟道中产生张应力能够显著地提高电子迁移率，且借助于产生压应力能够改善空穴迁移率。于是，为了改善半导体器件的特性，就在n型器件(例如nFET)和/或p型器件(例如pFET)的沟道中产生张应力和/或压应力。此外，沟道中的应力越大，可能实现的迁移率改善就越多
利用淀积在晶体管顶部上的Si3N4或氮化物，可以引入沟道应力。沟道中引入的应力的符号(伸张或压缩)与氮化物膜中应力的符号相同。但引入的沟道应力的幅度仅仅是氮化物膜中应力的一小部分。典型的应力约为张应力1-2 GPa和压应力1-2.5GPa，因此，最大应变效应受到了限制。
例如，具有加有应力的晶体管沟道的相关技术的晶体管包括其上表面上形成有栅氧化物的硅衬底。接着在栅氧化物上淀积多晶硅栅。偏置衬垫或栅侧壁被形成为临近多晶硅栅的二侧。栅侧壁可以被用来在硅衬底内形成适当的离子注入延伸结构。此外，Si3N4衬垫被充分地形成在多晶硅栅的各个侧壁上。应该指出的是，通常在离子注入之前将Si3N4衬垫固定到栅侧壁。接着用离子注入来形成多晶硅栅二侧上硅衬底中的源区/漏区。
进一步的加工包括在源/漏区附近形成衬底硅化物区以及形成在多晶硅栅上的栅硅化物区。衬底和栅硅化物区可以包括CoSi或NiSi。衬底和栅硅化物区被形成为自对准于源/漏区和多晶硅栅区。
接着，高度受应力的Si3N4或氮化物膜以相同的厚度被均匀地淀积在硅衬底、源区和漏区、偏置衬垫、以及多晶硅栅上。受应力的氮化物膜被淀积成共形层，包括被淀积在侧壁衬垫上。此氮化物膜通过硅衬底与氮化物膜的晶格结构的失配而在包括晶体管沟道区的硅衬底中引起应力。晶体管沟道区中诱发的应力正比于氮化物膜中的应力且与氮化物膜中应力的符号相同(伸张或压缩)。诱发应力的幅度是氮化物膜中应力的一小部分。
应该指出的是，在上述器件中，晶体管沟道区中诱发的应力是氮化物膜应力的一小部分。由于载流子迁移率的改善随着晶体管沟道区中应力幅度的增大而增大，故在晶体管沟道区中产生更大的应力的方法有可能进一步改善晶体管的性能。
发明内容
本发明包括在具有排列在衬底上的栅叠层的半导体器件中增大应力的方法，它包括沿衬底和栅叠层的表面淀积氮化物膜，其中的氮化物膜在衬底表面上更厚，而在栅叠层部分上更薄。
本发明还包括在具有排列在衬底上的栅叠层的半导体器件中增大应力的方法，它包括在栅叠层上和衬底表面上淀积氮化物膜层以及清除部分栅叠层和淀积于其上的氮化物膜。
本发明还包括一种半导体器件，它具有硅衬底、排列在硅衬底上的栅叠层、排列在硅衬底和栅叠层上的受应力的氮化物膜，其中，受应力的氮化物膜在硅衬底上更厚，而在部分栅叠层上更薄。
附图说明
图1示出了形成根据本发明的实施方案的过程中的一个步骤；
图2示出了形成根据本发明的实施方案的过程中的一个步骤；
图3示出了形成根据本发明的实施方案的过程中的一个步骤；
图4示出了形成根据本发明的实施方案的过程中的一个步骤；
图5示出了形成根据本发明的实施方案的过程中的一个步骤；
图6示出了形成根据本发明的实施方案的过程中的一个步骤；
图7示出了根据本发明制作的半导体器件中应力对距离的关系；
图8示出了形成根据本发明的实施方案的过程中的一个步骤；
图9示出了形成根据本发明的实施方案的过程中的一个步骤；
图10示出了形成根据本发明的实施方案的过程中的一个步骤；
图11示出了形成根据本发明的实施方案的过程中的一个步骤；
图12示出了形成根据本发明的实施方案的过程中的一个步骤；
图13示出了形成根据本发明的实施方案的过程中的一个步骤。
具体实施方式
借助于在晶体管沟道区中产生应力，可以提高晶体管的性能。因此，可以将栅结构形成为从受应力的氮化物膜在晶体管沟道中诱发增大的应力。为了得到此增大了的应变效应，本发明的一个实施方案包括在形成硅化物之后从晶片清除栅衬垫，然后淀积不共形的Si3N4膜，包括在栅叠层顶部处的栅侧壁上形成很少或不形成氮化物。以这种方式，借助于在器件的晶体管沟道区中产生所希望的应力，提供了晶体管性能的提高。应该指出的是，用来增大晶体管沟道中的应变效应的这种方法和设备，适用于n型器件或p型器件二者。因此，如本技术领域熟练人员众所周知的那样，借助于适当地调整淀积参数，能够使氮化物伸张或压缩。
在另一实施方案中，借助于在淀积受应力的氮化物膜之后用旋涂材料涂敷晶片，可以得到这种结构。栅二侧上下方区域处的受应力的氮化物膜在后续的材料清除步骤中受到旋涂材料保护。在此方法的另一实施方案中，在已经涂敷旋涂材料之后，利用CMP(化学机械整平)工艺从栅顶部区域清除氮化物叠层，可以得到增大了应力的结构。后一种技术也可以被用来代替栅工艺。
现在参照附图，图1示出了硅衬底12，其上表面上形成有栅氧化物14。接着，多晶硅栅16被形成在栅氧化物14上。偏置衬垫即栅侧壁18被形成在多晶硅栅16的侧面上。此偏置衬垫18被用来在硅衬底12内形成适当的离子注入延伸结构。
图2示出了形成在多晶硅栅16的每一侧面上的Si3N4衬垫20。在离子注入之前，Si3N4衬垫20被固定到偏置衬垫18。接着，离子注入被用来在多晶硅栅16二侧处的硅衬底12内形成源/漏区22。对于n型晶体管，例如浅而高剂量的砷离子可以被用来形成源/漏区。对于p型晶体管，例如浅而高剂量的BF2离子可以被用来形成源/漏区。
图3示出了在Si3N4衬垫20二侧上清除的栅氧化物14。还示出了形成在源/漏区22附近的衬底硅化物区24和形成在多晶硅栅16上的栅硅化物区26。衬底和栅硅化物区24和26可以包括CoSi或NiSi。衬底和栅硅化物区24和26被形成为自对准于源/漏区22和多晶硅栅区16。
图4示出了形成受应力的晶体管沟道之前的半导体器件，它具有带掺杂的硅化物区24的硅衬底12。在硅衬底12的顶部上是栅氧化物14，而在栅氧化物14顶部上是多晶硅栅16。栅侧壁18被形成在多晶硅栅16的侧面上。栅硅化物区26被形成在多晶硅栅16上，从而完成栅叠层。多晶硅栅16和栅侧壁18一起形成栅叠层。为此描述，栅叠层也可以包括例如多晶硅栅16、栅侧壁18、以及栅硅化物区26。以本技术领域熟练人员所知的任何常规方法来形成所述的结构。
如图4所示，利用对CoSi和氧化物有选择性的各向同性Si3N4RIE(反应离子刻蚀)工艺，从栅侧壁18清除可能存在的任何Si3N4衬垫(图2中参考号20所指)。Si3N4衬垫可以用RIE方法完全清除、减小尺寸，或简单的退缩。应该指出的是，如本技术领域熟练人员应该知道的那样，可以采用从栅叠层顶部清除或减少Si3N4衬垫的任何工艺。
参照图5，用PECVD(等离子体增强的化学气相淀积)工艺在晶体管栅上淀积不共形的Si3N4或氮化物膜32。可以用PECVD淀积方法在比较低的温度下来形成不共形的Si3N4膜，在晶片加工的这一阶段，这是可取的。虽然PECVD被用作例子，但应该指出的是，可以采用任何能够淀积不共形氮化物膜的工艺。在一种执行过程中，氮化物膜32应该被淀积成在栅侧壁18上只有很少或没有Si3N4。如下面进一步描述的那样，由于在栅侧壁18上不存在氮化物膜32或被减少了，故由于材料的突然终止而产生应力聚集器或提升器，使更大的应力被诱发在晶体管沟道34中。
图6示出了对于可能是本发明一个执行特征的60nm宽的多晶硅栅和50nm厚的衬垫在栅氧化物以下5nm区域内，清除氮化物帽之前(实线)和之后(虚线)晶体管沟道中的应力数字模拟Sxx与沿器件衬底的单位为微米的水平距离的函数关系的结果曲线，其中，氮化物膜形成在晶体管沟道中的应力Sxx为2.0GPa，这在栅氧化物以下大约5nm处大于大约每平方厘米4.5×109达因。在另一执行过程中，在栅氧化物以下大约5nm处，晶体管沟道中增大了的应力大于大约每平方厘米5.5×109达因。
如图6的曲线所示，数字模拟示出了当Si3N4叠层从栅的顶部区被清除时，特别是当Si3N4从靠近栅叠层顶部的栅侧壁被清除时，相应晶体管沟道中的应力增大了39％。
参照图7-8，示出了晶体管沟道应力增大的另一实施方案，其中，图7示出了一种半导体器件，它具有其上带栅氧化物14的硅衬底12。硅衬底12具有硅化物区24。具有栅侧壁18的多晶硅栅16位于栅氧化物14上。栅硅化物区26被形成在多晶硅栅16的顶部上。
在图4器件的一个变种中，Si3N4衬垫36被添加到图7所示器件。图7的衬垫36占据了硅衬底12和栅侧壁18表面上的一个小区域，并被形成在栅叠层的下部区域上。亦即没有沿整个侧壁提供衬垫。这种构造尽量减少了形成在栅叠层顶部附近的Si3N4的量。可以借助于诸如用对二氧化硅和硅化物有选择性的RIE工艺来使Si3N4衬垫36退缩之类的各种工艺来形成Si3N4衬垫36。如本技术领域熟练人员能够实现的那样，可以采用任何其它可将Si3N4衬垫36接近栅叠层底部形成的工艺。
参照图8，用例如PECVD工艺，不共形的Si3N4或氮化物层38被淀积在器件上，致使只有很少或没有Si3N4淀积在栅侧壁18上。再次借助于将尽量少的氮化物淀积在栅侧壁18上，氮化物结构终止得很突然，产生应力聚集器或提升器，这增大了形成在晶体管沟道40中的应力。
虽然PECVD工艺被用于例子中，但也可以采用可淀积不共形氮化物膜的诸如高密度等离子体淀积之类的任何工艺。而且，可以采用择优减少淀积在栅侧壁18上的氮化物量的任何工艺。
参照图9，示出了另一种提高晶体管沟道中的应力的方法，其中，氮化物膜28淀积在具有栅氧化物14、Si3N4衬垫20、侧壁衬垫18、以及顶部上具有栅硅化物区26的多晶硅栅16的硅衬底12上。在已经淀积氮化物膜28之后，诸如ARC(抗反射涂层)、氧化物、或SILKTM(一种硅和低k介质材料的组合物)的旋涂材料42被涂敷。
借助于用旋涂技术涂敷一种材料，此材料被择优淀积在低的位置，使高位置仍然未被涂敷。此外，可以在氮化物膜28随后被清除时用作抗蚀剂的任何材料都可以是适当的旋涂材料。于是，旋涂涂敷方法使氮化物膜28的高处仍然被暴露为了进一步加工。将材料择优淀积在低区中并使高区暴露的其它方法，可以用来在氮化物膜28的顶部上形成膜。
参照图10，通过Si3N4 RIE工艺，氮化物膜28的暴露部分被清除，使仅仅从栅叠层的顶部择优地清除氮化物膜28。借助于清除氮化物膜28的暴露部分，栅叠层的上部免除了氮化物膜28，而硅衬底的顶部仍然被覆盖。氮化物膜28的这种选择性清除，形成了其中由于硅衬底12仍然被覆盖而具有增大的应力的晶体管沟道44。可以用择优清除氮化物膜28并留下旋涂材料42的任何工艺，来清除氮化物膜28。
图11-13示出了另一实施方案，用此实施方案可以形成具有增大的应力的晶体管沟道。参照图11，示出了如图9所示的半导体器件，它具有其上带有栅氧化物14的硅衬底12。硅衬底12具有硅化物区24。具有栅侧壁18的多晶硅栅16位于栅氧化物14上。栅硅化物区26被形成在多晶硅栅16的顶部上，所有这些都是本技术领域熟练人员所知的，且根据所知的实践被实现。此外，示出了具有暴露的高区的氮化物涂层28和旋涂材料42。或者，可以涂敷氧化物层(HDP(高密度等离子体)氧化物或BPSG(硼磷硅酸盐玻璃))，使氮化物膜28的高处仍然被暴露。此外，可在氮化物膜28被随后清除时用作抗蚀剂的任何材料，都可以是适当的旋涂材料。
如图12所示，用CMP清除氮化物膜28的暴露部分和栅叠层顶部区域，晶片被整平。因此，硅衬底12仍然被氮化物膜28覆盖，而栅叠层的顶部被清除。借助于一起清除栅叠层的顶部与其上形成的任何氮化物膜28，就在硅衬底12内形成增大了应力的晶体管沟道46。整平晶片的任何其它已知的方法，都可以被用来清除栅叠层的顶部。
最后，如图13所示，清除旋涂材料42，并在栅叠层的顶部上形成硅化物栅区48。任何择优清除旋涂材料的方法，都可以用于此步骤。得到的结构再次包括被氮化物膜覆盖的衬底，同时免去了栅叠层上部上的氮化物膜。应该指出的是，图11-13所述的方法可以被容易地用来代替栅工艺。
虽然就实施方案而言已经描述了本发明，氮本技术领域熟练人员可以理解的是，能够在所附权利要求的构思与范围内以修正的方式来实施本发明。例如本发明能够被容易地应用于体衬底。
Claims (21)
1.一种在具有设置在衬底上的栅叠层的半导体器件中增大应力的方法，它包括：
沿衬底的表面和栅叠层淀积氮化物膜，其中的氮化物膜在衬底表面上更厚，而在栅叠层部分上更薄，
其中，氮化物膜是不共形的氮化物膜。
2.权利要求1的方法，还包括形成仅仅临近栅叠层下部的衬垫。
3.权利要求2的方法，其中，形成衬垫包括减小衬垫的尺寸。
4.权利要求3的方法，其中，减小衬垫的尺寸包括反应离子刻蚀。
5.权利要求1的方法，其中，淀积氮化物膜包括等离子体增强气相淀积工艺。
6.权利要求1的方法，其中，氮化物膜的淀积在晶体管沟道内提供了增大了的应力。
7.一种在半导体器件中增大应力的方法，它包括：
在栅叠层和衬底表面上淀积氮化物膜层；
在衬底上方的氮化物膜表面上淀积抗蚀剂材料，同时使栅叠层上部附近的氮化物膜的表面暴露；以及
清除栅叠层上的氮化物膜，以便在栅叠层下方的晶体管沟道中提供增大了的应力。
8.权利要求7的方法，还包括清除栅叠层的上部以及设置在其上的氮化物膜。
9.权利要求7的方法，其中，淀积抗蚀剂包括淀积旋涂材料、抗反射涂层、氧化物膜、以及低k材料之一。
10.权利要求9的方法，还包括在栅叠层侧壁的下部处形成衬垫。
11.权利要求9的方法，其中形成衬垫包括沿基本上所有的侧壁形成衬垫并蚀刻衬垫，以便在侧壁的下部处形成衬垫。
12.权利要求9的方法，其中，淀积抗蚀剂包括在低处淀积氧化物层或硼磷硅酸盐玻璃中的至少一种，并使高处仍然被暴露。
13.权利要求8的方法，其中，清除栅叠层部分和设置在其上的氮化物膜包括反应离子刻蚀。
14.权利要求8的方法，其中，清除栅叠层部分和设置在其上的氮化物膜包括化学机械抛光。
15.权利要求7的方法，还包括形成临近栅叠层侧壁的衬垫以及蚀刻衬垫的上部以便仅仅在侧壁下部处形成侧壁。
16.权利要求7的方法，其中，栅的宽度约为60nm，衬垫的宽度约为50nm，且氮化物膜提供约为2.0GPa的应力，晶体管沟道中增大了的应力在栅氧化物下方约5nm处约为每平方厘米4.5×109达因。
17.权利要求7的方法，其中，对于半导体器件的栅宽度约为60nm，衬垫的宽度约为50nm，且氮化物膜应力约为2.0GPa的情况，晶体管沟道中增大了的应力在栅氧化物下方约5nm处大于大约每平方厘米5.5×109达因。
18.一种半导体器件，它包括：
硅衬底；
设置在硅衬底上的栅叠层；
硅衬底和栅叠层上的受应力的氮化物膜，其中，受应力的氮化物膜在硅衬底上更厚，而在栅叠层部分上更薄，
其中，受应力的氮化物膜基本上不存在于栅叠层的上部上。
19.权利要求18的半导体器件，还包括设置在衬底上受应力的氮化物膜与栅叠层之间的使栅叠层的上部仍然被暴露的衬垫。
20.权利要求18的半导体器件，还包括仅仅栅叠层的下部。
21.权利要求20的半导体器件，还包括设置在受应力的氮化物膜上使栅叠层暴露的旋涂材料。
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- 2004-01-16 US US10/707,842 patent/US7118999B2/en not_active Expired - Lifetime
-
2005
- 2005-01-03 TW TW094100066A patent/TWI377596B/zh not_active IP Right Cessation
- 2005-01-14 CN CNB2005100043050A patent/CN100385635C/zh active Active
-
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- 2006-08-18 US US11/465,663 patent/US7790558B2/en active Active
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| JP2002198368A (ja) * | 2000-12-26 | 2002-07-12 | Nec Corp | 半導体装置の製造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI377596B (en) | 2012-11-21 |
| US20060286786A1 (en) | 2006-12-21 |
| US20050158955A1 (en) | 2005-07-21 |
| US7118999B2 (en) | 2006-10-10 |
| CN1641848A (zh) | 2005-07-20 |
| US7462915B2 (en) | 2008-12-09 |
| US7790558B2 (en) | 2010-09-07 |
| US20060281272A1 (en) | 2006-12-14 |
| TW200534348A (en) | 2005-10-16 |
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