CN100388631C - A rapid calculation method for channel coding in mobile communication - Google Patents
A rapid calculation method for channel coding in mobile communication Download PDFInfo
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Abstract
The present invention discloses a rapid calculation method for channel codes in mobile communication, which comprises the following procedures that the relation between the initial state of each path output of a channel code encoder and each shift register in the encoder and each path input bit is obtained according to the logic structure of the channel code encoder used at present; each function representation part of each obtained path output is respectively stored, and a corresponding lookup table is respectively generated for each storage part; when a code is calculated, each code is firstly obtained by all functions of an ith path of output of the channel code encoder, which represent the present calculation, according to each corresponding lookup table, and then modular-two addition is carried out for all the obtained codes so as to obtain the final code of the ith path of output. The calculating speed of channel codes can be greatly increased by the method so that integral business processing capacity is enhanced.
Description
Technical field
The present invention relates to channel coding technology, be meant the quick calculation method of chnnel coding in a kind of mobile communication especially.
Background technology
Convolution code is a kind of channel coding technology that nineteen fifty-five Elias proposes, and has been widely used at present in the communication system, and the 3GPP that has just grown up is also with its chnnel coding as main employing.Specifically, convolutional encoding is that k information bit is encoded into n bit, and the n-k of this group verification unit is not only relevant with k the information code element of this group, and with front N-1 input coding device information-related constantly, N=n+1 wherein, as seen, the code element that is mutually related in the cataloged procedure is Nn.Increase because the error correcting capability of convolution code is the increase with N, and error rate is index decreased with the increase of N that therefore, N is called as constraint length.
Equally, in the convolution code decode procedure, not only from the code character that current time is received, extract decoding information, but also extract for information about in each code character of receiving constantly before will utilizing or later on.In cataloged procedure, made full use of the respectively correlation between the group just because of convolution code, and for block encoding, k is also relative with n less, realizes that the best and accurate optimal decoding are also than being easier to.
The whole cataloged procedure of encoder for convolution codes can be regarded the convolution of another sequence that input message sequence and shift register and XOR connected mode determined as, generally the convolution code note is done that (N), its code efficiency is Rc=k/n for n, k.According to the difference of code efficiency, convolution code comprises again: 1/2 convolution code, 1/3 convolution code or the like, wherein 1/2,1/3 be code efficiency, here, code efficiency also can abbreviate code check as.
Usually, the generator polynomial of encoder for convolution codes is as shown in Equation (1):
G(D)＝A
0+A
1D+...+A
n-1D
n-1+A
nD
n (1)
With 1/2 code check is example, and the generator polynomial of 1/2 encoder for convolution codes is shown in formula (2), formula (3):
G
0(D)＝1+D
2+D
3+D
4+D
8 (2)
G
1(D)＝1+D+D
2+D
3+D
5+D
7+D
8 (3)
In 3GPP, the structure of encoder for convolution codes as shown in Figure 1, wherein, what Fig. 1 a provided is 1/2 encoder for convolution codes, what Fig. 1 b provided is 1/3 encoder for convolution codes.Referring to shown in Figure 1, the encoder for convolution codes of 3GPP comprises eight shift registers, after the different disposal of a list entries through eight shift registers, exports two or three sequences, and concrete output sequence number is relevant with the code check that is adopted.As can be seen from Figure 1, each output bit all is that current input bit carries out the result that XOR obtains with some bit of importing before this.
In fact, the conventional method of convolution coding is exactly to pursue bit operating by the logical construction of generator polynomial decision.Because the difference of generator polynomial, the operand size is also different.Handling the employed XOR instruction of each bit among Fig. 1 is 5 or 7, and operand is quite big like this, is not suitable for high-speed data communication.
At present, two kinds of typical computational methods of convolution coding are: calculate and calculate based on impulse response based on the generator polynomial status items.Wherein, based on the main process of generator polynomial status items Calculation Method is such: at first, bit stream to be encoded is divided into one or more processing units, and described processing unit is preferably consistent with the processing bit wide of processor, and the processing bit wide that has processor now generally is 8,16,32 or the like.Then, store the bit sequence of each status items correspondence, use so that calculate later on.Here, described status items is meant each exponential term of D in the generator polynomial, and for formula (2), formula (3), status items comprises: 1, and D, D
2, D
3, D
4, D
5, D
7, D
8Wherein, the status items 1 corresponding pretreatment unit of working as; The bit sequence of status items D correspondence is than postponing 1 moment when pretreatment unit; Status items D
2Corresponding bit sequence postpones 2 moment than working as pretreatment unit, and the like.At last,, the bit sequence of each status items correspondence is carried out XOR, obtain coded sequence when pretreatment unit according to generator polynomial.Though method computational speed is the fastest can reach lcycle/bit for this, but its computational speed is subjected to the restriction of processor processing bit wide, have only processor bit wide 2 times more than or equal to constraint length, just when W 〉=2 (N-1), could obtain each status items quickly and easily, otherwise speed will be had a greatly reduced quality.And the coded data that this method produces is deposited according to branch road, also needs extra processor expense when branch road merges.
Calculate for convolution coding based on impulse response, as shown in Figure 1 because the input bit of any time t all can produce impulse one time to encoder, current impulse can influence t constantly and later t+1 until t+8 constantly, each corresponding constantly output bit is from c0 to c8.So, just in time incoming bit stream is regarded as impulse one by one, corresponding output code flow is exactly this stack of impulse response one by one.Because the output bit of the impulse response correspondence of " 0 " all is 0, can not consider again, and only consider the impulse response of " 1 ".Therefore, may further comprise the steps based on the impulse response Calculation Method:
1), selects suitable register for use, and carry out initialization according to the data length of coder state.Such as: the encoder constraint length shown in Fig. 1 b is 9, and data length is (9-1)/(1/3)=24, deposits respectively so choose the register of three 32 bits: impulse response accumulation result S, " 1 " impulse response A, encoder output C.
2) calculate the impulse response of " 1 ", and be stored in the register of corresponding A.
3) carry out iteration as follows:
A. get an input bit, judge that input bit is 0 or 1, if 1, execution in step b then, otherwise execution in step c;
B. the bit stream with register A adds up into register S;
C. three the input register C that the bit stream among the register S moved to left, these three is exactly the encoded radio of input bit, and the result that register S moves to left after three still is retained among the register S;
D. the encoded radio among the last output register C returns step a.
Described computational methods based on impulse response, though computational speed also is the lcycle/bit level, be applicable to high-speed data communication, but this method is the mode of a serial all the time, because a deterministic process all will be arranged at each input bit, can not parallel processing one blocks of data, therefore the raising on computational speed still is conditional.
Summary of the invention
In view of this, main purpose of the present invention is to provide the quick calculation method of chnnel coding in a kind of mobile communication, can improve the computational speed of chnnel coding greatly, and then improves whole traffic handing capacity.
For achieving the above object, technical scheme of the present invention is achieved in that
The quick calculation method of chnnel coding in a kind of mobile communication, this method may further comprise the steps:
A. according to the logical construction of currently used channel code encoder, obtain the initial condition of each shift register in every road output of this channel code encoder and the encoder and the relation between the input bit of every road;
Each function representation part storage respectively of b. the every road that is obtained being exported, and the different values of the independent variable that comprises with each storage area are allocation index, generate the look-up table of each storage area correspondence respectively, comprise the different values of described independent variable and the corresponding relation between the output of every road in the described look-up table;
C. when calculation code, will represent that earlier all functions current calculating, the output of channel code encoder i road respectively according to each self-corresponding look-up table acquisition coding separately, carry out all codings that obtained mould 2 again and add the final coding that obtains the output of i road.
Wherein, step a also comprises: obtain the initial condition of each shift register in the update mode of each shift register in the currently used channel code encoder and the encoder and the relation between the input bit of every road simultaneously.
In the such scheme, further comprise between step b and the step c: judge whether each storage area needs to continue segmentation, if desired, then current storage area further is divided into sub-storage area more than, and each the sub-storage area after dividing is generated corresponding look-up table respectively by specified criteria; Otherwise, direct execution in step c.Accordingly, this method further comprises: set in advance the condition that need segment, then described judge whether to be subdivided into judge whether to meet sub-divided condition, if meet, then need the segmentation; Otherwise do not need segmentation.Wherein, the described condition of segmenting is: the memory space of the storage area of difference described in the step b is greater than given memory space.
In the such scheme, if current storage area further is divided into sub-storage area more than, then step c is: will represent that all functions current calculating, channel code encoder i road output obtain separately coding according to the look-up table of sub-storage area correspondence separately respectively, and again the coding of each sub-storage area of correspondence of all acquisitions be carried out mould 2 and add the coding that obtains the output of i road.
In the such scheme, the content of each storage area can be stored in the table respectively.In addition, described channel code encoder is: the encoder for convolution codes of the encoder for convolution codes of 1/2 code check or 1/3 code check or Turbo code encoder.
The quick calculation method of chnnel coding in the mobile communication provided by the present invention, because logical construction according to current channel code encoder correspondence, obtain in advance under the treatment state of different input bits, the initial condition of each shift register and the relation between the input bit position, every road in every road output of current channel code encoder and the encoder, and according to the corresponding look-up table of this relation generation; When carrying out corresponding chnnel coding, export on the every road that directly utilizes the look-up table that generates in advance to obtain under the channel code encoder current state, so can improve the computational speed of chnnel coding greatly.Because the present invention is based on the parallel processing realization, so have very high degree of parallelism, handle flexibly, be not subject to processing the restriction that device is handled bit wide; And one-time-reach-place without any need for closing dataway operation, therefore can not bring extra expense yet.
Description of drawings
Fig. 1 a is the logical construction schematic diagram of 1/2 encoder for convolution codes among the 3GPP;
Fig. 1 b is the logical construction schematic diagram of 1/3 encoder for convolution codes among the 3GPP;
Fig. 2 is the structure composition diagram of common channel code coder;
Fig. 3 is the realization flow figure of the inventive method.
Embodiment
Basic thought of the present invention is exactly: according to the logical construction of current channel code encoder correspondence, obtain in advance under the treatment state of different input bits, the initial condition of each shift register and the relation between the input bit position, every road in every road output of current channel code encoder and the encoder, and the initial condition of each shift register and the relation between the input bit of every road in the update mode of each shift register and the encoder in the encoder, and generate corresponding look-up table respectively according to described relation; When carrying out corresponding chnnel coding, directly utilize the look-up table that generates in advance to obtain the every road output under the channel code encoder current state or the update mode of shift register.
As shown in Figure 2, Fig. 2 is a general channel code encoder logic structure, total N road input of this encoder and the output of L road, and the state of supposing encoder is by R
1, R
2..., R
kExpression, and R
k～R
1Initial condition be C
k～C
1Certainly, encoder may not have state yet, such as: encoder only adds circuit by mould 2 and forms, and that is to say, the output of encoder is only relevant with input at that time, in this case, only needs R
k～R
1(C
k～C
1) remove.Suppose INPUT
1A byte of input is M
1=M
1,8, M
1,7, M
1,6, M
1,5, M
1,4, M
1,3, M
1,2, M
1,1, M wherein
1,8Be highest significant position (MSB), M
1,1Be least significant bit (LSB); From INPUT
2A byte of input is M
2=M
2,8, M
2,7, M
2,6, M
2,5, M
2,4, M
2,3, M
2,2, M
2,1, M wherein
2,8Be MSB, M
2,1Be LSB; The rest may be inferred, and a byte of importing from INPUT is M
n=M
N, 8, M
N, 7, M
N, 6, M
N, 5, M
N, 4, M
N, 3, M
N, 2, M
N, 1, M wherein
N, 8Be MSB, M
N, 1Be LSB.Suppose that encoder is at all input bit M
N, iAfter (1≤n≤N, 1≤i≤8) end-of-encode, the bit of output is designated as OUT respectively according to sequencing
1, OUT
2..., OUT
LSo, export and encoder update mode R through the L road of transform coder
1～R
kExpression formula shown in table one and table two, wherein table one is the expression formula of general encoder for convolution codes L road output, table two is the expression formula of general encoder for convolution codes update mode.
| OUT 1＝φ 1(C 1，C 2，....，C k)+f 1，1(M 1，1，M 1，2，...M 1，8)+...+f 1，N(M N，1，M N，2...，M N，8) |
| OUT 2＝φ 2(C 1，C 2，....，C k)+f 2，1(M 1，1，M 1，2，...M 1，8)+...+f 2，N(M N，1，M N，2...，M N，8) |
| OUT 3＝φ 3(C 1，C 2，....，C k)+f 3，1(M 1，1，M 1，2，...M 1，8)+...+f 3，N(M N，1，M N，2...，M N，8) |
| ...... |
| OUT L＝φ L(C 1，C 2，....，C k)+f L，1(M 1，1，M 1，2，...M 1，8)+...+f L，N(M N，1，M N，2...，M N，8) |
Table one
In the table one, φ
i(C
1, C
2...., C
k) represent it is C
1..., C
kA function, C
1To C
kBe the initial condition of shift register, φ
iSubscript i represent it is the function of i road output; f
1,1(M
1,1, M
1,2... M
1,8) represent it is M
1,1, M
1,2... M
1,8Function, M wherein
1,2The expression input, specifically be exactly, second bit in the byte of first via input, by that analogy.f
1,1In the subscript first 1 expression first via output, the input of second the 1 expression first via; "+" expression mould 2 adds.
| R 1＝g 1(C 1，C 2，....，C k)+h 1，1(M 1，1，M 1，2，...M 1，8)+...+h 1，N(M N，1，M N，2...，M N，8) |
| R 2＝g 2(C 1，C 2，....，C k)+h 2，1(M 1，1，M 1，2，...M 1，8)+...+h 2，N(M N，1，M N，2...，M N，8) |
| R 3＝g 3(C 1，C 2，....，C k)+h 3，1(M 1，1，M 1，2，...M 1，8)+...+h 3，N(M N，1，M N，2...，M N，8) |
| ...... |
| R k＝g k(C 1，C 2，....，C k)+h k，1(M 1，1，M 1，2，...M 1，8)+...+h k，N(M N，1，M N，2...，M N，8) |
Table two
Same, in the table two, g
i(C
1, C
2...., C
k) represent it is C
1..., C
kA function, C
1To C
kBe the initial condition of shift register, g
iSubscript i represent it is the function of i road output; h
1,1(M
1,1M
1,2... M
1,8) represent it is M
1,1, M
1,2... M
1,8Function, M wherein
1,2The expression input, specifically be exactly, second bit in the byte of first via input, by that analogy.h
1,1In the subscript first 1 expression first via output, the input of second the 1 expression first via; "+" expression mould 2 adds.
In fact, the concrete processing procedure of calculating channel coding of the present invention may further comprise the steps as shown in Figure 3:
Step 301: according to the logical construction of currently used channel code encoder, obtain the initial condition of each shift register in output of the every road of this encoder and the encoder and the relation between the input bit of every road, obtain the initial condition of each shift register in the update mode of each shift register in this encoder and the encoder and the relation between the input bit of every road simultaneously;
Step 302: each function representation part that export on the every road that is obtained is stored respectively, such as: table one is divided into N+1 sublist, shown in table three, table four, table five;
| OUT 1＝φ 1(C 1，C 2，....，C k) |
| OUT 2＝φ 2(C 1，C 2，....，C k) |
| OUT 3＝φ 3(C 1，C 2，....，C k) |
| ...... |
| OUT L＝φ L(C 1，C 2，....，C k) |
Table three
| OUT 1＝f 1，1(M 1，1，M 1，2，...M 1，8) |
| OUT 2＝f 2，1(M 1，1，M 1，2，...M 1，8) |
| OUT 3＝f 3，1(M 1，1，M 1，2，...M 1，8) |
| ...... |
| OUT L＝f L，1(M 1，1，M 1，2，...M 1，8) |
Table four
| OUT 1＝f 1，N(M N，1，M N，2...，M N，8) |
| OUT 2＝f 2，N(M N，1，M N，2...，M N，8) |
| OUT 3＝f 3，N(M N，1，M N，2...，M N，8) |
| ...... |
| OUT L＝f L，N(M N，1，M N，2...，M N，8) |
Table five
Step 303: generate the look-up table of corresponding each storage area respectively, just, generate the look-up table of N+1 sublist respectively;
Step 304: when calculation code, all functions that to represent the i road output of current calculating earlier obtain separately coding according to each self-corresponding look-up table respectively, all codings that obtained are carried out mould 2 again and add and can obtain this road and export desired final coding.
Between step 302 and step 303, can also increase a judgement, whether the part of judging storage respectively also need continue segmentation, if desired, then current storage area further is divided into sub-storage area more than, and each the sub-storage area after dividing is generated corresponding look-up table respectively by specified criteria.Can set in advance sub-divided condition, such as: the memory space of look-up table is greater than the just segmentation again of certain set-point, so, just decide during segmentation and how to segment according to the memory space set-point, be exactly specifically, the look-up table stores amount of current storage area is 64K, and set-point is 32K, so, current storage area further will be divided into two storage areas again.If segment, then step 304 will be an allocation index with the contained independent variable of each sub-storage area respectively also, searches corresponding look-up table, again all lookup results is carried out XOR.
For the storage that above-mentioned each step is mentioned, a table can be set store, if certain two table is divided from certain table, then these two tables can be described as the sublist of former table.
Embodiment: the convolution coding with 1/2 code check shown in Fig. 1 a is an example.
According to the 3GPP standard code, the encoder for convolution codes of 3GPP 1/2 code check has one tunnel output Input, two-way output Output0 and Output1, and this encoder adopts eight shift registers, and concrete logical construction is as shown in Figure 1a.In the present embodiment, each function representation part of every road output is just specifically represented by corresponding shift register initial condition and input bit position.
The used shift register of encoder from left to right is designated as respectively shown in setting Fig. 1 a: D8, D7, D6, D5, D4, D3, D2, D1; The initial condition of each shift register is designated as respectively: C8, C7, C6, C5, C4, C3, C2, C1; A byte of input is designated as M=M8M7M6M5M4M3M2M1, and wherein M8 is MSB, and M1 is LSB.And when input M1 bit, the output Output0 of encoder is designated as OUT1, and Output1 is designated as OUT2; When input M2 bit, the output Output0 of encoder is designated as OUT3, and Output1 is designated as OUT4; The rest may be inferred, import respectively M3 ..., during the M8 bit, the output Output0 and the Output1 of encoder are designated as respectively: OUT5, OUT6, OUT7, OUT8, OUT9, OUT10, OUT11, OUT12, OUT13, OUT14, OUT15, OUT16.The process of then calculating 1/2 convolution coding is:
The first step: according to the logical construction that Fig. 1 a provides, in the time of can obtaining bit of every input, the relation between the current update mode of shift register and shift register initial condition and the input bit, as shown in Table 6.When the input bit not, equal C1 such as: shift register D1; Behind first bit of input, equal C2; Behind second bit of input, equal C3; By that analogy.
| CLK | INPUT | D8 | D7 | D6 | D5 | D4 | | D2 | D1 | |
| 0 | C8 | C7 | C6 | C5 | C4 | | C2 | C1 | ||
| 1 | M1 | M1 | C8 | C7 | C6 | C5 | | C3 | C2 | |
| 2 | M2 | M2 | M1 | C8 | C7 | C6 | C5 | C4 | C3 | |
| 3 | M3 | M3 | M2 | M1 | C8 | C7 | C6 | C5 | C4 | |
| 4 | M4 | M4 | M3 | M2 | M1 | C8 | C7 | C6 | C5 | |
| 5 | M5 | M5 | M4 | M3 | M2 | M1 | C8 | C7 | C6 | |
| 6 | M6 | M6 | M5 | M4 | M3 | M2 | M1 | C8 | C7 | |
| 7 | M7 | M7 | M6 | M5 | M4 | M3 | M2 | M1 | C8 | |
| 8 | M8 | M8 | M7 | M6 | M5 | M4 | M3 | M2 | M1 |
Table six
Simultaneously, the logical construction that provides according to Fig. 1 a also, in the time of can obtaining bit of every input, the relation between the output of 1/2 encoder for convolution codes and shift register initial condition and the input bit, as shown in Table 7.Such as: behind first bit of input, first of this 1/2 encoder for convolution codes is output as M1+C7+C6+C5+C1; Second is output as M1+C8+C7+C6+C4+C2+C1, by that analogy.Wherein, "+" in the table adds for mould 2, below each the table in "+" represent that all mould 2 adds.
| OUT1＝M1+C7+C6+C5+C1 |
| OUT2＝M1+C8+C7+C6+C4+C2+C1 |
| OUT3＝M2+C8+C7+C6+C2 |
| OUT4＝M2+M1+C8+C7+C5+C3+C2 |
| OUT5＝M3+M1+C8+C7+C3 |
| OUT6＝M3+M2+M1+C8+C6+C4+C3 |
| OUT7＝M4+M2+M1+C8+C4 |
| OUT8＝M4+M3+M2+M1+C7+C5+C4 |
| OUT9＝M5+M3+M2+M1+C5 |
| OUT10＝M5+M4+M3+M2+C8+C6+C5 |
| OUT11＝M6+M4+M3+M2+C6 |
| OUT12＝M6+M5+M4+M3+M1+C7+C6 |
| OUT13＝M7+M5+M4+M3+C7 |
| OUT14＝M7+M6+M5+M4+M2+C8+C7 |
| OUT15＝M8+M6+M5+M4+C8 |
| OUT16＝M8+M7+M6+M5+M3+M1+C8 |
Table seven
If directly generate the pairing look-up table of table seven, obviously incorrect, because total 16 independents variable of M8～M1, C8～C1 in the table are corresponding, have 2
16=65536 (64K) plant combined situation, so can cause the look-up table stores amount too big, therefore, continue to carry out second step.
Second step: with obtained, storing respectively of representing each output with the input bit relevant portion with shift register initial condition relevant portion, that is: table seven is divided into table eight, two sublists of table nine, wherein table eight is each output expression part relevant with input bit, and table nine is each output expression part relevant with the shift register initial condition.
| OUT1＝M1 |
| OUT2＝M1 |
| OUT3＝M2 |
| OUT4＝M2+M1 |
| OUT5＝M3+M1 |
| OUT6＝M3+M2+M1 |
| OUT7＝M4+M2+M1 |
| OUT8＝M4+M3+M2+M1 |
| OUT9＝M5+M3+M2+M1 |
| OUT10＝M5+M4+M3+M2 |
| OUT11＝M6+M4+M3+M2 |
| OUT12＝M6+M5+M4+M3+M1 |
| OUT13＝M7+M5+M4+M3 |
| OUT14＝M7+M6+M5+M4+M2 |
| OUT15＝M8+M6+M5+M4 |
| OUT16＝M8+M7+M6+M5+M3+M1 |
Table eight
| OUT1＝C7+C6+C5+C1 |
| OUT2＝C8+C7+C6+C4+C2+C1 |
| OUT3＝C8+C7+C6+C2 |
| OUT4＝C8+C7+C5+C3+C2 |
| OUT5＝C8+C7+C3 |
| OUT6＝C8+C6+C4+C3 |
| OUT7＝C8+C4 |
| OUT8＝C7+C5+C4 |
| OUT9＝C5 |
| OUT10＝C8+C6+C5 |
| OUT11＝C6 |
| OUT12＝C7+C6 |
| OUT13＝C7 |
| OUT14＝C8+C7 |
| OUT15＝C8 |
| OUT16＝C8 |
Table nine
The 3rd step: be allocation index with the independent variable in table eight or the table nine respectively, generate the look-up table of correspondence table eight or table nine storage area.
Here, be example with table eight, the detailed process that generates look-up table is: 256 kinds of values listing M1～M8 earlier; According to the relation of each output in the table eight, calculate pairing each output valve of every kind of different values of M1～M8 again with M1～M8; With M1～M8 is allocation index, all stores into all output valves in the register; 256 kinds of values about each output of Xing Chenging are exactly required look-up table at last.Such as: the value of M1～M8 is 01111010 o'clock, because OUT5 is M3+M1, M3=1 here, M1=0, the value that then calculates OUT5 is 1, the computational methods of other output are identical therewith.
The 4th step: when carrying out convolutional encoding, respectively two look-up tables are carried out addressing actual, two values that will obtain are then carried out mould 2 and are added the encoded radio that gets final product to the end.That is to say, obtain the value of two corresponding OUTn respectively according to two look-up tables, then the value of two OUTn is carried out mould 2 and add, the result who obtains is the output of final OUTn.
Because his-and-hers watches eight and table nine generate look-up table respectively, therefore required memory space is 2
8* 2=512 word is with respect to 2
16, memory space is reduced to original 1/128.
Computational methods and the foregoing description for the convolution coding of 1/3 code check shown in Fig. 1 b are identical, and just the encoder for convolution codes of 1/3 code check has three tunnel outputs, and is corresponding, 24 OUT can occur.For other chnnel coding, as long as it can calculate by determining logical construction, can adopt method of the present invention, such as: Turbo coding or the like, concrete basic implementation procedure is also all same as the previously described embodiments.
Method of the present invention both can save time for single-bit is calculated, again can conserve space.For example: if environment is very strict to space requirement, 16 bits can be divided into two 8 bits, the space can be saved and is original 2
-7=1/128; Also 8 bits can be divided into two 4 bits, the space can be saved and is original 1/8; Simultaneously, can also save two bits or three bits darnings is the complicated processes of a word or byte, has also saved the operating time certainly.
Method of the present invention also is applicable to individual bit, does not promptly become the bit of a byte, only needs former positions of sign indicating number that addressing is obtained to remove and gets final product.In addition, the output bit flow of the inventive method is the road of closing of the output bit flow of each branch road and exports, and does not need the independent dataway operation that closes.
For the amount of calculation of the inventive method, can specifically calculate, such as: input code flow is one group of per 8 bit, and then 1/2 code check, constraint length are that the amount of calculation situation of 9 encoder for convolution codes is twice table lookup operation and an xor operation; During 1/3 code check, only need the storage mode of form has been stored just from changing into according to double word according to the word storage, do not need extra expense, just increase memory space.In addition, adopt method of the present invention, for encoder for convolution codes shown in Figure 1, its computational speed can reach the speed that is lower than lcycle/bit.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.
Claims (8)
1. the quick calculation method of chnnel coding in the mobile communication is characterized in that this method may further comprise the steps:
A. according to the logical construction of currently used channel code encoder, obtain the initial condition of each shift register in every road output of this channel code encoder and the encoder and the relation between the input bit of every road;
Each function representation part storage respectively of b. the every road that is obtained being exported, and the different values of the independent variable that comprises with each storage area are allocation index, generate the look-up table of each storage area correspondence respectively, comprise the different values of described independent variable and the corresponding relation between the output of every road in the described look-up table;
C. when calculation code, will represent that earlier all functions current calculating, the output of channel code encoder i road respectively according to each self-corresponding look-up table acquisition coding separately, carry out all codings that obtained mould 2 again and add the final coding that obtains the output of i road.
2. method according to claim 1, it is characterized in that step a also comprises: obtain the initial condition of each shift register in the update mode of each shift register in the currently used channel code encoder and the encoder and the relation between the input bit of every road simultaneously.
3. method according to claim 1, it is characterized in that, further comprise between step b and the step c: judge whether each storage area needs to continue segmentation, if desired, then current storage area further is divided into sub-storage area more than, and each the sub-storage area after dividing is generated corresponding look-up table respectively by specified criteria; Otherwise, direct execution in step c.
4. method according to claim 3 is characterized in that, this method further comprises: set in advance the condition that need segment, then described judge whether to be subdivided into judge whether to meet sub-divided condition, if meet, then need the segmentation; Otherwise do not need segmentation.
5. method according to claim 4 is characterized in that, the described condition of segmenting is: the memory space of the storage area of difference described in the step b is greater than given memory space.
6. method according to claim 3, it is characterized in that, if current storage area further is divided into sub-storage area more than, then step c is: will represent that all functions current calculating, channel code encoder i road output obtain separately coding according to the look-up table of sub-storage area correspondence separately respectively, and again the coding of each sub-storage area of correspondence of all acquisitions be carried out mould 2 and add the coding that obtains the output of i road.
7. method according to claim 1 is characterized in that, the content of each storage area is stored in the table respectively.
8. method according to claim 1 is characterized in that, described channel code encoder is: the encoder for convolution codes of the encoder for convolution codes of 1/2 code check or 1/3 code check or Turbo code encoder.
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| CN1338824A (en) * | 2000-08-17 | 2002-03-06 | 华为技术有限公司 | Method and decoder for decoding turbo code |
| CN1433238A (en) * | 2001-11-09 | 2003-07-30 | 生命扫描有限公司 | Data character string authorizing system and method |
| US6609226B1 (en) * | 2000-04-10 | 2003-08-19 | Nortel Networks Limited | Networking device and method for making cyclic redundancy check (CRC) immune to scrambler error duplication |
| JP2003264468A (en) * | 2002-03-12 | 2003-09-19 | Sharp Corp | Viterbi decoder |
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| US6233711B1 (en) * | 1997-09-02 | 2001-05-15 | Sony Corporation | Turbo coding, decoding devices and turbo coding, decoding methods |
| CN1283898A (en) * | 1999-07-06 | 2001-02-14 | 深圳市华为技术有限公司 | Method for estimating code error rate of wireless channel in digital mobile communication system |
| US6609226B1 (en) * | 2000-04-10 | 2003-08-19 | Nortel Networks Limited | Networking device and method for making cyclic redundancy check (CRC) immune to scrambler error duplication |
| CN1338824A (en) * | 2000-08-17 | 2002-03-06 | 华为技术有限公司 | Method and decoder for decoding turbo code |
| CN1433238A (en) * | 2001-11-09 | 2003-07-30 | 生命扫描有限公司 | Data character string authorizing system and method |
| JP2003264468A (en) * | 2002-03-12 | 2003-09-19 | Sharp Corp | Viterbi decoder |
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