CN100389470C - Reference eurrent producing circuit of multiple allocation flash storage - Google Patents
Reference eurrent producing circuit of multiple allocation flash storage Download PDFInfo
- Publication number
- CN100389470C CN100389470C CNB02142263XA CN02142263A CN100389470C CN 100389470 C CN100389470 C CN 100389470C CN B02142263X A CNB02142263X A CN B02142263XA CN 02142263 A CN02142263 A CN 02142263A CN 100389470 C CN100389470 C CN 100389470C
- Authority
- CN
- China
- Prior art keywords
- reference current
- flash memory
- memory unit
- grid
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Abstract
The present invention relates to a reference current generation circuit of a multibit flash memory, which applies an identical boosted word line voltage to the grid electrodes of the reference storage units of different reference current generation units. The reference current generation circuit also uses the gateway width of different reference storage units to obtain reference currents of different levels as required, so that the problem of the different drift of the reference current which changes as temperature and a mains voltage Vcc can be effectively improved.
Description
Technical field
The invention relates to a kind of multiple bit flash memory (Multiple Bit Flash Memory), and particularly relevant for a kind of reference current generating circuit of multiple bit flash memory.
Background technology
Flash memory is that a kind of data of can carrying out repeatedly write (Program), read (Read) and the non-voltile memory (Non-Volatile Memory) of removing actions such as (Erase), owing to the data that are stored in wherein can not disappear because of the interruption of power supply supply, and be easy to change the characteristic of its stored data, thereby be applied at large in the electronic equipment such as personal computer through removing with write activity.
Typical flash memory is made up of many flash memory cells (Flash Cell), and each flash memory cell then is commonly used to store the data of a position.The structure of flash memory cell is made the floating boom utmost point (Floating Gate) and control grid (Control Gate) with the polysilicon that mixes, then be separated by between the floating boom utmost point and the control grid, and be separated by with tunnel oxide (Tunnel Oxide) between the floating boom utmost point and substrate with dielectric layer.When the operation that flash memory cell write/clear data, apply bias voltage in its control grid with drain electrode, so that the electronics injection floating boom utmost point or electronics pulled out from the floating boom utmost point.And during the data in reading flash memory cell, then on the control grid, apply a word line voltage (Word-Line Voltage), the electriferous state of the floating boom utmost point can influence the open/close state of its lower channel (Channel) at this moment, and the open/close state of this channel is the foundation of interpretation data value " 0 " or " 1 ".
Along with the progress of semiconductor science and technology and the demand that increases for flash capacity, a kind of multiple bit flash memory so develop, that is to say that each flash memory cell wherein stores the above data in two positions.Therefore, when reading the stored data of flash memory cell, the electric current and the reference current that read must be made comparisons, judge the data value that it is stored.
Please refer to shown in Figure 1ly, it is start voltage (Threshold Voltage) distribution schematic diagram of 2 flash memory cells of a flash memory.Horizontal ordinate among the figure is represented start voltage V
ThSize, ordinate are then represented each start voltage V
ThThe quantity of flash memory cell, its distributed number situation can present a Gaussian distribution as shown in the figure usually.Show among the figure, when removing flash memory cell, its start voltage V
ThTo be positioned at below the EV; When writing " 01 " data value to flash memory cell, its start voltage V
ThTo be positioned at PV
1To being lower than R
2Between; When writing " 10 " data value to flash memory cell, its start voltage V
ThTo be positioned at PV
2To being lower than R
3Between; And when writing " 11 " data value to flash memory cell, its start voltage V
ThThen be positioned at PV
3More than.So when carry out removing flash memory cell, the word line voltage that applies EV in the control grid, and is judged by the electric current that reads whether remove action finishes; When execution writes " 01 ", when " 10 " reach " 11 " data value to flash memory cell, will apply PV respectively
1, PV
2And PV
3Word line voltage in the control grid, and judge by the electric current that reads whether write activity is finished; And when carrying out the data value that reads the flash memory cell storage, then apply R respectively
1, R
2And R
3Word line voltage in the control grid, and judge that by the electric current that reads the data value that reads is why, wherein and with the reference current that electric current and reference current generating circuit produced that reads makes comparisons, with the data value of judging that it reads.
Known in order to reach the employed reference current generating circuit of above-mentioned purpose, reach with the grid that word line voltage (Boosted Word-Line Voltage is called for short BWLV) puts on different reference memory units (reference Cell) that raises of different accurate positions.As being example, because of total EV, PV with two above-mentioned flash memory cells
1, PV
2, PV
3, R
1, R
2And R
3Deng clear confirmation (Erase Verify)/write affirmation (Program Verify)/the read word line voltages of 7 kinds of different accurate positions of (Read), so need 7 kinds the word line voltages that raise of different accurate positions finish, as being that the word line voltages that raise that example then more must 15 kinds of different accurate positions are finished with 3 flash memory cells.Because respectively raising word line voltage is subject to temperature and supply voltage V
CCThe influence that changes and different variations is arranged causes each reference current that reference current generating circuit produced in this way, also will be along with temperature and supply voltage V
CCVariation and different drifts is arranged.
Summary of the invention
In view of this, the invention provides a kind of reference current generating circuit, it can improve reference current along with temperature and supply voltage V
CCVariation and the problems of different drifts are arranged.
For reaching above-mentioned and other purpose, the invention provides a kind of reference current generating circuit, be applicable to a multiple bit flash memory, this reference current generating circuit comprises most reference current generation units, and each reference current generation unit then comprises a load and a reference memory unit.Load has first link and second link, and first link connects a working power, and second link then connects first source/drain electrode of reference memory unit, second source of reference memory unit/grounded drain, and grid connects one and raises word line voltage.Wherein, the grid of each reference current generation unit is connected to identical one and raises word line voltage, and the width of the grid groove of the reference memory unit of each reference current generation unit, then according to the size of a reference current of the required generation of reference current generation unit and difference.
In the preferred embodiment of the present invention, its reference memory unit is a virtual memory cell (Dummy Cell), and so-called virtual memory cell links together the floating boom utmost point of the flash memory cell of the multiple bit flash memory of same structure and forms with the control grid.Wherein, in order to be easier to grasp the characteristic of reference memory unit, event is made as the length of the grid groove of the reference memory unit of each reference current generation unit identical, and the size of the length of the grid groove of reference memory unit, the length of the grid groove of the flash memory cell of more multiple bit flash memory is of a size of greatly, and for example the length of the grid groove of design reference storage unit is of a size of 1 μ m.
In addition, in order further to improve the characteristic of reference memory unit, can will be made in the same layout block (bank), and a reference memory unit or most the same reference storage unit of taking wherein produce reference current more than the required reference memory unit of each reference current generation unit.And most same reference storage unit in taking same layout block are connected in parallel all same reference storage unit of taking together, to produce reference current when producing reference current.
By in the above-mentioned explanation as can be known, because a kind of reference current generating circuit provided by the invention uses identical one to raise word line voltage, put on the grid of different reference memory units, and with the width of the grid groove of different reference memory units, reach the reference current of required different accurate positions, so can effectively improve reference current along with temperature and supply voltage V
CCVariation and the problems of different drifts are arranged.
For above and other objects of the present invention, feature and advantage can be become apparent, hereinafter special with preferred embodiment, and cooperate appended graphicly, elaborate.
Description of drawings
Fig. 1 shows the start voltage distribution schematic diagram of two flash memory cells of a flash memory;
Fig. 2 shows a kind of reference current generating circuit synoptic diagram of the preferred embodiment according to the present invention;
Fig. 3 shows the reference current relation curve synoptic diagram of a kind of reference current generating circuit of the preferred embodiment according to the present invention.
Label declaration:
200 reference current generating circuits
210,270 loads
211,271 first links
212,272 second links
213,273 first source/drain electrodes
214,274 second source/drain electrodes
215,275 grids
Embodiment
Please refer to shown in Figure 2ly, it is a kind of reference current generating circuit synoptic diagram according to a preferred embodiment of the present invention.Show among the figure that this reference current generating circuit 200 comprises m reference current generation unit bank
1～bank
mThe value of m need use the flash memory unit bit of the multiple bit flash memory of this reference current generating circuit 200 to decide on it herein, as being then m=7 of example with 2 flash memory cells, with 3 flash memory cells is then m=15 of example, then the rest may be inferred for the flash memory cell of other figure place, will be that example illustrates with 2 flash memory cells that is m=7 below.
As being that example then will have bank among the figure with 2 flash memory cells
1～bank
7Deng totally 7 reference current generation units, reference current generation unit bank
1The reference memory unit k that comprises load 210 and be connected in parallel
11～k
1n, the reference memory unit k that reference current generation unit bank7 then comprises load 270 and is connected in parallel
71～k
7n, the structure of reference current generation unit bank2～bank6 that other does not illustrate also together.
Wherein, reference memory unit k
11～k
7nFor example be a virtual memory cell (DummyCell), also soon the floating boom utmost point of the flash memory cell of the multiple bit flash memory of same structure links together with the control grid.Because of the general larger-size manufacture craft of grid groove, its characteristic can be easy to grasp, so in order to be easier to grasp this reference memory unit k
11～k
7nCharacteristic, make the reference current of generation more accurate, be with this reference memory unit k
11～k
7nThe size of length of grid groove, make to such an extent that the length of grid groove of flash memory cell of more multiple bit flash memory is of a size of greatly, for example when the manufacture craft of multiple bit flash memory is used 0.18 μ m manufacture craft, can be with reference memory unit k
11～k
7nGrid groove length be designed and sized to 1 μ m.
In addition, when topological design, in order further to improve reference memory unit k
11～k
7nCharacteristic, can be with each reference current generation unit bank
1～bank
7Required reference memory unit k
11～k
7nBe made in individually in the same layout block (bank).Also be reference memory unit k
11～k
1nBe made in the same layout block, and reference memory unit k
71～k
7nAlso be made in another layout block, and select for use the reference memory unit of non-layout block border to use, to reduce the characteristic variations factor that edge effect causes in each layout block.
As shown in the figure, the load 210 of reference current generation unit bank1 has first link 211 and second link, 212, the first links, 211 connections, one working power V
DD, 212 of second links connect reference memory unit k
11～k
1nDeng the first source/drain electrode 213 that is connected in parallel, reference memory unit k
11～k
1nDeng second source that is connected in parallel/214 ground connection of drain electrode, grid 21 5 is connected in parallel to one and raises word line voltage BWLV.In addition, except the reference memory unit k of above-mentioned explanation
11～k
1nThe size of length of grid groove, make to such an extent that the length of grid groove of flash memory cell of more multiple bit flash memory is of a size of greatly, for example be outside the 1 μ m, and with reference memory unit k
11～k
1nThe size of width of grid groove, according to the reference current Id of required generation
1Size make.
Other is reference current generation unit bank
7Load 270 have first link 271 and second link, 272, the first links 271 connect a working power V
DD, 272 of second links connect reference memory unit k
71～k
7nDeng the first source/drain electrode 273 that is connected in parallel, reference memory unit k
71～k
7nDeng second source that is connected in parallel/274 ground connection of drain electrode, grid 275 is connected in parallel to one and raises word line voltage BWLV.In addition, except the reference memory unit k of above-mentioned explanation
71～k
7nThe size of length of grid groove, make to such an extent that the length of grid groove of flash memory cell of more multiple bit flash memory is of a size of greatly, for example be outside the 1 μ m, and with reference memory unit k
71～k
7nThe size of width of grid groove, according to the reference current Id of required generation
7Size make.
Wherein, because of each reference current generation unit bank
1～bank
7The grid 215～275 that is connected in parallel is connected to identical one and raises word line voltage BWLV, and because of grid groove width W, the length of grid channel L of the reference current Id that produces and reference memory unit itself, raise word line voltage BWLV and start voltage Vth concerns as follows:
Id∝?W/L(BWLV-Vth)
And each reference memory unit k
11～k
7nLength of grid channel L all be designed to identically in the present embodiment, for example be 1 μ m, so start voltage V
ThAlso identical, in addition with each reference memory unit k
11～k
7nThe grid groove width W according to the reference current Id of required generation
1～Id
7Size make, to obtain different reference current Id
1～Id
7, for example as reference memory unit k
11～k
1nGrid groove width W when being 1 μ m, reference memory unit k then
21～k
2nThe grid groove width W be 2 μ m, the rest may be inferred to reference memory unit k
71～k
7nThe grid groove width W be 7 μ m, its relation curve is as shown in Figure 3.
Each above-mentioned reference current generation unit bank
1～bank
7Though be with most identical reference memory unit k
11～k
1n... k
71～k
7nWait and produce different reference current Id
1～Id
7, or also can further ask for its mean value as reference electric current I d
1～Id
7So being familiar with the operator should know, also can be at each reference current generation unit bank
1～bank
7In, a reference memory unit of only taking wherein produces reference current Id
1～Id
7For example at reference current generation unit bank
1In, only take reference memory unit k wherein
11Produce reference current Id
1, and in reference current generation unit bank7, only take reference memory unit k wherein
71Produce reference current Id
7, other reference memory unit is not then incorporated in this reference current generating circuit.
In sum, the present invention has following advantage at least:
1, owing to uses identical one to raise word line voltage, put on the grid of different reference memory units, with the width of the grid groove of different reference memory units, reach the reference current of required different accurate positions, again so can effectively improve reference current along with temperature and supply voltage V
CCVariation and the problems of different drifts are arranged.
2, since use non-critical size (non-critical dimension) reference memory unit grid groove width and length and select that one or most individual reference memory units of most reference memory units produce reference current in the same layout block (bank), so more easily grasp the characteristic of each reference memory unit.
Though the present invention with preferred embodiment openly as above; right its is not in order to limiting the present invention, anyly is familiar with this operator, without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (4)
1. a reference current generating circuit is applicable to a multiple bit flash memory, it is characterized in that: comprise most reference current generation units, each reference current generation unit comprises:
One load has one first link and one second link, and this first link connects a working power;
A most reference memory unit, have a grid, one first source/drain electrode and one second source/drain electrode respectively, wherein this of above-mentioned each reference memory unit first source/drain electrode connects this second link jointly, this second source/grounded drain, and this grid then connects one jointly and raises word line voltage;
Wherein, this grid of each reference current generation unit be connected to identical one this raise word line voltage, and the width of the grid groove of this reference memory unit of each reference current generation unit, the then difference according to the size of the reference current of this majority required generation of reference current generation unit.
2. reference current generating circuit as claimed in claim 1, it is characterized in that: wherein the identical length of the grid groove of this reference memory unit of each reference current generation unit together, and the size of the length of the grid groove of this reference memory unit, the length of the grid groove of the flash memory cell of this multiple bit flash memory is of a size of greatly.
3. reference current generating circuit as claimed in claim 2 is characterized in that: wherein the length of the grid groove of this reference memory unit is of a size of 1 μ m.
4. reference current generating circuit as claimed in claim 1 is characterized in that: wherein this reference memory unit is connected in parallel together with most same reference storage unit that are arranged in same layout block, to produce this reference current.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB02142263XA CN100389470C (en) | 2002-08-28 | 2002-08-28 | Reference eurrent producing circuit of multiple allocation flash storage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB02142263XA CN100389470C (en) | 2002-08-28 | 2002-08-28 | Reference eurrent producing circuit of multiple allocation flash storage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1479319A CN1479319A (en) | 2004-03-03 |
| CN100389470C true CN100389470C (en) | 2008-05-21 |
Family
ID=34147992
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB02142263XA Expired - Lifetime CN100389470C (en) | 2002-08-28 | 2002-08-28 | Reference eurrent producing circuit of multiple allocation flash storage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100389470C (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5163021A (en) * | 1989-04-13 | 1992-11-10 | Sundisk Corporation | Multi-state EEprom read and write circuits and techniques |
| US5508958A (en) * | 1994-09-29 | 1996-04-16 | Intel Corporation | Method and apparatus for sensing the state of floating gate memory cells by applying a variable gate voltage |
| US5894436A (en) * | 1996-10-29 | 1999-04-13 | Nec Corporation | Nonvolatile semiconductor memory having memory cells each storing multi-bits information |
| US6038169A (en) * | 1999-03-18 | 2000-03-14 | Halo Lsi Design & Device Technology, Inc. | Read reference scheme for flash memory |
| US6434049B1 (en) * | 2000-12-29 | 2002-08-13 | Intel Corporation | Sample and hold voltage reference source |
-
2002
- 2002-08-28 CN CNB02142263XA patent/CN100389470C/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5163021A (en) * | 1989-04-13 | 1992-11-10 | Sundisk Corporation | Multi-state EEprom read and write circuits and techniques |
| US5508958A (en) * | 1994-09-29 | 1996-04-16 | Intel Corporation | Method and apparatus for sensing the state of floating gate memory cells by applying a variable gate voltage |
| US5894436A (en) * | 1996-10-29 | 1999-04-13 | Nec Corporation | Nonvolatile semiconductor memory having memory cells each storing multi-bits information |
| US6038169A (en) * | 1999-03-18 | 2000-03-14 | Halo Lsi Design & Device Technology, Inc. | Read reference scheme for flash memory |
| US6434049B1 (en) * | 2000-12-29 | 2002-08-13 | Intel Corporation | Sample and hold voltage reference source |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1479319A (en) | 2004-03-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6288944B1 (en) | NAND type nonvolatile memory with improved erase-verify operations | |
| CN108091365B (en) | Nonvolatile memory device | |
| CN102157203B (en) | Memory circuitry and operational approach thereof | |
| KR100935889B1 (en) | Method for storing E-Fuse data in flash memory device | |
| US20140119127A1 (en) | Dielectric charge trapping memory cells with redundancy | |
| CN101504864B (en) | Multi-level unit programming methods and integrated circuit apparatus | |
| US9177649B2 (en) | Flash memory circuit | |
| CN101345085A (en) | Flash memroy device and erase method thereof | |
| CN104520933B (en) | Method, equipment and the manufactured goods of the adaptive algorithm of fast flash memory bank | |
| CN105304669A (en) | Non-volatile resistance-variable storage circuit and control method thereof | |
| CN105229745A (en) | Share in memory and support circuit | |
| CN114613775B (en) | Nonvolatile memory and layout structure thereof | |
| WO2017074576A1 (en) | Smart verify for programming non-volatile memory | |
| US6185131B1 (en) | Nonvolatile semiconductor storage device capable of electrically isolating dummy cell array region from memory cell array region | |
| CN1937078B (en) | Multi-operation mode nonvolatile memory | |
| JP3474614B2 (en) | Nonvolatile semiconductor memory device and method of operating the same | |
| CN100389470C (en) | Reference eurrent producing circuit of multiple allocation flash storage | |
| CN100449646C (en) | Method and apparatus for programming nonvolatile memory | |
| CN100444285C (en) | Reference current producing circuit of multiple allocation flash storage | |
| CN100438037C (en) | Multistage NROM memory unit and its operation method | |
| KR100222811B1 (en) | Nonvolatile semiconductor device | |
| US6266280B1 (en) | Method of programming nonvolatile semiconductor device at low power | |
| KR100335779B1 (en) | Method of erasing flash memory device | |
| CN100342454C (en) | Reference current producing circuit of multiple allocation flash storage | |
| JPH11176179A (en) | Non-volatile semiconductor storage |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20080521 |
|
| CX01 | Expiry of patent term |