CN100395745C - Control system of peripheral unit - Google Patents
Control system of peripheral unit Download PDFInfo
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- CN100395745C CN100395745C CNB2004100433485A CN200410043348A CN100395745C CN 100395745 C CN100395745 C CN 100395745C CN B2004100433485 A CNB2004100433485 A CN B2004100433485A CN 200410043348 A CN200410043348 A CN 200410043348A CN 100395745 C CN100395745 C CN 100395745C
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- bus
- peripheral unit
- processor
- bridge
- control system
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Abstract
The present invention relates to a control system of a peripheral device, which comprises a processor, a first bus and a bridge device, wherein the processor comprises a set of control instructions. The first bus is connected with the processor device by a first bus protocol. The bridge device is communicated with the first bus through the first bus protocol, and is communicated with the peripheral device through a second bus protocol, wherein the processor transmits the set of control instructions to the peripheral device through the first bus and the bridge device, and the processor directly controls the peripheral device to perform the preset function.
Description
Technical field
The present invention relates to calculator system and peripheral unit control system, in order to control a peripheral unit.
Background technology
Along with the continuous expansion of computer system functions, various with the computer peripheral device also diversification all the more of mode of modularization and expansion in addition.In the known technology, computer system have more central processing unit (Central Processing Unit, CPU), to plan as a whole each assembly and the peripheral device in the control computer system.Central processing unit is many to link to each other with bus, and with a predetermined frequency, is commonly called as the outer frequency into central processing unit usually, transfers data to bus or carries out the communication of signal with bus.The data processing speed of the data processing speed of each peripheral unit and central processing unit and bus usually has nothing in common with each other, have sizable gap to each other, therefore, slow peripheral unit generally then passes through chipset, such as north and south bridge chip group, be connected with bus.And central processing unit is not generally directly controlled the thin portion or the independent function of peripheral unit.In this case, desire to make the peripheral unit can normal operation, the peripheral device of known technology has such as 8032 mostly, the microcontroller of the class of Z80.When central processing unit transmitted an instruction (instruction) to peripheral unit, this instruction was received by the microcontroller on the peripheral unit, and microcontroller and then each functional module of peripheral unit controlled is to realize the requirement of this instruction.
Because the peripheral unit in the known technology can not directly be controlled by central processing unit, and must comprise microcontroller, so that each function of control peripheral unit also makes the normal operation of peripheral unit energy, in this case, each peripheral unit still need be considered the installation of microcontroller when carrying out modular design, this can cause the increase of manufacturing cost.
Summary of the invention
The invention provides a kind of peripheral unit control system, an available processor cooperates a bridge-set directly to control a peripheral unit, and need not must could control each function of peripheral unit and make its normal operation by the microcontroller of peripheral unit inside as known technology.
Peripheral unit control system of the present invention mainly comprises: processor, first bus, bridge-set.Processor comprises one group of steering order, and this group steering order is to use when transmitting on first bus and meets first bus protocol, so that can be sent to bridge-set.And bridge-set links up with processor with first bus protocol on first bus, and links up with second bus protocol on second bus and this peripheral unit.Wherein, the steering order that processor sent is passed through first bus to bridge-set, bridge-set is then further changed this group steering order and is passed through second bus to this peripheral unit, thus, needn't must pass through microcontroller as known technology, carry out a specific function just processor of the present invention can directly be controlled peripheral unit.
Compared to known computer systems, this peripheral unit control system can directly be controlled peripheral unit, so that the processor in the control system can directly be controlled each functional module of this peripheral unit, and must could not realize above-mentioned purpose at the inner microcontroller of installing in addition of this peripheral unit, therefore can reduce the manufacturing cost of peripheral unit.
Description of drawings
Fig. 1 is the functional block diagram of peripheral unit control system of the present invention.
Fig. 2 is the functional block diagram of Fig. 1 bridge-set.
Fig. 3 is the sequential chart of peripheral unit control system of the present invention.
Fig. 4 is the functional block diagram of Fig. 1 peripheral unit and bridge-set.
Fig. 5 is the functional block diagram of another embodiment of peripheral unit control system of the present invention.
The reference numeral explanation
10,60: microcontroller apparatus control system 12,62: processor
18: peripheral unit 30: the data acquisition module
32: bus protocol modular converter 40: the address date shared pins
42: 44: the first registers of data pin
46: the second registers control in 48: the first pin
52: the first pins of 50: the second control pins
Pin 64 in 54: the second: the interface bus unit
66: internal bus 68: sub-processor
Embodiment
See also Fig. 1, Fig. 1 is the functional block diagram of peripheral unit control system one embodiment of the present invention.Peripheral unit control system 10 comprises processor 12, the first buses 14, and bridge-set 16.First bus 14 can be an advanced microcontroller bus architecture bus (AdvancedMicro-controller Bus Architecture Bus in the present embodiment, be abbreviated as the AMBA bus), the AMBA bus is connected between processor 12 and the bridge-set 16, with first bus protocol (or claiming the AMBA bus protocol) and bridge-set 16 transmission data or instructions.Bridge-set 16 further links via second bus 20 and peripheral unit 18, and the transmission data.The content of these data can comprise one and write instruction or reading command, makes processor 12 be able to directly control peripheral unit 18 of this instruction of mat.
See also Fig. 2, Fig. 2 is the functional block diagram of Fig. 1 bridge-set 16.Bridge-set 16 has data acquisition module 30 and bus protocol modular converter 32.Data acquisition module 30 is connected with first bus 14, judge according to the address message that is transmitted in the data on first bus 14, and acquisition is relevant and suitable information.And bus protocol modular converter 32 is converted to one second bus protocol in order to the data that data acquisition module 30 is captured by first bus protocol, makes these data or instruction be sent to peripheral unit 18 in the mode that meets second bus protocol via second bus 20.
In the present embodiment, processor 12 can be industry normal use RISC processor as ARM, MIPS etc. (Reduced Instruction Set Computer Processor, RISCProcessor).This processor 12 comprises between an addressed area, and processor 12 is exactly to control the operation of peripheral unit 18 to send address message in dropping between this addressed area.When control system 10 desires require peripheral unit 18 to carry out a specific periphery operation or function, processor 12 produces one group of steering order, this group steering order comprises the address message in dropping between this addressed area, and this group steering order also transmits via first bus 14.Because bridge-set 16 also is connected on first bus 14, after the address message that is comprised in the steering order on data acquisition module 30 interpretations first bus 14 wherein was relevant with it, the content that just will organize steering order captured to bus protocol modular converter 32.The content that to instruct of bus protocol modular converter 32 temporarily stores afterwards, and then this group instruction after changing and will change with second bus protocol is sent to peripheral unit 18, and making processor 12 be able to mat should direct this peripheral unit 18 of controlling of group instruction.
See also Fig. 3, Fig. 3 is the sequential chart of peripheral unit control system one embodiment of the present invention.In conjunction with a specific embodiment, illustrate how the present invention utilizes message that bridge-set 16 transmits first bus 14 to be converted to the message of second bus 20, with next sequential chart with Fig. 3 to control this peripheral unit 18.In the present embodiment, when processor 12 was desired to write data to peripheral unit 18, processor 12 can produce one group of steering order so that subsequent control peripheral unit 18.This group steering order comprises an address message, and one writes message, a data message, and a data validation message.Comprehensive, processor 12 at first can be sent to bridge-set 16 with the steering order that meets the AMBA bus protocol by first bus (AMBA bus) 14, bridge-set 16 can carry out necessary signaling protocol conversion after receiving steering order, so that further steering order is sent to peripheral unit 18.
Detailed description can be as shown in Figure 3, processor 12 at first transmits an address message and via first bus 14 and writes message to bridge-set 16, transmit a data message subsequently, and when the transmission of data message finishes, transmit a data validation message to bridge-set 16.The message of this part transmits, can be with reference to shown in Fig. 3 first half.After first bus 14 is finished aforesaid message transmission, then recover idle state, this moment, processor 12 just can utilize first bus 14 and other device to link up, so that the usefulness of processor 12 is performed to maximum.The data acquisition module 30 of bridge-set 16 can be in addition interpretation of the message that is transmitted on first bus 14, with understand present message whether and the device of oneself being responsible for have relevantly, if having, then must further be captured and be handled.Therefore when address message present on data acquisition module 30 interpretations first bus 14 is pointed to peripheral unit 18, then whole group of steering order on first bus 14 captured to bus protocol modular converter 32, so that first bus protocol is converted to second bus protocol, and steering order is sent to this peripheral unit 18 with second bus protocol.The message of this part transmits, can be with reference to shown in Fig. 3 Lower Half.Bridge-set 16 is to transmit this group steering order to this peripheral unit 18 with time-sharing format.That is to say that the address message that bridge-set 16 at first will meet second bus protocol is sent to this peripheral unit 18, and the address latch message of arranging in pairs or groups, then bridge-set 16 is sent to this peripheral unit 18 with the data message, and arranges in pairs or groups and one write message.Thus, processor 12 just can successfully write to data peripheral unit 18, and not need must just can finish by the microcontroller of peripheral unit inside as known technology via first bus 14, bridge-set 16 and second bus 20.
Signal waveform on second bus also can be with reference to as shown in Figure 3.Control signal on second bus mainly by address message, data message, write message, read message and the address latch message is formed.The signal that is produced on second bus normally belongs to specific waveform, for example: the mode of asynchronous control signal, carry out data transfer or signal generation with this, and remove to control peripheral unit 18, its work clock has only several MHz to 30MHz usually.
In the present embodiment, peripheral unit 18 is the peripheral unit of the peripheral unit of MsC-51 series, particularly MSC-518032.Peripheral unit 18 can also can write peripheral unit outside CD-ROM drive (Recordable Optical Disc Drive) or a USB converter (USBTransceiver), GPIO controller or any IC of being independent of or the like for a CD-ROM drive (Optical Disc Drive), in addition.The intercommunity of this peripheral unit is that they are the passive acceptance control from outside other order usually, and sending these mandators can be the computer system that is connected with peripheral unit, or the central processor CPU in the computer system.And, as long as can accepting outside microcontroller, peripheral unit 18 controls, for example: the external microcontroller that can accept one 51 series (MSC 51 family) is controlled, peripheral unit 18 inside can not comprise microcontroller, or comprising microcontroller does not still need to utilize microcontroller to carry out peripheral unit control operation related to the present invention.
That is to say that the peripheral unit of the MSC-51 8032 that gives an example at present embodiment can not include controller usually, but the steering order that the computer system that can accept to be connected is sent is controlled.A steering order can correspond to a string continuous specific waveforms, and bridge-set 16 proposed by the invention is exactly to be used for doing the transfer process that this steering order corresponds to specific waveforms, to replace the role of microcontroller in the prior art.If there is not bridge-set 16 of the present invention, then must remove to produce this waveform by front-end computer system high speed main control processor 12, thus, just represent that also processor 12 must reserve part system resource and carry out this work, this can influence the efficient of overall peripheral apparatus control system 10.The peripheral unit of the MSC-51 series of giving an example at present embodiment, if when wherein having microcontroller, usually also be belong at a slow speed (＜30MHz) and the microcontroller of figure place few (8 or 16), but must be able to accept the instruction of the high speed processor 12 of front end master control.
In the present invention, processor 12 can directly be sent to instruction peripheral unit 18 via first bus 14 and bridge-set 16, specific function with control peripheral unit 18, for example: processor 12 directly move instruction orders the read head (pickup head) of CD-ROM drive to move to ad-hoc location respectively, the rotation of order rotating shaft motor, and order laser head reading of data.Because the present invention can directly control peripheral unit 18, so controlled peripheral unit 18 can include microcontroller, so long as can identification and the instruction of accepting microcontroller get final product, thus, can reduce the manufacturing cost of peripheral unit.
See also Fig. 4, Fig. 4 is the functional block diagram of Fig. 1 peripheral unit 18 and bridge-set 16.Peripheral unit 18 is connected with bridge-set 16 with the pin sharing mode.Bridge-set 16 has address date shared pins 40.Address date shared pins 40 is connected to data pin 42, one first register 44 and one second register 46 of peripheral unit 18 simultaneously.In addition, bridge-set 16 also has the first control pin 48, the second control pin 50, is connected to first register, 44, the second registers 46 respectively.Peripheral unit 18 also has one first pin, 52, one second pins 54, is connected with first register 44, second register 46 respectively.First pin 52 can be the high address pin of peripheral unit 18, and second pin 52 can be the lower address pins of peripheral unit 18.The address date shared pins 40 of bridge-set 16 transmits the data pin 42 of first signal, second signal and data signals to the first register 44, second register 46 and peripheral unit 18 respectively.44 temporary transient first signals that store of this first register, then temporary transient second signal that stores of this second register 46.Afterwards, the first control pin 48 of bridge-set 16 and the second control pin 50 transmit a controlling signal respectively to control first register 44, second register 46, first signal, second signal are sent to first pin 52 and second pin 54 of peripheral unit 18.Utilize first register 44, the first control pin 48 of bridge-set 16 just can make to timesharing the data pin 42 of peripheral unit 18 and the address date shared pins 40 that first pin 52 is shared bridge-set 16.Similarly, utilize second register 46, the second control pin 50 of bridge-set 16 just can make to timesharing the data pin 42 of peripheral unit 18 and the address date shared pins 40 that second pin 54 is shared bridge-set 16.
Fig. 5 is the functional block diagram of another embodiment of peripheral unit control system of the present invention.Under framework proposed by the invention,, still can be suitable for the present invention if processor itself is not to use the AMBA bus.Fig. 5 then shows the peripheral unit control system 60 of another embodiment of the present invention, and in this system 60, processor 62 comprises a sub-processor 68 and an internal bus (internal bus) 66.That is to say, processor 62 itself is not to use the AMBA bus, and when being to use exclusive internal bus 66 or one the 3rd bus, in this case, then can carry out the operation of bus conversion earlier by interface bus unit 64, convert processor 62 internal buss or the signal of the 3rd bus the signal specification of first bus (AMBA bus) 14 to earlier, the signal hop of all the other and bridge-set 16 and peripheral unit 18 does not repeat them here just with noted earlier identical then.Thus, even processor 62 signals own use its exclusive internal bus 66, equally can be suitable for the present invention.
Comprehensive, the feature of peripheral unit control system of the present invention and advantage, can put in order as follows:
1. the present invention utilizes processor to cooperate bridge-set directly to control peripheral unit, need not must could control each function of peripheral unit and make its normal operation by the microcontroller of peripheral unit inside as known technology.In the present invention, peripheral unit is controlled by second bus by bridge-set, under this situation, whether including or do not include microcontroller in the peripheral control device just all has no relations, as long as can be controlled by second bus, even the microcontroller of peripheral unit inside can be omitted, so the present invention can not influence the manufacturing cost of saving microcontroller under the normal operation of original system.
2. bridge-set proposed by the invention can be converted to the steering order that processor sent specific waveforms, with the various operations of subsequent control peripheral unit, therefore can replace the role of microcontroller in the prior art.And the bridge-set complexity more proposed by the invention of the internal circuit in the general microcontroller is many, can omit microcontroller and reaches the purpose that the present invention controls peripheral unit with bridge-set, and this is that the present invention can save the manufacturing cost part.
3. except cost consideration,, then must remove to produce the waveform of subsequent control peripheral unit by the processor in the peripheral unit control system if there is not bridge-set of the present invention.Thus, just represent that also processor must reserve part system resource and carry out this work, this can influence the efficient of overall peripheral apparatus control system.Bridge-set of the present invention has been arranged, can share the working load of processor in a large number for the control peripheral unit, make processor can central system in Limited resources, handle most crucial evaluation work.Thus, can promote the efficient of overall peripheral apparatus control system.
4. under framework proposed by the invention,, still can be suitable for the present invention if processor itself is not to use the AMBA bus.In this case, then can be earlier technology by the known bus conversion of industry, convert the internal bus signal of processor the signal specification of AMBA bus to earlier, just can adopt the present invention in the technology described in the most preferred embodiment afterwards.
By the above detailed description of preferred embodiments, be to wish to know more to describe feature of the present invention and spirit, and be not to come category of the present invention is limited with above-mentioned disclosed preferred embodiment.On the contrary, its objective is that hope can contain in the category that is arranged in claim of the present invention of various changes and tool equality.
Claims (14)
1. the control system of a peripheral unit, this control system comprises:
One processor can produce one group of steering order;
One first bus, this first bus is used one first bus protocol, to transmit this group steering order that this processor is produced; And
One bridge-set is linked up with this first bus protocol and this first bus, and links up with one second bus protocol and this peripheral unit;
Wherein, this processor transmits this group steering order to this peripheral unit by this first bus and this bridge-set, makes this processor directly control this peripheral unit and carries out an intended function.
2. control system as claimed in claim 1, this bridge-set comprises:
One data acquisition module optionally receives this group steering order from this first bus with this first bus protocol; And
One bus protocol modular converter is connected to this data acquisition module, and this group steering order that receives is sent to this peripheral unit with this second bus protocol.
3. control system as claimed in claim 1, this group steering order comprises: an address message, an address latch message, write message, a data message and a data validation message.
4. control system as claimed in claim 1, this peripheral unit does not comprise microcontroller.
5. control system as claimed in claim 1, this peripheral unit comprises a microcontroller.
6. control system as claimed in claim 5, this microcontroller of this peripheral unit is one 51 Series of MCU.
7. control system as claimed in claim 1, this processor are a RISC processor.
8. control system as claimed in claim 1, this first bus are an advanced microcontroller bus architecture bus.
9. control system as claimed in claim 1, this processor comprises:
One sub-processor; And
One the 3rd bus is connected to this sub-processor, and the 3rd bus is used one the 3rd bus protocol;
Wherein, the 3rd bus of this processor connects the 3rd bus to this first bus via an interface bus unit.
10. control system as claimed in claim 9, this group steering order by this sub-processor via the 3rd bus and use the 3rd bus protocol to be sent to this interface bus unit, this interface bus unit with this received group steering order via this first bus and use this first bus protocol to be sent to this bridge-set.
11. control system as claimed in claim 10, this first bus are an advanced microcontroller bus architecture bus, the 3rd bus is an internal bus, and this sub-processor is a RISC processor.
12. a computer system, this computer system comprises:
One peripheral unit;
One processor can produce one group of steering order;
One first bus, this first bus is used one first bus protocol, to transmit this group steering order that this processor is produced; And
One bridge-set is linked up with this first bus protocol and this first bus, and links up with one second bus protocol and this peripheral unit;
Wherein, this processor transmits this group steering order to this peripheral unit by this first bus and this bridge-set, makes this processor directly control this peripheral unit and carries out a predetermined function.
13. computer system as claimed in claim 12, one address date shared pins of this bridge-set is connected to a data pin of this peripheral unit, this address date shared pins is connected with one first register, this first register further is connected with one first pin of this peripheral unit, one first control pin of this bridge-set is connected to this first register, makes this address date shared pins of this data pin and shared this bridge-set of this first pin with timesharing ground.
14. computer system as claimed in claim 13, this address date shared pins of this bridge-set also is connected to one second register, this second register further is connected with one second pin of this peripheral unit, one second control pin of this bridge-set is connected to this second register, makes this address date shared pins of this data pin and shared this bridge-set of this second pin with timesharing ground.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100433485A CN100395745C (en) | 2004-05-10 | 2004-05-10 | Control system of peripheral unit |
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| CNB2004100433485A CN100395745C (en) | 2004-05-10 | 2004-05-10 | Control system of peripheral unit |
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| CN1696919A CN1696919A (en) | 2005-11-16 |
| CN100395745C true CN100395745C (en) | 2008-06-18 |
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| CNB2004100433485A Expired - Fee Related CN100395745C (en) | 2004-05-10 | 2004-05-10 | Control system of peripheral unit |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US7797475B2 (en) * | 2007-01-26 | 2010-09-14 | International Business Machines Corporation | Flexibly configurable multi central processing unit (CPU) supported hypertransport switching |
| TWI547784B (en) * | 2011-04-22 | 2016-09-01 | 緯創資通股份有限公司 | Method of dynamically adjusting bus clock and device thereof |
| US9569375B2 (en) * | 2014-05-19 | 2017-02-14 | Microchip Technology Incorporated | Unifying class device interface with one host interface by using embedded controller |
| CN106155951B (en) * | 2015-03-30 | 2024-01-12 | 上海黄浦船用仪器有限公司 | Dual-bus arbitration control system and application thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02158856A (en) * | 1988-12-12 | 1990-06-19 | Matsushita Electric Ind Co Ltd | Peripheral controller and multiprocessor system |
| US5845107A (en) * | 1996-07-03 | 1998-12-01 | Intel Corporation | Signaling protocol conversion between a processor and a high-performance system bus |
| CA2282166A1 (en) * | 1998-09-11 | 2000-03-11 | Tundra Semiconductor Corporation | Method and apparatus for bridging a digital signal processor to a pci bus |
| JP2001005718A (en) * | 1999-06-24 | 2001-01-12 | Seiko Instruments Inc | Protocol handler and its signal processing method |
| JP2003323397A (en) * | 2002-05-07 | 2003-11-14 | Matsushita Electric Ind Co Ltd | Interface bridge device |
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2004
- 2004-05-10 CN CNB2004100433485A patent/CN100395745C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02158856A (en) * | 1988-12-12 | 1990-06-19 | Matsushita Electric Ind Co Ltd | Peripheral controller and multiprocessor system |
| US5845107A (en) * | 1996-07-03 | 1998-12-01 | Intel Corporation | Signaling protocol conversion between a processor and a high-performance system bus |
| CA2282166A1 (en) * | 1998-09-11 | 2000-03-11 | Tundra Semiconductor Corporation | Method and apparatus for bridging a digital signal processor to a pci bus |
| JP2001005718A (en) * | 1999-06-24 | 2001-01-12 | Seiko Instruments Inc | Protocol handler and its signal processing method |
| JP2003323397A (en) * | 2002-05-07 | 2003-11-14 | Matsushita Electric Ind Co Ltd | Interface bridge device |
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