CN100399472C - 用于使用快速突发模式以改善处理器性能的方法和装置 - Google Patents

用于使用快速突发模式以改善处理器性能的方法和装置 Download PDF

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CN100399472C
CN100399472C CNB02816928XA CN02816928A CN100399472C CN 100399472 C CN100399472 C CN 100399472C CN B02816928X A CNB02816928X A CN B02816928XA CN 02816928 A CN02816928 A CN 02816928A CN 100399472 C CN100399472 C CN 100399472C
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burst mode
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interrogation signal
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约恩·瑟伦森
保罗·D·克里瓦切克
迈克尔·艾伦
马克·邦斯
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Abstract

提供了用于以持续突发模式访问快速存储器的方法和装置。所述装置包含：处理器，其用于执行包含存储器访问指令的指令，该处理器生成表示下一个存储器访问是否是顺次接着当前存储器访问的下一个访问信号；存储器，其具有运行的持续突发模式；以及总线接口单元，其用于响应于存储器访问指令来控制对存储器的访问。在下一个访问信号被肯定时，总线接口单元启动存储器的持续突发模式。

Description

用于使用快速突发模式以改善处理器性能的方法和装置
相关申请的交叉引用
本申请要求于2001年8月29日申请的序列号为60/315,655的临时申请的权益，该申请合并在此全部作为参考之用。
技术领域
本发明涉及数字处理系统，更具体地说，涉及用于通过使用快速(flash)存储器的持续突发模式来改善处理器性能的方法和装置。
背景技术
诸如那些在无线应用中使用的嵌入式基带处理器可以在单个芯片上包括数字信号处理器、微控制器和存储器。在无线应用中，由于需要保持与无线系统的定时的同步，所以处理速度是关键。微控制器的处理速度很大程度上由相关联的存储器系统决定，特别由位于基带处理器外面的快速存储器系统决定。改善处理速度的一种途径是把代码从外部存储器中拷贝到内部的单片存储器(chip memory)上，其中，内部的单片存储器可以以处理器速度运行且拥有大于外部存储器的总线宽度。但是，代码库可能超过芯片上存储器(on-chip memory)的容量。此外，除了了代码存储之外，单片存储器中的至少一部分还被用于数据存储。
改善微控制器速度的一种选择是增加高速缓存存储器。但是，通过使用了高速缓存(cache)存储器，用于典型通信处理器的代码结构几乎没有得到改善。具体地说，代码可以被写入，以使得在每次传送(pass)的时候代码的大部分能够被使用。代码结构包含很多函数调用和条件代码。结果使得程序流典型地是不连续的，从而造成了低下的高速缓存性能。
突发模式(burst mode)快速存储器可以用来更快速地填充高速缓存存储器。突发模式快速存储器是这样一种存储器：其中访问脉冲串(burst)的第一字需要与传统快速存储器大约相同的时间(典型地是70-120nS)，而访问脉冲串的下面的字则快多了(典型地是20-25nS)。典型的突发模式快速存储器具有固定的脉冲串长度，例如4个字。举个示例，读取4个字的脉冲串可能需要70+20+20+20nS＝130nS的总访问时间，而把这4个字作为单个字而读取则需要4*70nS＝280nS。突发缓冲器可以用于在微控制器之前进行读取。这种方法所存在的问题是，由于程序结构的原因，微控制器可能只需要脉冲串中的少数指令。更具体地说，由于程序流的不连续性，可能不需要从快速存储器中读取的字。因此，突发缓冲器的使用不会在性能方面上带来很大的改善。
因此，需要有一种用于使用快速存储器的突发模式的经改善的方法和装置，以改善处理器性能。
发明内容
因此，根据本发明的第一方面，提供了数字处理装置。所述数字处理装置包含：处理器，其用于执行包含存储器访问指令的指令，该处理器生成表示下一个存储器访问是否是顺次接着当前存储器访问的下一个访问信号；存储器，其具有运行的持续突发模式，该存储器带有用于与处理器通信的存储器总线；以及总线接口单元，其用于响应于存储器访问指令来控制对存储器的访问。在下一个访问信号时被肯定(assert)，总线接口单元启动存储器的持续突发模式。
根据本发明的另一方面，提供了一种用于访问数字处理系统中的存储器的方法。该方法包含：提供用于执行包含存储器访问指令的指令的处理器，该处理器生成表示下一个存储器访问是否是顺次接着当前存储器访问的下一个访问信号；提供具有持续突发模式的存储器；以及在下一个访问信号被肯定时，启动存储器的持续突发模式。
附图说明
为了更好地理解本发明，针对附图给出了参考，其结合在此作为参考之用。在附图中：
图1是根据本发明的实施例的数字处理系统的框图；以及
图2是一个表，示出了一个示例以及提供通过本发明所获得的结果与通过现有技术方法所获得的结果之间的比较。
具体实施方式
根据本发明的一个方面，数字处理系统使用具有持续突发模式能力的这种类型的快速存储器。持续突发模式是这样一种模式：其允许突发访问持续进行而没有对脉冲串长度的限制，或者其允许突发访问拥有非常长的脉冲串长度。持续突发模式在长度上可以根据突发模式使能信号(enable signal)的状态而变化。此外，持续突发模式允许突发访问持续进行而没有对地址边界(address boundary)的限制。因此，例如，只要持续突发模式使能信号被肯定，快速存储器就可以在连续的存储器地址上供应数据字。
根据本发明的另一方面，数字处理系统使用生成“下一个访问(Next Access)”信号或类似信号的这种类型的处理器。下一个访问信号表示下一个存储器访问是否是顺次接着当前存储器访问。更具体地说，下一个访问信号表示下一个地址是否等于当前地址+1。提供也称为nSEQ信号的下一个访问信号的处理器的示例为由Advanced RiskMachines提供的ARM7TDMI微控制器。因此，当下一个访问信号被肯定时，下一个地址等于当前地址+1。当下一个访问信号没有被肯定时，下一个访问将到非当前地址+1的地址。
下一个访问信号可以由总线接口单元使用，以控制快速存储器的持续突发模式。因此，当下一个访问信号被肯定时，总线接口单元可以启动快速存储器的持续突发模式且以突发模式继续进行读取。当下一个访问信号被处理器否定(dessert)时，脉冲串读取被中断，从而提供了具有可变长度的脉冲串读取。这种方法利用了快速存储器的突发模式中的快速访问时间。进而，通过在否定下一个访问信号时中断突发模式，避免了对未使用字的读取。举个示例，持续脉冲串的第一字可以拥有70nS的访问时间，且该持续脉冲串中的所有后面的字可以拥有20nS的访问时间。通过访问持续脉冲串中的字和通过避免访问不被处理器使用的字的方式，获得了性能上的优势。
根据本发明的实施例的数字处理系统的框图如图1所示。微控制器10经由总线接口单元12连结至快速存储器14。微控制器10、总线接口单元12和快速存储器14通过地址总线、读取数据总线和控制总线进行互连。根据总线结构，写入数据可以由分离总线(未示出)承载(carried)。微控制器10提供下一个访问信号至总线接口单元12。如上所表示，当下一个存储器地址等于当前存储器地址+1时，下一个访问信号被肯定。当连续的存储器地址正被访问时，下一个访问信号是程序流的函数并且保持肯定状态。当存储器访问的是非连续的地址时以及当存储器没有正被访问时，下一个访问信号是否定的。当下一个访问信号被肯定时，总线接口单元12启动快速存储器14的持续突发模式。当启动持续突发模式时，快速存储器14供应来自连续的存储器地址的数据字，该存储器地址从在地址总线上供应的地址开始。当持续突发模式被否定时，当前脉冲串被中断且存储器的访问从新的地址开始。后面的访问可以是单个字访问或另一持续突发模式访问。
把本发明的实施例与现有技术进行比较的示例如图2所示。微控制器10中的指令缓冲器的大小设置为4个字，且执行6或12个连续的指令。在两种情况中，指令被扩散到装配在指令缓冲器中的3个块中。列20和22示出了不带有突发模式的正常快速存储器，其具有70nS的访问时间。列20示出了12指令序列的示例，其需要840nS的总访问时间，且列22示出了6指令序列的示例，其需要420nS的总访问时间。列24表示使用了在缓冲器中拥有4个字的突发缓冲器的12指令序列的情况。在这种情况中，接口单元总是读取整个块，其在这种情况中是4个字。在这种情况中，由于接口总是读取整个块，因此最差情况和最佳情况之间没有差别。列26和28示出了具有可变长度的持续脉冲串。列26表示在连续地址中的12个指令的指令序列，且列28表示在连续地址中的6指令的指令序列。使用持续突发模式，12指令序列需要了290nS的总访问时间，且6指令序列需要170nS的总访问时间。可从图2中看出，使用具有可变长度的持续突发模式，可以获得很大的改善。
上述的描述只是示出性的而非详尽的描述。该描述向本领域的普通技术人员提出了很多变化和替换的建议。所有这些变化和替换应当在所附权利要求的涵盖范围之内。本领域的普通技术人员可以认识到与在此所描述的具体实施例等效的其它等同物，其等同物也应当在所附权利要求的涵盖范围之内。进而，在下面独立权利要求中所呈现的特定特征能够以本发明的范围之内的其它方式互相组合，使得本发明应当被认为是明确涉及具有独立权利要求的特征的任何其它可能组合的其它实施例。

Claims (11)

1.数字处理装置，包含：
处理器，其用于执行指令，该指令包括存储器访问指令，所述处理器生成表示下一个存储器访问是否是顺次接着当前存储器访问的下一个访问信号；
存储器，其具有运行的持续突发模式，所述存储器带有用于与所述处理器通信的存储器总线；以及
总线接口单元，其用于响应于存储器访问指令来控制对所述存储器的访问，在下一个访问信号被肯定时，所述总线接口单元启动存储器的持续突发模式，所述下一个访问信号表明了对如下存储器地址的访问，所述存储器地址是紧接着当前访问的存储器地址的存储器地址。
2.如权利要求1所述的数字处理装置，其中所述处理器包含用于执行微控制器指令的微控制器。
3.如权利要求1所述的数字处理装置，其中，当下一个访问信号被否定时，所述总线接口单元禁止存储器的持续突发模式。
4.如权利要求1所述的数字处理装置，其中所述存储器包含快速存储器。
5.如权利要求1所述的数字处理装置，其中所述处理器、所述存储器和所述总线接口单元包含用于在无线终端中使用的基带处理器。
6.如权利要求1所述的数字处理装置，其中，在单个衬底上制造所述处理器、所述存储器和所述总线接口单元。
7.一种用于访问数字处理系统中的存储器的方法，包含：
提供执行包含存储器访问指令的指令的处理器，所述处理器生成表示下一个存储器访问是否是顺次接着当前存储器访问的下一个访问信号；
提供具有运行的持续突发模式的存储器；以及
在下一个访问信号被肯定时，启动存储器的持续突发模式，所述下一个访问信号表明了对如下存储器地址的访问，所述存储器地址是紧接着当前访问的存储器地址的存储器地址。
8.如权利要求7所述的方法，其中，提供处理器的步骤包含提供用于执行微控制器指令的微控制器。
9.如权利要求8所述的方法，其中，提供存储器的步骤包含提供快速存储器。
10.如权利要求7所述的方法，进一步包含：当下一个访问信号被否定时，禁止存储器的持续突发模式。
11.一种用于无线应用的基带处理器，包含：
微控制器，其用于执行包括存储器访问指令的微控制器指令，所述微控制器生成表示下一个存储器访问是否是顺次接着当前存储器访问的下一个访问信号；
快速存储器，其具有运行的持续突发模式，所述快速存储器带有用于与所述微控制器通信的存储器总线；以及
总线接口单元，其用于响应于存储器访问指令来控制对所述快速存储器的访问，在下一个访问信号被肯定时，所述总线接口单元启动快速存储器的持续突发模式，所述下一个访问信号表明了对如下存储器地址的访问，所述存储器地址是紧接着当前访问的存储器地址的存储器地址。
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