CN100405336C - Wiring architecture for transmission wires in high speed printed circuit board - Google Patents
Wiring architecture for transmission wires in high speed printed circuit board Download PDFInfo
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- CN100405336C CN100405336C CNB2004100918927A CN200410091892A CN100405336C CN 100405336 C CN100405336 C CN 100405336C CN B2004100918927 A CNB2004100918927 A CN B2004100918927A CN 200410091892 A CN200410091892 A CN 200410091892A CN 100405336 C CN100405336 C CN 100405336C
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- transmission line
- circuit board
- printed circuit
- speed printed
- wiring architecture
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Abstract
The present invention relates to a wiring framework for transmission lines in a high-speed printed circuit board, which is applied to the connection of a north bridge chip and PCI slots on a high-speed printed circuit board, wherein the north bridge chip is connected to a connection point through a main transmission line; the connection point is connected to the PCI slots through a plurality of branched transmission lines; the main transmission line and the branched transmission lines are respectively connected in series with a damping resistor; the north bridge chip and the PCI slots can mutually transmit signals through the main transmission line and the branched transmission lines. The present invention can effectively solve transmission line effect problems caused by the adoption of a traditional daisy chain wiring framework between the north bridge chip and the PCI slots on the high-speed printed circuit board, which improves the transmission quality of signals.
Description
[technical field]
The invention relates to the Wiring architecture of transmission line in a kind of high-speed printed circuit board, be meant a kind of transmission line Wiring architecture that is used for being used for improving between north bridge chips and PCI (Peripheral Component Interconnect, external unit expansion interface) slot on the high-speed printed circuit board signal transmitting quality especially.
[background technology]
Development of electronic technology makes that the operating rate of IC (integrated circuit) is more and more faster, frequency of operation is more and more higher, it has been generally acknowledged that if the frequency of DLC (digital logic circuit) reaches or surpass 45MHZ～50MHZ, and the circuit that is operated on this frequency accounted for the certain deal of whole electronic system (such as 1/3), and this circuit just is called high speed circuit.In fact, the harmonic frequency at signal edge is the unexpected result that fast-changing rising edge of signal and negative edge (or saltus step of title signal) have caused the signal transmission than the frequency height of signal itself.Therefore, if agreement line propagation delay is greater than the rise time of 1/2 digital signal drive end signal usually, think that then this type of signal is high speed signal and produces transmission line effect, be that line no longer is the simple lead that shows lumped parameter, but present the parameter effect of distribution, in the case, have only by using the high speed circuit design knowledge, the controllability of design process could be realized, otherwise high speed design that Here it is can't be worked based on the printed circuit board (PCB) of classic method design.
Development along with semiconductor technology, high speed design has become an important step in the modern electronic product design, compare with traditional design, high speed design will be considered problems of Signal Integrity more, and it mainly shows overshoot (overshoot), descends to dash (under shoot), ring (ringing), postpones (delay), crosstalks (crosstalk) and reflect aspects such as (reflection).General is to avoid or reduce transmission line effect by the topological structure of the strictness control track lengths and the cabling of making rational planning in the process of circuit design.
See also Fig. 1 and Fig. 2, north bridge chips 10 connects PCI slot 20,30,40 and 50 by a main transmission line 60, described north bridge chips 10, PCI slot 20,30,40,50 are connected with described main transmission line 60 via a terminal resistance R10, R20, R30, R40, R50 respectively, and the characteristic impedance that described terminal resistance R10, R20, R30, R40 and R50 resistance should be distinguished coupled branch's transmission line (figure is mark not) is complementary.Wherein, because drive signal is promptly to arrive each PCI slot 20,30,40 and 50 successively along this main transmission line 60 in these north bridge chips 10s from drive end, promptly from the signal of these north bridge chips 10s arrive each PCI slot the line length of process can be different, will there be the delay of certain hour and signal is every on the pcb board through the transmission line of a segment distance, so makes that the signal on each PCI slot is asynchronous; Simultaneously, owing to adopt the daisy chain Wiring architecture, interface between every branch's transmission line and the main transmission line can form a T type, make transmission line discontinuous, signal can come back reflective at this, even serial connection one terminal resistance also can not make the transmission coefficient of each branch all very good on each branch's transmission line.Therefore, we can see that ring, the overshoot phenomenon of signal curve 22,32,42,52 of described each PCI slot 20,30,40,50 is serious from Fig. 2, and each signal is asynchronous.
[summary of the invention]
Technical matters to be solved by this invention is to provide transmission line Wiring architecture in a kind of high-speed printed circuit board that can reduce on the motherboard ring of signal and overshoot phenomenon between north bridge chips and PCI slot.
Technical matters to be solved by this invention is achieved through the following technical solutions: described north bridge chips is connected to a tie point via a main transmission line, this tie point is connected to some PCI slots via some branches transmission line respectively again, respectively be connected in series a damping resistance on described main transmission line and the branch transmission line, can transmit signal mutually by described main transmission line and branch's transmission line between described north bridge chips and the described PCI slot, the difference in length value of wherein said some branches transmission line is not more than signaling rate and multiply by signal elevating time.
The advantage of technical scheme provided by the invention is: the present invention adopts described star topology framework and serial connection one damping resistance on described main transmission line and branch's transmission line, can make the signal transmissivity at described tie point place higher thus, signal can not come back reflective at described tie point place, effectively eliminate or reduced phenomenons such as ring and overshoot, improved signal transmitting quality.
[description of drawings]
The present invention is described in further detail to reach embodiment with reference to the accompanying drawings.
Fig. 1 is the synoptic diagram of Wiring architecture between existing north bridge chips and PCI slot.
Fig. 2 is the oscillogram on the PCI slot under the existing topological structure.
Fig. 3 is the synoptic diagram of the star-like Wiring architecture of the present invention.
Fig. 4 is the oscillogram on the PCI slot under the star topology framework of the present invention.
[embodiment]
See also Fig. 3, the present invention adopts the topological structure of symmetry, and in a printed circuit board (PCB), north bridge chips 1 is connected to a tie point A via a main transmission line 11, and this tie point A is connected to PCI slot 2,3,4,5 via branch's transmission line 21,31,41,51 respectively.End near described tie point A on described main transmission line 11, branch's transmission line 21,31,41,51 is connected in series a damping resistance R1, R2, R3, R4, R5, the resistance of described damping resistance R1, R2, R3, R4, R5 should be respectively be complementary with the characteristic impedance of described main transmission line 11, branch's transmission line 21,31,41,51, is 22 ohm in the resistance of the R1 of damping resistance described in the specific embodiment of the present invention, R2, R3, R4 and R5.In theory, best wire laying mode is that the length of described branch transmission line 21,31,41 and 51 will equate, but consider actual cabling requirement, want reserve part design enough and to spare, the described length of transmission line that waits of event allows a certain distance, but described gap is the smaller the better, and the difference in length L of described two branch's transmission lines calculates according to following formula:
L=signaling rate * signal elevating time
If via hole is few, device pin is few, then the transmission range of per nanosecond of signal is 5988mils (1mm=39.37mils) on the common pcb board, and the signal elevating time of high speed logic device is approximately 0.2ns.Therefore, in the specific embodiment of the present invention, be maximum wiring gap with 1198mils.Wherein said branch transmission line 21 and 51 is symmetrical distribution, and described branch transmission line 31 and 41 is symmetrical distribution.
In star topology framework of the present invention, the drive signal that described north bridge chips 1 sends is transmitted along described main transmission line 11, transmits signal through transmitting to described PCI slot 2,3,4 and 5 along described branch transmission line 21,31,41 and 51 respectively again behind the described tie point A.Signal from described PCI slot output also can be passed to described tie point A via described branch transmission line 21,31,41 and 51 respectively simultaneously, and then is passed to described north bridge chips 1 via described main transmission line 11.Since the signal of described north bridge chips 10 outputs is passed to that the line length of described PCI slot 2,3,4 and 5 processes equates or described line length difference each other in a scope that allows, make significantly not postpone between the signal on described PCI slot 2,3,4 and 5.Simultaneously because the present invention adopts the star topology framework, has only a tie point between each transmission line, as long as the described damping resistance R1 of serial connection, R2, R3, R4, R5 can improve signal transmitting quality to improve the signal transmissivity at described tie point place on described main transmission line 11 and branch's transmission line 21,31,41,51.
See also Fig. 4, can see therefrom with existing daisy chain Wiring architecture and comparing that ring, overshoot and signal asynchrony phenomenon have all had very big improvement, signal quality is better.
In above embodiment, in being connected of north bridge chips and PCI slot, adopted the star topology framework, but the present invention is not limited only to this, and the Wiring architecture of this printed circuit board (PCB) can also be applied to other single driver multiple collector or drive in the circuit structures that receive more more.
Claims (7)
1. the Wiring architecture of transmission line in the high-speed printed circuit board, be applied to being connected of north bridge chips and PCI slot on the high-speed printed circuit board, it is characterized in that: described north bridge chips is connected to a tie point via a main transmission line, this tie point is connected to some PCI slots via some branches transmission line respectively again, respectively be connected in series a damping resistance on described main transmission line and the branch transmission line, the transmission speed that the difference in length value of wherein said some branches transmission line is not more than signal multiply by signal elevating time.
2. the Wiring architecture of transmission line in the high-speed printed circuit board as claimed in claim 1 is characterized in that: described damping resistance is serially connected with an end of close described tie point on described main transmission line and the branch's transmission line.
3. the Wiring architecture of transmission line in the high-speed printed circuit board as claimed in claim 1 is characterized in that: the resistance of described damping resistance is complementary with the characteristic impedance of described transmission line respectively.
4. the Wiring architecture of transmission line in the high-speed printed circuit board as claimed in claim 3 is characterized in that: the resistance of described damping resistance is 22 ohm.
5. the Wiring architecture of transmission line in the high-speed printed circuit board as claimed in claim 1 is characterized in that: the equal in length of described branch transmission line.
6. the Wiring architecture of transmission line in the high-speed printed circuit board as claimed in claim 1 is characterized in that: described branch transmission line is symmetrical distribution.
7. the Wiring architecture of transmission line in the high-speed printed circuit board as claimed in claim 1 is characterized in that: the difference in length of described branch transmission line is less than 1198mils.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100918927A CN100405336C (en) | 2004-12-25 | 2004-12-25 | Wiring architecture for transmission wires in high speed printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100918927A CN100405336C (en) | 2004-12-25 | 2004-12-25 | Wiring architecture for transmission wires in high speed printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1797374A CN1797374A (en) | 2006-07-05 |
| CN100405336C true CN100405336C (en) | 2008-07-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2004100918927A Expired - Fee Related CN100405336C (en) | 2004-12-25 | 2004-12-25 | Wiring architecture for transmission wires in high speed printed circuit board |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100561487C (en) * | 2006-11-17 | 2009-11-18 | 鸿富锦精密工业（深圳）有限公司 | Printed circuit board (PCB) with multi-load topology cabling architecture |
| CN102573269A (en) * | 2010-12-09 | 2012-07-11 | 鸿富锦精密工业（深圳）有限公司 | Printed circuit board |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6237132B1 (en) * | 1998-08-18 | 2001-05-22 | International Business Machines Corporation | Toggle based application specific core methodology |
| CN2583879Y (en) * | 2002-11-02 | 2003-10-29 | 深圳市中兴通讯股份有限公司 | High speed rear panel |
| US6698003B2 (en) * | 2001-12-06 | 2004-02-24 | International Business Machines Corporation | Framework for multiple-engine based verification tools for integrated circuits |
| CN2609035Y (en) * | 2003-03-06 | 2004-03-31 | 浩鑫股份有限公司 | Integrated host computer panel structure |
-
2004
- 2004-12-25 CN CNB2004100918927A patent/CN100405336C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6237132B1 (en) * | 1998-08-18 | 2001-05-22 | International Business Machines Corporation | Toggle based application specific core methodology |
| US6698003B2 (en) * | 2001-12-06 | 2004-02-24 | International Business Machines Corporation | Framework for multiple-engine based verification tools for integrated circuits |
| CN2583879Y (en) * | 2002-11-02 | 2003-10-29 | 深圳市中兴通讯股份有限公司 | High speed rear panel |
| CN2609035Y (en) * | 2003-03-06 | 2004-03-31 | 浩鑫股份有限公司 | Integrated host computer panel structure |
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| CN1797374A (en) | 2006-07-05 |
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