CN100414685C - Manufacturing process of semiconductor device chip punch through isolation area and PN junction - Google Patents
Manufacturing process of semiconductor device chip punch through isolation area and PN junction Download PDFInfo
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- CN100414685C CN100414685C CNB200610068443XA CN200610068443A CN100414685C CN 100414685 C CN100414685 C CN 100414685C CN B200610068443X A CNB200610068443X A CN B200610068443XA CN 200610068443 A CN200610068443 A CN 200610068443A CN 100414685 C CN100414685 C CN 100414685C
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- isolation area
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Abstract
This invention provides a manufacture technology for passing through isolation regions and PN junctions of semiconductor chips, first of all, corroding the double sides of a chip symmetrically with etching and chemical corrosion to make grooves in the region for making PN junction passing through isolation and diffusion, then passing through the isolation region to finish impurity diffusion with the base synchronously to finish passing through the isolation region and forming base a PN junction, which reduces the diffusion temperature and time.
Description
Technical field
The present invention relates to the formation technology that break-through is isolated and P-N ties in the semiconductor device chip production, belong to the semiconductor device production field.
Background technology
In the semiconductor device chip manufacturing industry, the technology that generally all will use the break-through isolation realizes isolating and forms the P-N knot at present, and the technology that current break-through is isolated can be divided into three types:
1 conventional diffusion method:
The method also is conventional method of diffusion, be in semiconductor chip (with single, double be example to controllable silicon), in the zone of setting (break-through isolation diffusion district), pass through the different impurity source that mixes, again by diffuseing to form the realization break-through isolation and the PN junction of semiconductor device.Its chip structure comprises N type phosphorus district 2, punch through isolation area 4, N type growing base area 5, the light boron of P type district 3 and PN junction glassivation district 1 as shown in Figure 1.Characteristic feature has break-through isolation diffusion district and semiconductor device PN junction to form the district, and above two districts once form.Form the required diffusion temperature height of this structure: need more than 1270 ℃; The time of diffusion is long: needing more than 150--170 hour, in high temperature, long diffusion process like this, is inevitable to the defective that minority carrier life time and high temperature produced of device; Simultaneously to photoetching process and production equipment and technology requirement height; The qualification rate of product is on the low side, because the technological level difference of each producer, with 4 * 4Mmm
2Controlled silicon chip be example, qualification rate is generally between 60--83%, particularly along with this phenomenon of the increase of chip area is more outstanding.Qualification rate even can be lower than 40%, production cost also can significantly improve.
2 pairs of mesa etch deactivation methods
The method can not adopt diffusion method to carry out the break-through isolation, is to make the normal PN junction of device with two-sided corrosion and passivation method, and its chip structure comprises N type phosphorus district 2, the light boron of P type district 3, N type growing base area 5 and PN junction glassivation district 1 as shown in Figure 2.Its characteristic feature is no break-through isolation diffusion district, has glassivation district and semiconductor device PN junction to form the district.But because its scribe line is in glassivation district 1, so the N type district after the scribing is exposed to the outside, the damage and the UNICOM that cause PN junction easily when the encapsulation of back are so this type of chip encapsulation qualification rate at home is very low at present.So also just hindered applying of this technology.
3 laser drilling diffusion methods
The method is at first to punch on silicon chip with laser to carry out a kind of new process of diffusion of impurities again, and its chip structure schematic diagram such as Fig. 3 and Fig. 4 comprise laser hole 6, punch through isolation area 4, N type growing base area 5 and PN junction glassivation district 1.Its characteristic feature has laser drilling district and break-through isolation diffusion district, has the semiconductor device PN junction to form the district.Because the method will be punched by certain distribution to every, every row, every row one by one with laser, and to the degree of depth in hole, distance, straight through and punching after the clean of silicon chip the requirement of strictness is all arranged, so technology difficulty is big, the equipment investment height, production efficiency also is subjected to certain restriction, and corresponding production cost also can improve.
Summary of the invention
In order to overcome the deficiency of above-mentioned existing semiconductor device break-through isolation technology technology in manufacture process, the invention provides the manufacturing process of a kind of semiconductor device chip punch through isolation area and PN junction, make technical process and technology not increase equipment investment, not increase under the prerequisite of technology difficulty, can be towards low temperature, short time high production, high qualification rate, low cost and the direction that helps producing in enormous quantities develop.
The manufacturing process of semiconductor device chip punch through isolation area of the present invention and PN junction is:
On N type silicon chip, make semiconductor device chip, before the chip punch through isolation area diffusion, at first on silicon chip in the selected zone that will do the break-through isolation diffusion, the etching tank that erodes away with the method two sides symmetry of photoetching and chemical corrosion, punch through isolation area is finished diffusion of impurities synchronously with the base more then, and break-through is isolated and formation base PN junction to finish.The width of etching tank is that 10 μ m--5mm, the degree of depth are 2 μ m--230 μ m.The outward flange of etching tank is not less than 1.5mm to the outer peripheral distance of silicon chip.
The diffusion of punch through isolation area and base is once finished in the above-mentioned technology, and concrete technological process is:
------punch through isolation area and base prediffusion--punch through isolation area and base spread again--form punch through isolation area and base PN junction to etching tank in photoetching in oxidation.
1, oxidation: identical with the oxidation technology in the existing technology.
2, photoetching: the photoetching purpose is exactly clean for the oxide layer in the setting regions is removed.The width of etching tank is by the decision of the width of reticle bar, and the width of reticle bar is between 30 μ m--5000 μ m the time, and the width numerical value of etching tank is between 120 μ m--6000 μ m, and this will look the model of specific product and performance parameters and determine.Also require the outward flange of groove to be not less than 1.5mm simultaneously,, reduce the fragmentation odds to increase the mechanical strength of chip to the outer peripheral distance of silicon chip.
3, etching tank technology:
The component volume proportion of corrosive liquid is a nitric acid: glacial acetic acid: hydrofluoric acid=10: 3: 3
Etching time: 1 minute--20 minutes, decide on the temperature of corrosive liquid.
Corrosion depth: 2 μ m--230 μ m, decide on the thickness of chip.
Operating process is identical with the groove corrosion of normal mesa technique in the existing technology with method of operation.
Technology when 4, the diffusion of punch through isolation area and base is done diffuse source and once finished with gallium:
Gallium pre-expansion: furnace temperature: 1100 ℃--1250 ℃, the time: 30 minutes--180 minutes, R
(square resistance): 30 Ω/--300 Ω/, N
2(nitrogen): 1.2L/min, H
2(hydrogen): 20ml/min;
Gallium expands again: furnace temperature: 1100 ℃--and 1250 ℃, the time: 3 hours--40 hours, junction depth: 10 μ m--130 μ m, R
: 180 Ω/-110 Ω/.
Choosing of diffusion time and junction depth should be decided on whether mending boron technology behind the expansion gallium.Gallium expands and can lack slightly during if any benefit boron technology, and the time that the first time, gallium expanded again adds that the time that benefit boron expands again equals the total time that gallium expands again.To expand technology identical for normal gallium in operating process, method of operation and the existing technology.
Technology when 5, the diffusion of punch through isolation area and base is done diffuse source and once finished with boron:
All remove oxide layer clean;
Boron pre-expansion: furnace temperature: 1080 ℃, the time: 120 minutes, R
: 4 Ω/-4.5 Ω/;
Boron expands again: furnace temperature: 1250 ℃, and the time: 55 hours--65 hours, junction depth: 50 μ m--60 μ m.
When doing diffuse source, guaranteeing under the prerequisite that break-through puts in place, can adjust break-through diffusion and the collocation of light boron diffusion time, to reach the purpose of adjusting light boron junction depth with boron.Can independently adjust the junction depth of base.
The diffusion again of punch through isolation area is divided into secondary does, base junction depth just can independently be adjusted.
Because the advantage of technology of the present invention is that the junction depth of actual needs diffusion is shallow more a lot of than the junction depth of existing normal process diffusion, thick with sheet is that 225 μ m are example, promptly reduce to and have only 55 μ m now from 125 original μ m, so diffusion time is when using boron as impurity source equally, temperature is just from original 1270 ℃--and 1275 ℃ are reduced to 1250 ℃, and the time is also from original 150 hours--being reduced to 60 hours in 160 hours--65 hours.If adopt gallium is diffuse source, and under 1250 ℃, the time can be reduced to 25 hours equally--27 hours.
Technology of the present invention has reduced diffusion temperature and has reduced diffusion time, so the influence of product being made owing to the various defectives that produced in high temperature, the long-time process reduces greatly, especially because the formation in once spreading simultaneously of reach through region of this technology and base, so not only can be simple so that technical process becomes, and in existing normal process, product percent of pass reduced the influence of various defectives that photoetching caused, so can improve a lot to the manufacture process of product.With 4 * 4 (mm)
2Chip be example, monolithic test passes rate can reach as high as 95% more than 90%, and is metastable.
Description of drawings
Fig. 1 is the chip structure schematic diagram of conventional diffusion method.
Fig. 2 is the chip structure schematic diagram of two mesa etch deactivation methods.
Fig. 3 is the chip structure schematic diagram of laser drilling diffusion method.
Fig. 4 is along the cutaway view Amplified image of A-A line among Fig. 3.
Fig. 5 is the structural representation of mesa technique chip of the present invention.
Fig. 6 is the structural representation of planar technique chip of the present invention.
Fig. 7 is the silicon chip schematic diagram after the present invention is spread through dual surface lithography, etching tank, punch through isolation area and base.
Fig. 8 is the basic size schematic diagram of silicon chip.
Among the figure: 1, glassivation district, 2, N type phosphorus district, 3, the light boron of P type district, 4, punch through isolation area, 5, N type growing base area, 6, laser hole, 7, etching tank.
Embodiment
Embodiment 1
With N type silicon chip is example, and the structure of mesa technique chip as shown in Figure 5; The structure of planar technique chip as shown in Figure 6.Before the punch through isolation area diffusion, at first on silicon chip in the selected zone, with the method two sides symmetry of oxidation, photoetching and chemical corrosion erode away etching tank 7, the width of etching tank is that 180 μ m, the degree of depth are 70 μ m.Punch through isolation area 4 is finished diffusion of impurities synchronously with base 5 more then, to form punch through isolation area and PN junction.The outward flange of etching tank is not less than 1.5mm to the outer peripheral distance of silicon chip.Diffusion to logical isolated area 4 and base 5 is once finished, and its concrete technological process is: oxidation, and----------------punch through isolation area and base spread----and form punch through isolation area and base PN junction etching tank again for punch through isolation area and base prediffusion in photoetching.
1, oxidation: identical with the oxidation technology in the existing technology.
2, photoetching: during the width B of etching tank among Fig. 5=180 μ m, the wide 100 μ m that are designed to of reticle bar.Also require the outward flange of the pattern groove of ragged edge to be not less than 1.5mm simultaneously to the outer peripheral distance of silicon chip.To increase the mechanical strength of silicon chip, reduce the fragmentation odds.
3, the technology of etching tank:
The component proportioning (volume ratio) of corrosive liquid: nitric acid: glacial acetic acid: hydrofluoric acid=10: 3: 3;
Etching time: 12 minutes--20 minutes;
Corrosion depth: 70 μ m.
Operating process, method of operation are identical with the groove corrosion of normal mesa technique in the existing technology.
4, do diffuse source with gallium and once finish punch through isolation area and base diffusion, technology is:
Gallium pre-expansion: furnace temperature: 1200 ℃, the time: 120 minutes, N
2: 1.2L/min, H
2: 20ml/min, R
: 90 Ω/-110 Ω/.
Gallium expands again: furnace temperature: 1250 ℃, and the time: 20 hours--27 hours, R
: 180 Ω/-110 Ω/.
Junction depth: 50 μ m--60 μ m.
To expand technology identical for normal gallium in operating process, method of operation and the existing technology.
Through silicon chip schematic diagram such as the Fig. 7 after dual surface lithography, etching tank, punch through isolation area and the base diffusion; Basic size schematic diagram such as Fig. 8 of silicon chip.As can be seen, thick with sheet is that 225 μ m are example from Fig. 7, Fig. 8, and the diffusion length of existing normal break-through technology is: G=125 μ m, and adopted the actual dispersion distance after the technology of the present invention to be: C=55 μ m.
Difference from Example 1 is to do diffuse source with boron once to finish punch through isolation area and base diffusion, and its technology is:
Boron pre-expansion: furnace temperature: 1080 ℃, the time: 120 minutes, R
: 4 Ω/-4.5 Ω/.
Boron expands again: furnace temperature: 1250 ℃, and the time: 55 hours--65 hours, junction depth: 50 μ m--60 μ m.
When doing diffuse source, guaranteeing under the prerequisite that break-through puts in place, can adjust to the collocation of logical diffusion, to reach the purpose of adjusting light boron junction depth with the light boron diffusion time with the boron source.During as diffuse source, can independently adjust the junction depth of base with boron.
With boron during as diffuse source, before reach through region, base prediffusion, oxide layer all to be removed totally, then do not need to remove oxide layer during as diffuse source with gallium.
Claims (8)
1. the manufacturing process of semiconductor device chip punch through isolation area and PN junction, it is characterized in that: on N type silicon chip, make semiconductor device chip, before the chip punch through isolation area diffusion, at first on silicon chip in the selected zone that will do the break-through isolation diffusion, the etching tank that erodes away with the method two sides symmetry of photoetching and chemical corrosion, punch through isolation area is finished diffusion of impurities synchronously with the base more then, and break-through is isolated and formation base PN junction to finish.
2. the manufacturing process of semiconductor device chip punch through isolation area according to claim 1 and PN junction is characterized in that: the width of described etching tank is that 10 μ m--5mm, the degree of depth are 2 μ m--230 μ m.
3. the manufacturing process of semiconductor device chip punch through isolation area according to claim 1 and PN junction is characterized in that: the outward flange of described etching tank is not less than 1.5mm to the outer peripheral distance of silicon chip.
4. the manufacturing process of semiconductor device chip punch through isolation area according to claim 1 and PN junction, it is characterized in that: described punch through isolation area and base diffusion are once finished, and the flow process of described semiconductor device chip punch through isolation area and PN junction manufacturing process is: oxidation, and------punch through isolation area and base prediffusion--punch through isolation area and base spread again--form punch through isolation area and base PN junction to etching tank in photoetching.
5. the manufacturing process of semiconductor device chip punch through isolation area according to claim 1 and PN junction, it is characterized in that: the width of described etching tank is by the width decision of reticle bar, the width of reticle bar is between 30 μ m--5000 μ m the time, and the width numerical value of etching tank is between 120 μ m--6000 μ m.
6. the manufacturing process of semiconductor device chip punch through isolation area according to claim 4 and PN junction, it is characterized in that: the technology of described etching tank is: the component volume proportion of corrosive liquid is a nitric acid: glacial acetic acid: hydrofluoric acid=10: 3: 3, etching time are 1 minute--20 minutes.
7. the manufacturing process of semiconductor device chip punch through isolation area according to claim 4 and PN junction is characterized in that: described punch through isolation area and base diffusion are done diffuse source with gallium, once finish, and technology is:
Gallium pre-expansion: furnace temperature: 1100 ℃--1250 ℃, the time: 30 minutes--180 minutes, R
Mouthful: 30 Ω/mouth-300 Ω/mouths, N
2: 1.2L/min, H
2: 20ml/min;
Gallium expands again: furnace temperature: 1100 ℃--and 1250 ℃, the time: 3 hours--40 hours, junction depth: 10 μ m--130 μ m, R
Mouthful: 180 Ω/mouth-110 Ω/mouths.
8. the manufacturing process of semiconductor device chip punch through isolation area according to claim 4 and PN junction is characterized in that: described punch through isolation area and base diffusion are done diffuse source with boron, adopt one time diffusion method, and technology is:
Boron pre-expansion: furnace temperature: 800 ℃--1000 ℃, the time: 30 minutes--180 minutes, R
Mouthful: 10 Ω/mouth-300 Ω/mouths;
Boron expands again: furnace temperature: 1250 ℃, and the time: 10 hours--100 hours, junction depth: 10 μ m--30 μ m.
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| CN100414685C true CN100414685C (en) | 2008-08-27 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101901832A (en) * | 2010-06-28 | 2010-12-01 | 启东吉莱电子有限公司 | Controlled silicon punchthrough structure formed by gallium diffusion and production method thereof |
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| CN1913130A (en) | 2007-02-14 |
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