CN100416573C - 利用电源岛管理集成电路上的功率 - Google Patents

利用电源岛管理集成电路上的功率 Download PDF

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CN100416573C
CN100416573C CNB2004800195860A CN200480019586A CN100416573C CN 100416573 C CN100416573 C CN 100416573C CN B2004800195860 A CNB2004800195860 A CN B2004800195860A CN 200480019586 A CN200480019586 A CN 200480019586A CN 100416573 C CN100416573 C CN 100416573C
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CN1820270A (zh
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巴里·艾伦·赫贝曼
丹尼尔·L·希尔曼
乔恩·希尔
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    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02Regulating voltage or current
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01Details
    • H03K3/012Modifications of generator to improve response time or to decrease power consumption
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/324Power saving characterised by the action undertaken by lowering clock frequency
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/3296Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J4/00Circuit arrangements for mains or distribution networks not specified as ac or dc
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00Reducing energy consumption in communication networks
    • Y02D30/50Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

公开了一种利用电源岛管理集成电路上的功率的系统和方法。该集成电路包括多个电源岛,其中在电源岛的每一个中独立控制功率消耗。功率管理器确定电源岛之一的目标功率电平。功率管理器然后确定将电源岛之一的消耗功率电平改变到目标功率电平的动作;功率管理器将电源岛之一的消耗功率电平改变到目标功率电平的动作。

Description

利用电源岛管理集成电路上的功率
相关申请的交叉参考
本申请要求于2003年5月7日提交、名称为“用于管理集成电路中的功率的系统和方法”、序列号为60/468,742的美国临时申请的权益,其在此通过参考被引入。
技术领域
本申请通常涉及集成电路,并且更具体地涉及利用电源岛(powerisland)管理集成电路上的功率。
背景技术
对集成电路的一个设计目标是减小功率消耗。具有电池的装置,比如单元电话和膝上型电脑,特别需要集成电路中功率消耗方面的减小,以扩延长电池的电量。此外,功率消耗方面的减小避免了过热,并降低了集成电路的热耗散,在一些情况中,其消除或简化了集成电路的散热器和/或风扇。
利用构建成块的模块库单元设计一些集成电路。这些模块库单元是执行一定功能的电路块。模块库单元的一些例子是NAND门、多路复用器、解码器、比较器和存储器。
在“全定制”流程(flow)中,在最低电平处设计集成电路,比如在单独的晶体管、电容器和电阻器电平处。“全定制”流程可以利用内部开发的模块库单元。集成电路可以具有最佳性能,因为在最低电平处很详细地设计集成电路。然而,由于“全定制”流程的一些问题是与在这种详细的电平处的设计相联系的长时间和昂贵的成本。此外,“全定制”流程是麻烦的,因为设计在最低电平处。
在“标准单元”流程中,利用从第三团体或其它外部源获取的模块库单元设计集成电路。在逻辑或功能电平处标准化这些模块库单元。减小了用于标准单元流程的设计时间,因为已经预设计和预测试了模块库单元。
在用于设计集成电路的一个例子中,选择模块库单元,并且指定定制逻辑,以构建集成电路。然后,写入用于集成电路的寄存器转移电平(RTL),用于模拟和调试。在模拟和调试之后,对集成电路运行综合(synthesis)。执行性能测试软件,以确定集成电路的性能。然后基于集成电路的最佳性能运行集成电路的最后综合。
由于许多集成电路的一个问题是未有效利用功率消耗。例如,整个集成电路可以在刚好支持需要最大频率的应用的最大频率处工作,同时集成电路的其它部分可以在较低频率处工作。在另一例子中,集成电路中无源的电路消耗功率,并增大泄漏的可能性。无效的功率消耗也可以有害地影响集成电路的性能。
由于增大了集成电路的复杂性,当集成电路采用多个功能性时,功率消耗的减小甚至是更重要的。集成电路的一个例子是包括微处理器、存储器、I/O接口和全部在单个芯片中的模拟数字转换器的片上系统。由于在单个芯片中采用的多个不同类型的功能性,片上系统比单功能集成电路甚至消耗了更多的功率。
一些现有技术的集成电路已经采用电压岛或多个块,以降低功率消耗。由于这些集成电路的一个问题是电源岛中的电压和多个块的频率是静态的。电压和频率不是基于集成电路的需要和操作而动态改变。
发明内容
通过利用电源岛管理集成电路中的功率,本发明解决了上面的问题。集成电路包括多个电源岛,其中在电源岛的每一个中独立控制功率消耗。功率管理器为电源岛之一确定目标功率电平。功率管理器然后确定将电源岛之一的消耗功率电平改变到目标功率电平的动作;功率管理器执行将电源岛之一的消耗功率电平改变到目标功率电平的动作。功率控制电路控制电源岛之一的功率。
基于集成电路的地理因数或功能电路可以描绘电源岛。在一些实施例中,所述动作是为电源岛之一选择时钟频率或为电源岛之一选择时钟。在一些实施例中,所述动作是为电源岛之一修改电压。所述动作可以是通电或断电电源岛之一。
在一些实施例中,功率管理器监控电源岛之一的功率消耗电平,基于功率消耗电平确定阈值电平是否被跨越,并基于阈值电平的跨越而执行该动作。在一些实施例中,功率管理器存储和恢复电源岛之一中的部件的状态。
附图说明
图1是在本发明的示范性实施方式中用于管理集成电路中的功率的系统的方块图;
图2是在本发明的示范性实施方式中用于管理集成电路中的功率的系统的图示;
图3是在本发明的示范性实施方式中对用于低功率标准单元逻辑块的低泄漏电路的描述;
图4是本发明的示范性实施方式中电源岛的图示;
图5是本发明的示范性实施方式中从应用请求至从属功率管理器动作的流程图;
图6是在本发明的示范性实施方式中用于灵巧功率单元的内部电路的描述;
图7是在本发明的示范性实施方式中用于灵巧功率单元的外部电路的描述;
图8是本发明的示范性实施方式中从应用请求至灵巧功率单元(smart power unit)动作的流程图;
图9是在本发明的示范性实施方式中当通电时,在断电和恢复IP单元的状态之前用于存储IP单元的状态的流程图;
图10是本发明的示范性实施方式中片上系统和扩展的局部存储器的图示;
图11是在本发明的示范性实施方式中用于产生从中间功率管理器至功率管理控制层的“热点”报告的流程图;
图12是本发明的示范性实施方式中片上系统的图示;
图13是本发明的示范性实施方式中用于利用电源岛建立芯片的流程。
具体实施方式
如示范性附图中示出的,其中类似的参考数字表示附图中类似或相应的部件,下面详细描述依据本发明的系统和方法的示范性实施例。然而,可以理解,能够以各种形式具体化本发明。因此,于此公开的具体细节不被解释为限制,而是对权利要求的基础和用于教导本领域的普通技术人员以实际上任何合适详细的系统、结构、方法、过程或方式采用本发明的有代表性的基础。
图1描述了在本发明的示范性实施方式中用于管理集成电路110中的功率的系统100的方块图。所述系统100包括集成电路110和功率管理器120。集成电路110是被例示成硅和/或相关制造材料的任何电子装置。集成电路110的一个例子是片上系统。集成电路110包括多个IP单元,其是执行特定功能的电路块。
集成电路110包括四个电源岛112、114、116和118。为了简化,图1仅描述了四个电源岛112、114、116和118。集成电路110的其它实施例包括多个电源岛112、114、116和118。电源岛112、114、116和118耦合至总线125。
电源岛112、114、116和118是集成电路110的任何部分、描绘、隔开或分度,其中在所述部分、描绘、隔开或分度中控制功率消耗。在一些实施例中,基于集成电路110的地理因数描绘电源岛112、114、116和118。在一些实施例中,基于集成电路110的功能性IP单元描绘电源岛112、114、116和118。在图10中示出的一个例子中,通过存储器、微处理器和单独的IP块描绘电源岛。在一些实施例中,电源岛112、114、116和118是彼此异步或同步的。在一些实施例中,电源岛112、114、116和118包括子岛(sub-island),以在集成电路110中提供控制功率中的特性。在一些实施例中,每一电源岛112、114、116和118利用它自身的控制支持多时钟域(clock domain)。在一些实施例中,电源岛112、114、116和118中的时钟是可变的。
在一些实施例中,每一电源岛112、114、116和118包括功率控制电路。功率控制电路是为控制电源岛112、114、116和118的一个中的功率而设置的任何电路。功率控制电路的一些例子包括用于电平位移、信号隔离、Vdd多路复用、时钟多路复用和动态反馈偏压的电路。在一些实施例中,功率控制电路包括在用于集成电路110的标准元件设计的标准单元库中。
功率管理器120也耦合至总线125。总线125的一个例子是在下面图10中进一步详细所述的功率命令总线。系统100的其它实施例包括其中功率管理器120和电源岛112、114、116和118互连的多个变化。功率管理器120是任何电路、装置或系统,被配置用于(1)为电源岛112、114、116和118之一确定目标功率电平、其中在每一电源岛112、114、116和118中独立控制功率消耗,(2)确定将电源岛112、114、116和118之一的消耗功率电平改变到目标功率电平的动作,(3)执行将电源岛112、114、116和118之一的消耗功率电平改变到目标功率电平的动作。功率管理器120可以基于集成电路110的需要和操作而动态改变电源岛112、114、116和118的功率消耗。目标功率电平是电源岛112、114、116和118的期望、计算或指定的功率消耗。功率管理器120的一些例子是从属功率管理器(SPM)、中间功率管理器(IPM)和主功率管理器(MPM),其在下面做进一步的描述。功率管理器120可以是功率管理器120的体系或组。尽管图1说明了如位于集成电路110之外的功率管理器120,其它实施例可以具有位于集成电路110中的功率管理器120。在其它实施例中,功率管理器120可以分布于开启或关闭集成电路110或与CPU结合的多个功率控制器中。
所述动作是控制电源岛112、114、116和118中的功率消耗的任何指令、消息、过程、功能、信号或变量。所述动作的一些例子是时钟门控和动态时钟选择。所述动作的另一例子是修改电源岛112、114、116和118之一的时钟频率。所述动作的另一例子是修改电源岛112、114、116和118之一的电压,比如动态电压源、Vdd、选择。所述动作的另一例子是通过控制可变的Vt晶体管控制动态泄漏。
图2描述了在本发明的示范性实施例中用于管理集成电路250中的功率的系统200的图示。该系统200包括嵌入的固件栈210和集成电路250。嵌入的固件栈210包括在中央处理单元(CPU)上运行的软件层。在一些实施例中,嵌入的固件栈210可以包括应用层212、操作系统(OS)子系统216、功率管理控制层(PMCL)218、实时操作系统(RTOS)220、I/O驱动器222和用于MPM、IPM和/或SPM的功率管理器(PM)固件224。
集成电路250包括电源岛260、电源岛270和MPM280。电源岛260包括低功率标准单元逻辑块262和SPM 264。电源岛270包括低功率存储器块272和SPM 274。低功率标准单元逻辑块262和低功率存储器块耦合至接口265。MPM 280耦合至PMCL 218、SPM 264和SPM 274。
在一些实施例中,应用层212包括全局功率应用层(GPAL)214。该GPAL 214在更复杂的应用中有用。如果存在GPAL 214,然后到PMCL 218应用程序接口(API)的全部调用被首先导引至GPAL 214。GPAL 214和PMCL 218都为集成电路250提供管理。在一些实施例中,GPAL 214和/或PMCL 218监控什么负载在每一电源岛260和270上。此外,GPAL 214和PMCL 218可以建立电源岛260和270上功率电平的历史,并存储历史数据于数据库中。GPAL 214和PMCL 218也可以为对电源岛260和270的功率电平感兴趣的即时请求资源(on-demandresources)提供数据。
在一些实施例中,当存在GPAL 214,GPAL 214在进行用于集成电路250的功率管理的本地决定中提供向MCL218的导引。GPAL 214和PMCL 218包括用于静态调度表的复杂算法。GPAL 214和PMCL218提供用于使用代码的功能,以相互作用,并控制包括提供数据库和统计的功率行为和参数。
PMCL 218也收集来自MPM 280的信息,并提供命令至MPM 280,以用于可能的IPM、SPM 264和274以及电源岛260和270。一些命令可以是通电/断电、改变功率电平、或改变电源岛260和270的功率。在具有灵巧功率单元(SPU)290的一些实施例中,GPAL 214和/或PMCL 218负责与SPU 290通信,以执行功率政策和收集实际电源上的信息。下面在图6-8中将进一步详细描述SPU 290。在一些实施例中,GPAL 214和/或PMCL 218提供用于现有功率管理技术的插座。
功率管理器固件224是通过主功率管理器280、中间功率管理器和从属功率管理器264和274执行的固件。
MPM 280是为控制整个集成电路250的“共用”功率行为而设置的任何电路。在一些实施例中,存在控制整个集成电路250的功率行为的多个MPM280。在一些实施例中,MPM 280与现有的IPM和SPM
264和274通信,以控制电源岛260和270中的功率。MPM 280可以接收来自SPM 264和274和IPM的关于电源岛260和270的状态信息。MPM 280也可以确定IPM和SPM264和274之间的功率折中。
MPM 280也可以提供至PMCL 218固件的主接口。在一些实施例中,MPM 280与PMCL 218通信,以接受命令(例如存储器映射的命令),并提供关于集成电路250中功率的状态信息。在一些实施例中,MPM 280通过用于集成电路250的主总线与PMCL 218通信。MPM280也登记SPM 264和274和IPM的每一个以及PMCL 218的容量(capacity)。下面在图5、8、9和11中详细描述MPM 280的一些操作。在一些实施例中,MPM 280读和写扫描链,用于状态贮存并与本地逻辑分析器能力一起恢复。
一些实施例可以包括代表MPM 280来协调SPM 264和274的IPM(未示出)。在一些实施例中,IPM控制和协调由MPM 280控制的区域的一部分上的功率行为。在一些实施例中,IPM控制与MPM 280的分开的芯片上的SPM264和274。
SPM 264是为控制集成电路250中电源岛264中的功率而设置的任何电路。SPM 264的一个例子是控制集成电路250中电源岛264中的功率的IP块。SPM 264可以包括信号缓冲、电平位移和信号隔离。在一些实施例中,SPM 264集成在扫描链中,以提供更容易的实现和集成。此外,在一些实施例中,SPM 264具有非常小的“脚印(footprint)”,所述脚印具有低门计数和低功率。在一些实施例中,SPM 264包括命令接口,以通知状态信息、服务请求和命令。一些命令是负载、休眠和空载。SPM 264也可以识别它自身的地址,以允许多压降高压线与汇流排的连接(bussing)。
在一些实施例中,SPM 264具有登记能力。为了在加电时登记,SPM 264利用典型用于断开芯片SPM和IPM的收回登记(callbackregistration)。为了静态登记,当为片上SPM产生形成电路时,SPM 264登记SPM264可以做什么,以及SPM 264或IPM可以服务的命令的类型。SPM 264也可以具有用于断电周期的储存和恢复功能。该SPM
264可以具有看门狗定时器。在一些实施例中,该SPM 264具有与电源岛260协调的调试接口。该SPM 264也可以为电源岛260中的部件监控本地状态并收集信息。该SPM 264也可以本地控制Vdd、用于频率选择的时钟以及动态反偏置。用于SPM 264的描述也应用于电源岛270的SPM 274。
在一些实施例中,该SPM 264检查当从电源岛260收集的信息跨过阈值或超出范围时是否出现事件。在一些实施例中,SPM 264、IPM或MPM 280监控电源岛260的功率消耗电平,以检查功率消耗电平是否跨过阈值电平或超出范围。功率消耗电平是表示在电源岛260中消耗的功率的任何信息、数据或统计。功率消耗电平的一些例子是温度和功率。阈值或范围可以是可编程的。SPM 264可以异步报告事件,或者比如MPM 280的另一部件可以请求事件是否已出现。事件也可以是多电平测试,比如在大于给出的可编程频率或超出给出的可编程持续时间处出现的情况。
在一些实施例中,低功率标准单元逻辑块262是可以包括在电源岛260的标准单元库的一个例子。在一些实施例中,为了较低的功率最优化标准单元库。可以基于操作电压的范围特征化标准单元库。在一些实施例中,标准单元库包括同步电路和/或异步电路。在一些实施例中,标准单元库包括静态电路和/或封装、动态逻辑电路。标准单元库也可以包括多电压域接口电路,比如电平移位器和信号隔离电路。标准单元库也可以具有多阈值设计和特征,比如标准Vt、高Vt、低Vt和可变的Vt电路。标准单元库也可以包括数据保持(阴影)电路和抗低频干扰电路。标准单元库也可以包括低泄漏“休眠”电路。图3描述了在本发明的示范性实施方式中用于低功率标准单元逻辑块262的低泄漏电路300的说明。
图4说明了本发明的示范性实施方式中电源岛270的图示。电源岛270包括低功率存储器块272和SPM 274。低功率存储器块272包括用于存储器和休眠、断电电路450的联组体系结构410、420、430和440。在一些实施例中,电源岛270中的存储器是RAM和/或ROM。RAM的一些例子是SRAM编译器,比如单端口、2端口和双端口。ROM的一些例子是ROM编译器。为了低功率目的,电源岛270中的一些存储器被最优化,例如低功率存储器块272。在一个实施例中,低功率存储器块272包括通过编译器的多联组体系结构,比如联组工作的体系结构410、420、430和440。电源岛270中的存储器也可以包括用于低功率模式的休眠、断电电路450,比如休眠、小睡和完全断电。电源岛270中的存储器也可以包括可编程的读/写端口。电源岛270中的存储器也可以是异步和/或同步设计。
在一些实施例中,所述系统200也包括灵巧功率单元(SPU)290。在一些实施例中,SPU 290是与集成电路250分开芯的片。该SPU 290是为控制集成电路的功率和时钟分布而设置的外部单元。下面在图7和8中进一步详细描述SPU的电路。
图5说明了本发明的示范性实施方式中从应用请求至SPM动作的流程。图5开始于步骤500。在步骤502中,调用应用,比如放电影。在步骤504中,该应用为IP单元的性能确定需要的频率。例如,该应用为用于MPEG解码器的IP单元确定以MHz指定的频率。在一些实施例中,当IP单元是完全异步时,需要的频率将是对性能的人工测定。在具有包括的多时钟的一些实施例中,指定用于每一时钟的最小性能。
在步骤506中,该应用请求PMCL 218API调用。该调用的一个例子是“Ser_Rate(单元Y、N MHz、允许的动态能量管理(DMP)的程度、DMP阈值、允许DMP折中的其它信息、利用动态偏置起动用于SPM的反偏置、等待加电标记)”。在该例子中,其它信息可以是“电源不断开,利用高Vt并关闭时钟作为替换”和“主要等待是大约10us, 400ns阈值”。在具有多时钟的一些实施例中,PMCL 218API调用允许应用指定全部需要的频率。
PMCL 218确定可用于单元的可能的折中,并选择频率、Vdd和Vt,如果适用于最佳满足步骤508中给出需要的单元,并确定步骤510中适用的SPM 264和274。在一些实施例中,MPM 280或IPM执行步骤508和510。在用于多时钟的一些实施例中,指定的Vdd和Vt将允许为满足或超出它们的需要频率的全部指定时钟。
在步骤512中,PMCL 218然后将SPM264和274期望的设置写到MPM 280(或IPM)中。在步骤514,MPM 280(或IPM)将请求转换成用于与单元相联系的SPM 264和274(或IPM)的一个或多个命令。
在步骤516中,如果应用设置等待加电标记,PMCL 218然后等待,直至在从调用返回之前IP单元被完全加电。另外,利用用于认可的0状态、用于快速加电的1、用于缓慢加电的2或用于错误条件的3+,一确认命令,调用就返回。该通电状态是何时该单元处于请求频率的期望Vdd处,并且该单元不是刚好开启。
在步骤518中,MPM 280(或IPM)发送请求至合适的目标。在步骤520中,MPM 280等待接收到确认,其表示接收和执行的信息或者已经开始执行。也可以从SPM 264和274返回NACK或否定确定。
在步骤522中,SPM 264接收命令,并执行动作。步骤524-528是SPM 264可以执行的可能动作。在步骤524中,SPM 264开关Vdd多路复用器。在步骤526中,SPM 264开关时钟多路复用器。在一些实施例中,当电压下降,在步骤524之前执行步骤526,在步骤528中,SPM 26改变相联系的晶体管的Vt。在SPM 264执行该动作之后,SPM 264向上游返回表示步骤530中确认或否定确认的状态信息。图5结束于步骤532。
图6说明了本发明的示范性实施例中用于SPU 290的内部电路600的描述。在该实施例中,用于SPU 290的内部电路600对于图2的集成电路250而言是内在的。该内部电路600包括外部电压610、降压调节器620、降压调节器630、逻辑块640和逻辑块650。
图7说明了本发明的示范性实施例中用于SPU 290的外部电路700的描述。在该实施例中,用于SPU 290的外部电路700对于图2的集成电路250而言是外在的。外部电路700包括外部电压710、电源插针720、电源插针730、电源插针740、逻辑块750、逻辑块760、逻辑块770。用于SPU 290的外部电路700提供DC/DC转换。该DC/DC转换提供多路独立的电源插针720、730和740。电源插针720、730和740在每一单独的电源插针上具有可变的电压供给。此外,在一些实施例中,可变电压在范围中,并在步骤中。在一些实施例中,PMCL
218控制至电源插针720、730和740的电压。
图8说明了在本发明的示范性实施方式中从应用请求至SPU动作的流程。图8开始于步骤800。在步骤802中,调用应用。在步骤804中,该应用为IP单元的性能确定需要的频率。例如,该应用为用于MPEG解码器的IP单元确定以MHz指定的频率。
在步骤806中,应用请求PMCL 218 API调用。该调用的一个例子是“Set_Rate(单元Y、N MHz、允许的动态能量管理(DMP)的程度,DMP阈值、允许DMP折中的其它信息、利用动态偏置起动用于SPM的反偏置、等待加电标记)”。在该例子中,其它信息可以是“电源不断开,利用高Vt并关闭时钟作为替换”和“主要等待是大约10us,400ns阈值”。
PMCL 218确定可用于该单元的可能折中,并选择将支持步骤808中的请求频率的最低可能Vdd,并确定将被影响的SPM 264和274,和哪些些电源插针在步骤810中改变。
在步骤812中,PMCL 218发送命令至MPM 280,以使SPM 264和274(以及IPM)准备Vdd改变。在步骤814中,PMCL 218等待来自MPM 280的确认。在步骤816中,PMCL 218发送命令至SPU 290,以改变选择的电源插针上的Vdd,并等待受影响的区域“确定下来”。在步骤818中,该PMCL 218然后发送“在指定频率处重新开始操作”命令至MPM 280。在步骤810中,MPM 280传播重新开始命令至所有受影响的SPM 264和274(以及IPM)。在步骤822中,功率管理器(也就是MPM 280、IPM、或SPM 264和274)的一个设定指定频率,在步骤824中,在已经固定时钟之后重新开始IP单元操作。图8终止于步骤826。在一些实施例中,用户应用具有等待全部操作的选项,以结束或继续,以及关于操作的进展来查询PMCL 218或等待来自PMCL 218的“结束的”中断。
图9说明了当在本发明的示范性实施例中加电时,在断电和恢复IP单元的状态之前用于储存IP单元的状态的流程。图9开始于步骤900。在步骤902中,用户应用请求PMCL 218将IP单元断电,并希望存储IP单元的状态。在一些实施例中,IP单元的重新配置花费长的时间。通过状态被存储的区域的地址,可以完成步骤902中的请求。
在步骤904中,PMCL 218发送“停止时钟并读IP单元状态”信息至步骤906中被影响单元的SPM 264和274。在步骤908中,MPM280利用IP单元的扫描链将状态读入寄存器或缓冲器,以呈现给PMCL 218。在步骤910中,如果PMCL 218提供MPM 280存储区域的地址,MPM 280将状态信息直接存储在指定区域中。在步骤912中,在已经存储全部IP单元的全部状态之后,PMCL 218发送“IP单元断电”信息至MPM 280。在步骤914中,MPM 280然后传播出“IP单元断电”信息。在步骤916中,PMCL 218将该存储状态区域返回到用户应用。该存储状态区域包含单元的状态。
在随后的时间处,在步骤918中,用户应用请求PMCL 218通电IP单元,备份并恢复IP单元的状态。在一些实施例中,用户应用请求包括状态被存储到的区域的地址。在步骤920中,PMCL 218发送“IP单元加电,时钟关闭并恢复状态”信息至MPM 280。在步骤922中,MPM 280传播“IP单元加电,时钟关闭并恢复状态”信息给受影响的IP单元的SPM 264和274。在步骤924中,在加电IP单元之后,MPM 280利用扫描链重新加载单元的状态。在一些实施例中,单元的状态的重新加载直接发源于存储区域,或发源于从PMCL 218传递到MPM 280的信息。在步骤926中,PMCL 218发送信息到MPM 280,以使时钟往回走,并向用户应用报告IP单元即将继续操作。图9终止于步骤928。
在一些实施例中,图9的相同的功能性可以用于执行内部“逻辑分析器”功能,其中所讨论的IP单元在被读之后将不被断电。如果与IP单元的相联系的SPM 264和274具有单步或多步时钟的能力,通过具有SPM 264和274“单独隔离”IP单元来执行本地扫描测试。然后,单步或多步时钟的能力和使用扫描链的能力的组合的应用可以读/写IP单元的内部状态。
图10说明了本发明的示范性实施方式中片上系统(SOC)1000和扩展的本地存储器的图示。SOC 1000是集成电路250的一个例子,并与在如上面所述的图2中的嵌入的固件栈210通信。该SOC 1000包括CPU 1010、本地存储器1020、存储器控制器1030、混合信号电路1040、应用指定电路1050、PCI-X电路1060、MPM 1070、实时时钟(RTC)1075、以太网电路1080和USB电路1090。CPU 1010、本地存储器1020、存储器控制器1030、混合信号电路1040、应用指定电路1050、PCI-X电路1060、以太网电路1080和USB电路1090全部通电的岛,其中通过功率管理器在电源岛中控制功率。在该实施例中,通过SOC 1000的一部分的功能性描绘电源岛。
扩展的本地存储器1004包括耦合至总线1071的IPM 1006。CPU
1010包括耦合至总线1071的SPM 1015。本地存储器1020包括也耦合至总线1071的SPM 1025。存储器控制器1030包括耦合至总线1071的SPM 1035。混合信号电路1040包括耦合至总线1071的SPM 1045。应用指定电路1050包括都耦合至总线1072的IPM 1055和SPM 1058。PCI-X电路1060包括耦合至总线1072的SPM 1065。MPM 1070耦合至总线1071和总线1072。MPM 1070是如上面所述的MPM 280的一个例子。以太网电路1080包括耦合至总线1072的SPM 1085。USB电路1090包括耦合至总线1072的SPM 1095。
在该实施例中,功率命令总线包括总线1071和总线1072。总线1071和总线1072是可以跨过芯片边界和互连功率管理器的单独多压降串行总线。功率命令总线可以是串行总线的组合,比如总线1071和总线1072、芯片的每一区域、以及然后该区域中的多压降(multi-drop)。在其它实施例中,功率命令总线包括并行总线或串行和并行总线的组合。在一些实施例中,功率命令总线是系统总线。该功率命令总线可以包括与具有相联系的净负荷的至少一个单元ID的信息。对于到点总线的固定点,该信息不需要单元ID,仅有净负荷。
在一些实施例中,功率命令总线利用误差检测方案,比如奇偶性、ECC或冗余码。在一些实施例中,功率命令总线是不妨碍集成电路设计的低性能总线,并对用户是不可见的。在一些实施例中,PMCL 218和MPM 1070之间的通信是被映射的存储器,并基于主总线,比如用于SOC 1000的AHB。
一些实施例可以包括用于报告功率管理器之间的状态信息的单独总线。在一个例子中,该单独的总线从SPM至MPM的异步“告警信号”类型的状态信息。
可以是用于功率命令总线的各种信息格式。在用于基本格式的一个例子中,信息格式包括信息指示符的开始、功率管理器地址、类型编码、基本命令和信息指示符的末尾。在用于扩展格式的一个例子中,信息格式包括基本格式、附加长度和附加信息。在用于响应信息格式的一个例子中,信息格式包括信息回复指示符的开始、功率管理器地址、3b ACK或NAK或返回状态(隐含的ACK)、用于返回状态信息的净负荷长度、用于返回状态信息的净负荷(payload)、用于NAK的原因编码以及信息指示符的末尾。
在一些实施例中,SPM 1015或IPM 1006在回复命令时中断,并且MPM 1070重发命令,即可编程数量的次数。如果SPM 1015或IPM1006仍然失败,MPM 1070将SPM 1015或IPM 1006标记为不可用,并向回报告故障至PMCL 218。在一个实施例中,PMCL使MPM 1070通过扫描系统重新初始化失败的SPM 1015或IPM 1006,然后重试发送信息。也通过重新初始化处理比如对命令的无效响应或无效状态报告的其它情况。在一些实施例中,可以读出失败SPM 1015或IPM 1006的状态,或为了随后的分析将其存储。
图11描述了在本发明的示范性实施方式中用于产生从IPM 1055至PMCL 218的“热点”报告的流程。图11开始于步骤1100。在步骤1102中,IPM 1055监控SPM的温度统计。在步骤1104中,IPM 1055检查平均温度是否已经超出预定和编程的阈值。如果平均温度没有超出阈值,IPM 1055返回至步骤1102,以保持监控。如果平均温度已经超出阈值,IPM 1055然后在步骤1106中产生问题(“热点”)报告信息。在步骤1108中,IPM 1055等待MPM 1070下一状态查询。在一些实施例中,为至MPM 280的异步状态报告提供逻辑分离的总线。
在步骤1110中,MPM 1070接收热点报告信息。在步骤1112中,MPM 1070或等待进一步的确认(也就是“热点”最后越过预定阈值)或基于MPM 1070的内部逻辑立即采取行动以固定问题。在一些实施例中,在步骤1114中,通过提出需要注意的中断至PMCL 280,MPM1070采取行动(动作)。在其它实施例中,如果PMCL 280足够频繁地查询MPM 1070,则不需要中断。在步骤1116中,通过进行本地折中、执行动作或排序要被执行的动作,MPM 1070(或IPM)固定问题。固定问题的一个例子是降低热点区域的操作频率。在步骤1118中,MPM 1070向上游报告问题和问题的固定。
在步骤1120中,PMCL218读来自MPM 1070的修改的热点报告。在步骤1122中,PMCL 218确定采取什么动作以固定问题或向GPAL214通知问题。在步骤1124中,PMCL 218发出合适的命令至MPM
1070,以固定问题,在该步骤中,软件将进行需要的折中(trade-off),以固定问题。在一些实施例中,如果GPAL 214确定高电平固定,然后GPAL 214发送它至PMCL 280,以被转换成MPM命令。在步骤126中,PMCL 218在指定的时间段内监控问题区域,以检查是否固定问题。图11终止于步骤1128。
在一些实施例中,在比如PMCL 218的其它电平处可以执行图11中功能性的类型。在一个例子中,PMCL 218向(通过MPM 1070)具有期望的测量能力的全部SPM(以及IPM)查询它们的本地环境,并然后例如建立它可以起作用的功率用途的“图”。
图12描述了在本发明的另一示范性实施方式中片上系统(SOC)1200的图示。SOC 1200连接至传感器链路1212、RF链路1214、控制链路1216、视频链路1295、接口链路1296、控制链路1217和功率链路1298。SOC 1200包括时钟和分布管理1210、IP块电源岛1220、存储器电源岛1230、微处理器电源岛1240、IP块电源岛1250、分布电源岛1260、IP块电源岛1270、IP块电源岛1280和功率和分布管理1290。
IP块电源岛1220包括产品标准接口IP块,所述产品标准接口IP块包括模拟数字转换器(ADC)122,其包括SPM 1224。存储器电源岛1230包括存储器1232,其包括SPM 1234。微处理器电源岛1240包括微处理器1242,其包括SPM 1244。IP块电源岛1250包括产品标准接口IP块,所述产品标准接口IP块包括ADC 1252,其包括SPM
1254。分布电源岛1260包括数字和信号分布1262,其包括SPM 1264。IP块电源岛1270包括通用IP块,所述通用IP块包括数字信号处理器(DSP)1272,其包括SPM 1274。IP块电源岛1280包括产品指定IP块1282,其包括SPM 1284。功率和分布管理1290包括MPM 1292。
图13描述了在本发明的示范性实施方式中用于建立具有电源岛的芯片的流程。图13开始于步骤1300。在步骤1302中,选择IP或模块库单元,如果有的话,指定定制逻辑用于建立芯片。在一些实施例中,指定最大时钟速率和子时钟速率、%空闲时间和最小和最大Vdd。在步骤1304中,写入寄存器传递电平(RTL)。在步骤1306中,模拟和调试RTL。
在RTL的写入过程中或者之后,软件工具可以用于在步骤1308中为MPM、IPM和/或SPM块添加注释。在一些实施例中,在注释中指定期望的功能性选择。在一些实施例中,利用每一模块基础上的SPM确认信息注释RTL。在一些实施例中,在RTL的写入过程中或者之后,在每一模块基础上通过手动插入合适的注释。在其它实施例中,利用模块名称和各自的注释产生合适格式中的单独表格。在一些实施例中,单独的软件工具提供交互建立单独的表格的能力。在一些实施例中,利用来自表格的信息,软件工具添加合适的注释至RTL中未注释的模块。
在步骤1310中,在电源岛基础上运行综合,在这种情况中不混合电源岛。在步骤1312中,在用于每一Vdd和Vt选择的每一模块上运行性能测量软件,然后添加用于MPM的注释至RTL。在一些实施例中,在全部期望的电压和Vt组合处测量设计的性能。软件工具然后导出实际的频率、Vdd和Vt表格,以用于每一SPM和向回注释SPM特性的MPM(或IPM)RTL。
在步骤1314中,在电源岛基础上运行最后综合。在一些实施例中,模块被分别路由,或通过SPM。在步骤1316中,运行软件工具,以将电源和时钟与每一SPM关联。步骤1318是到分出(TAPE-OUT)的剩余步骤。在一些实施例中,软件工具产生具有全部信息的完成的网表(net-list)。
上面所述的部件由在存储介质上存储的指令构成。通过处理器可以重现和执行该指令。指令的一些例子是软件、程序编码以及固件。存储介质的一些例子是存储器装置、磁带、磁盘、集成电路和服务器。当通过处理器执行时,所述指令是可操作的,以导引处理器依据本发明工作。本领域的普通技术人员熟悉指令、处理器和存储介质。
上面的说明是描述的和不受限制的。基于所述公开内容的阅读,本发明的多种变形对本领域的普通技术人员是显而易见的。因此将不参照上面的说明确定本发明的范围,相反通过参照附加权利要求和它们的等价物的全部范围对其确定。

Claims (15)

1. 一种管理包括多个电源岛的集成电路上的功率的方法,所述方法包括:
基于集成电路的需要和操作确定电源岛之一的目标功率电平,其中在电源岛的每一个中独立控制功率消耗;
从多个动作中确定将电源岛之一的消耗功率电平改变到目标功率电平的至少一个动作,所述多个动作中的一个包括为电源岛选择频率;以及
执行所述将电源岛之一的消耗功率电平改变到目标功率电平的至少一个动作。
2. 权利要求1的方法,进一步包括:
监控电源岛之一的功率消耗电平;
基于功率消耗电平确定阈值电平是否被跨越;以及
基于阈值电平的跨越执行所述多个动作中的一个。
3. 权利要求1的方法,其中基于由集成电路的功能电路和集成电路的地理因数构成的组中的一个来描绘电源岛。
4. 权利要求1的方法,其中电源岛包括由电源子岛和多时钟域构成的组中的一个。
5. 权利要求1的方法,其中所述多个动作中的一个包括由下面的动作构成的组中的一个:为电源岛之一选择时钟、为电源岛之一修改第一电压、通电电源岛之一、断电电源岛之一、将电源岛之一改变到休眠模式、保存电源岛之一中的部件的状态和恢复电源岛之一中的部件的状态。
6. 权利要求1的方法,其中所述多个动作中的一个包括为电源岛之一修改第一电压,其中所述第一电压包括由源电压和阈值电压构成的组中的一个。
7. 一种用于包括多个电源岛的集成电路的系统,其中在所述电源岛的每一个中独立控制功率消耗,所述系统包括:
功率控制电路,配置用于控制电源岛之一的功率;以及
功率管理器,配置用于基于集成电路的需要和操作确定电源岛之一的目标功率电平,从多个动作中确定将电源岛之一的消耗功率电平改变到目标功率电平的至少一个动作,并且执行所述将电源岛之一的消耗功率电平改变到目标功率电平的至少一个动作,其中所述多个动作中的一个包括为电源岛之一选择频率。
8. 权利要求7的系统,其中该功率管理器配置用于监控电源岛之一的功率消耗电平,基于功率消耗电平确定阈值电平是否被跨越,并且基于阈值电平的跨越执行所述多个动作中的一个。
9. 权利要求7的系统,其中基于由集成电路的功能电路和集成电路的地理因数构成的组中的一个来描绘电源岛。
10. 权利要求7的系统,其中电源岛包括由电源子岛和多时钟域构成的组中的一个。
11. 权利要求7的系统,其中所述多个动作中的一个包括由以下动作构成的组中的一个:为电源岛之一选择时钟、为电源岛之一修改第一电压、通电电源岛之一、断电电源岛之一、将电源岛之一改变到休眠模式、保存电源岛之一中的部件的状态和恢复电源岛之一中的部件的状态。
12. 权利要求7的系统,其中所述多个动作中的一个包括为电源岛之一修改第一电压,其中所述第一电压包括由源电压和阈值电压构成的组中的一个。
13. 权利要求7的系统,进一步包括耦合至功率管理器和电源岛的总线。
14. 权利要求7的系统,其中功率管理器包括由主管理器和从管理器构成的组中的一个,所述主管理器配置用于控制集成电路的功率,所述从管理器配置用于控制集成电路的功率。
15. 权利要求7的系统,其中功率控制电路包括由时钟多路复用电路、电压多路复用电路和电平位移电路构成的组中的一个。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101840446B (zh) * 2009-01-30 2016-01-27 技领半导体(上海)有限公司 从模拟拼片传输配置信息到另一拼片的方法

Families Citing this family (250)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6895520B1 (en) 2001-03-02 2005-05-17 Advanced Micro Devices, Inc. Performance and power optimization via block oriented performance measurement and control
US7039819B1 (en) * 2003-04-30 2006-05-02 Advanced Micro Devices, Inc. Apparatus and method for initiating a sleep state in a system on a chip device
CN100416573C (zh) 2003-05-07 2008-09-03 睦塞德技术公司 利用电源岛管理集成电路上的功率
KR20060027804A (ko) * 2003-06-10 2006-03-28 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 집적 회로
US7170315B2 (en) * 2003-07-31 2007-01-30 Actel Corporation Programmable system on a chip
WO2005024910A2 (en) 2003-09-09 2005-03-17 Robert Eisenstadt Apparatus and method for integrated circuit power management
US7227383B2 (en) 2004-02-19 2007-06-05 Mosaid Delaware, Inc. Low leakage and data retention circuitry
US7138824B1 (en) * 2004-05-10 2006-11-21 Actel Corporation Integrated multi-function analog circuit including voltage, current, and temperature monitor and gate-driver circuit blocks
KR100750590B1 (ko) * 2004-06-15 2007-08-20 삼성전자주식회사 파워-업시 내부 전원 전압 제어 방법 및 장치, 이를가지는 반도체 메모리 장치
US9281718B2 (en) * 2004-06-28 2016-03-08 Broadcom Corporation On-board power supply monitor and power control system
US7409315B2 (en) * 2004-06-28 2008-08-05 Broadcom Corporation On-board performance monitor and power control system
US7926008B2 (en) * 2004-06-28 2011-04-12 Broadcom Corporation Integrated circuit with on-board power utilization information
US7382178B2 (en) * 2004-07-09 2008-06-03 Mosaid Technologies Corporation Systems and methods for minimizing static leakage of an integrated circuit
US7984398B1 (en) * 2004-07-19 2011-07-19 Synopsys, Inc. Automated multiple voltage/power state design process and chip description system
US7434073B2 (en) * 2004-11-29 2008-10-07 Intel Corporation Frequency and voltage scaling architecture
US20060119382A1 (en) * 2004-12-07 2006-06-08 Shumarayev Sergey Y Apparatus and methods for adjusting performance characteristics of programmable logic devices
US7131099B2 (en) * 2004-12-09 2006-10-31 International Business Machines Corporation Method, apparatus, and computer program product for RTL power sequencing simulation of voltage islands
US7275164B2 (en) * 2005-01-31 2007-09-25 International Business Machines Corporation System and method for fencing any one of the plurality of voltage islands using a lookup table including AC and DC components for each functional block of the voltage islands
CN1844946A (zh) * 2005-04-08 2006-10-11 株式会社东芝 半导体集成电路及其延迟检测方法
US7454738B2 (en) * 2005-06-10 2008-11-18 Purdue Research Foundation Synthesis approach for active leakage power reduction using dynamic supply gating
US7482792B2 (en) 2005-06-14 2009-01-27 Intel Corporation IC with fully integrated DC-to-DC power converter
US7598630B2 (en) 2005-07-29 2009-10-06 Intel Corporation IC with on-die power-gating circuit
US7574683B2 (en) * 2005-08-05 2009-08-11 John Wilson Automating power domains in electronic design automation
US7264985B2 (en) * 2005-08-31 2007-09-04 Freescale Semiconductor, Inc. Passive elements in MRAM embedded integrated circuits
US7609799B2 (en) * 2005-09-02 2009-10-27 Cypress Semiconductor Corporation Circuit, system, and method for multiplexing signals with reduced jitter
US7554843B1 (en) * 2005-11-04 2009-06-30 Alta Analog, Inc. Serial bus incorporating high voltage programming signals
US7716612B1 (en) * 2005-12-29 2010-05-11 Tela Innovations, Inc. Method and system for integrated circuit optimization by using an optimized standard-cell library
US7421601B2 (en) * 2006-02-17 2008-09-02 International Business Machines Corporation Method and system for controlling power in a chip through a power-performance monitor and control unit
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US7932545B2 (en) 2006-03-09 2011-04-26 Tela Innovations, Inc. Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US8214778B2 (en) 2007-08-02 2012-07-03 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US7908578B2 (en) 2007-08-02 2011-03-15 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8247846B2 (en) 2006-03-09 2012-08-21 Tela Innovations, Inc. Oversized contacts and vias in semiconductor chip defined by linearly constrained topology
US8245180B2 (en) 2006-03-09 2012-08-14 Tela Innovations, Inc. Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US8225239B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining and utilizing sub-resolution features in linear topology
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US7943967B2 (en) 2006-03-09 2011-05-17 Tela Innovations, Inc. Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US8225261B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining contact grid in dynamic array architecture
US7454642B2 (en) * 2006-03-31 2008-11-18 International Business Machines Corporation Method and architecture for power management of an electronic device
US7739629B2 (en) * 2006-04-14 2010-06-15 Cadence Design Systems, Inc. Method and mechanism for implementing electronic designs having power information specifications background
US20090230769A1 (en) * 2006-06-15 2009-09-17 Koninklijke Philips Electronics N.V. method of balancing power consumption between loads
US7949887B2 (en) 2006-11-01 2011-05-24 Intel Corporation Independent power control of processing cores
US8397090B2 (en) * 2006-12-08 2013-03-12 Intel Corporation Operating integrated circuit logic blocks at independent voltages with single voltage supply
US7899434B2 (en) * 2006-12-15 2011-03-01 Broadcom Corporation Power management for a mobile communication device and method for use therewith
CN101627347B (zh) * 2006-12-31 2012-07-04 桑迪士克股份有限公司 在功率岛边界处具有保护的系统、电路、芯片及方法
US20080162954A1 (en) * 2006-12-31 2008-07-03 Paul Lassa Selectively powered data interfaces
TW200900910A (en) * 2006-12-31 2009-01-01 Sandisk Corp Systems, methods, and integrated circuits with inrush-limited power islands
US8304813B2 (en) * 2007-01-08 2012-11-06 SanDisk Technologies, Inc. Connection between an I/O region and the core region of an integrated circuit
TW200835151A (en) * 2007-02-15 2008-08-16 Univ Nat Chiao Tung Low-power dynamic sequential controlling multiplexer
US8286107B2 (en) 2007-02-20 2012-10-09 Tela Innovations, Inc. Methods and systems for process compensation technique acceleration
US7979829B2 (en) 2007-02-20 2011-07-12 Tela Innovations, Inc. Integrated circuit cell library with cell-level process compensation technique (PCT) application and associated methods
US7735030B1 (en) * 2007-02-28 2010-06-08 Cadence Design Systems, Inc. Simulating restorable registers in power domain systems
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8135944B2 (en) * 2007-03-14 2012-03-13 Sandisk Technologies Inc. Selectively powered data interfaces
US7739626B2 (en) * 2007-04-20 2010-06-15 Iwatt Inc. Method and apparatus for small die low power system-on-chip design with intelligent power supply chip
US7954078B1 (en) * 2007-06-29 2011-05-31 Cadence Design Systems, Inc. High level IC design with power specification and power source hierarchy
US8055925B2 (en) * 2007-07-18 2011-11-08 International Business Machines Corporation Structure and method to optimize computational efficiency in low-power environments
US8122273B2 (en) * 2007-07-18 2012-02-21 International Business Machines Corporation Structure and method to optimize computational efficiency in low-power environments
US20090037629A1 (en) * 2007-08-01 2009-02-05 Broadcom Corporation Master slave core architecture with direct buses
US7941679B2 (en) 2007-08-10 2011-05-10 Atrenta, Inc. Method for computing power savings and determining the preferred clock gating circuit of an integrated circuit design
US8205182B1 (en) * 2007-08-22 2012-06-19 Cadence Design Systems, Inc. Automatic synthesis of clock distribution networks
US7710800B2 (en) * 2007-12-12 2010-05-04 International Business Machines Corporation Managing redundant memory in a voltage island
US20090157334A1 (en) * 2007-12-14 2009-06-18 Kenneth Joseph Goodnow Measurement of power consumption within an integrated circuit
US7715995B2 (en) * 2007-12-14 2010-05-11 International Business Machines Corporation Design structure for measurement of power consumption within an integrated circuit
US8327173B2 (en) 2007-12-17 2012-12-04 Nvidia Corporation Integrated circuit device core power down independent of peripheral device operation
US8112641B2 (en) * 2007-12-26 2012-02-07 Cisco Technology, Inc. Facilitating communication and power transfer between electrically-isolated powered device subsystems
US7830039B2 (en) * 2007-12-28 2010-11-09 Sandisk Corporation Systems and circuits with multirange and localized detection of valid power
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US9411390B2 (en) 2008-02-11 2016-08-09 Nvidia Corporation Integrated circuit device having power domains and partitions based on use case power optimization
US20090204835A1 (en) * 2008-02-11 2009-08-13 Nvidia Corporation Use methods for power optimization using an integrated circuit having power domains and partitions
US7898285B2 (en) * 2008-03-26 2011-03-01 International Business Machines Corporation Optimal local supply voltage determination circuit
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US9423846B2 (en) 2008-04-10 2016-08-23 Nvidia Corporation Powered ring to maintain IO state independent of the core of an integrated circuit device
US8607177B2 (en) 2008-04-10 2013-12-10 Nvidia Corporation Netlist cell identification and classification to reduce power consumption
US8762759B2 (en) 2008-04-10 2014-06-24 Nvidia Corporation Responding to interrupts while in a reduced power state
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US20100057404A1 (en) * 2008-08-29 2010-03-04 International Business Machines Corporation Optimal Performance and Power Management With Two Dependent Actuators
US8001405B2 (en) * 2008-08-29 2011-08-16 International Business Machines Corporation Self-tuning power management techniques
GB2464510B (en) * 2008-10-17 2013-09-04 Advanced Risc Mach Ltd Power control of an integrated circuit including an array of interconnected configurable logic elements
US9189049B2 (en) * 2008-12-24 2015-11-17 Stmicroelectronics International N.V. Power management in a device
US8161304B2 (en) * 2009-01-20 2012-04-17 Microsoft Corporation Power management for large memory subsystems
US8341582B2 (en) * 2009-01-30 2012-12-25 Active-Semi, Inc. Programmable analog tile configuration tool
US8248152B2 (en) * 2009-02-25 2012-08-21 International Business Machines Corporation Switched capacitor voltage converters
US8127167B2 (en) * 2009-03-30 2012-02-28 Mediatek Inc. Methods for reducing power consumption and devices using the same
US8174288B2 (en) 2009-04-13 2012-05-08 International Business Machines Corporation Voltage conversion and integrated circuits with stacked voltage domains
EP2437170A4 (en) 2009-05-25 2013-03-13 Panasonic Corp MULTIPROCESSOR SYSTEM, MULTIPROCESSOR CONTROL METHOD AND INTEGRATED MULTIPROCESSOR CIRCUIT
US8004922B2 (en) 2009-06-05 2011-08-23 Nxp B.V. Power island with independent power characteristics for memory and logic
US8385148B2 (en) * 2009-06-15 2013-02-26 Broadcom Corporation Scalable, dynamic power management scheme for switching architectures utilizing multiple banks
US8533388B2 (en) * 2009-06-15 2013-09-10 Broadcom Corporation Scalable multi-bank memory architecture
US8370683B1 (en) 2009-07-31 2013-02-05 Western Digital Technologies, Inc. System and method to reduce write splice failures
US7977972B2 (en) * 2009-08-07 2011-07-12 The Board Of Trustees Of The University Of Arkansas Ultra-low power multi-threshold asynchronous circuit design
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US8276002B2 (en) * 2009-11-23 2012-09-25 International Business Machines Corporation Power delivery in a heterogeneous 3-D stacked apparatus
US8502590B2 (en) 2009-12-14 2013-08-06 The Boeing Company System and method of controlling devices operating within different voltage ranges
US9058440B1 (en) * 2009-12-15 2015-06-16 Cadence Design Systems, Inc. Method and mechanism for verifying and simulating power aware mixed-signal electronic designs
US8356194B2 (en) 2010-01-28 2013-01-15 Cavium, Inc. Method and apparatus for estimating overshoot power after estimating power of executing events
JP5610566B2 (ja) * 2010-02-22 2014-10-22 ルネサスエレクトロニクス株式会社 半導体装置及びデータ処理システム
US20120017100A1 (en) * 2010-02-25 2012-01-19 Emmanuel Petit Power System Optimization and Verification for Embedded System Design
US8271812B2 (en) * 2010-04-07 2012-09-18 Apple Inc. Hardware automatic performance state transitions in system on processor sleep and wake events
KR20110124617A (ko) * 2010-05-11 2011-11-17 삼성전자주식회사 시스템-온-칩 및 그것의 디버깅 방법
US20110283130A1 (en) * 2010-05-17 2011-11-17 Global Unichip Corporation Power control manager
US8629705B2 (en) 2010-06-07 2014-01-14 International Business Machines Corporation Low voltage signaling
CN102314208B (zh) * 2010-06-30 2016-08-03 重庆重邮信科通信技术有限公司 一种动态调整嵌入式设备频率电压的方法及装置
TWI411930B (zh) * 2010-07-15 2013-10-11 Faraday Tech Corp 系統階層模擬/驗證系統及其方法
US8601288B2 (en) 2010-08-31 2013-12-03 Sonics, Inc. Intelligent power controller
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US9709625B2 (en) * 2010-11-19 2017-07-18 International Business Machines Corporation Measuring power consumption in an integrated circuit
US8756442B2 (en) 2010-12-16 2014-06-17 Advanced Micro Devices, Inc. System for processor power limit management
JP5630870B2 (ja) * 2011-02-18 2014-11-26 ルネサスエレクトロニクス株式会社 半導体集積回路のレイアウト方法及びプログラム
US20120226949A1 (en) * 2011-03-02 2012-09-06 Texas Instruments Incorporated Multi-Channel Bus Protection
JP5647062B2 (ja) * 2011-04-28 2014-12-24 富士通フロンテック株式会社 最大消費電力軽減装置
EP2667547B1 (en) 2011-07-29 2016-01-20 Huawei Technologies Co., Ltd. Bandwidth adjustment method, bus controller and signal converter
US8918102B2 (en) * 2011-07-29 2014-12-23 At&T Intellectual Property I, L.P. Method and system for selecting from a set of candidate frequency bands associated with a wireless access point
KR101861743B1 (ko) * 2011-09-19 2018-05-30 삼성전자주식회사 이종의 전력 제어와 동종의 전력 제어를 선택적으로 수행할 수 있는 시스템-온 칩과 이의 동작 방법
US8868941B2 (en) * 2011-09-19 2014-10-21 Sonics, Inc. Apparatus and methods for an interconnect power manager
US9680773B1 (en) 2011-09-26 2017-06-13 Altera Corporation Integrated circuit with dynamically-adjustable buffer space for serial interface
JP5660010B2 (ja) * 2011-11-21 2015-01-28 トヨタ自動車株式会社 情報処理装置、データ復帰方法
US9400545B2 (en) 2011-12-22 2016-07-26 Intel Corporation Method, apparatus, and system for energy efficiency and energy conservation including autonomous hardware-based deep power down in devices
US9773344B2 (en) 2012-01-11 2017-09-26 Nvidia Corporation Graphics processor clock scaling based on idle time
US9158359B2 (en) * 2012-03-23 2015-10-13 Avago Technologies General Ip (Singapore) Pte. Ltd. Adaptive voltage scaling using a serial interface
US9529953B2 (en) * 2012-08-02 2016-12-27 The United States Of America, As Represented By The Secretary Of The Navy Subthreshold standard cell library
US9471395B2 (en) 2012-08-23 2016-10-18 Nvidia Corporation Processor cluster migration techniques
US8947137B2 (en) 2012-09-05 2015-02-03 Nvidia Corporation Core voltage reset systems and methods with wide noise margin
US20140136873A1 (en) * 2012-11-14 2014-05-15 Advanced Micro Devices, Inc. Tracking memory bank utility and cost for intelligent power up decisions
US9946319B2 (en) * 2012-11-20 2018-04-17 Advanced Micro Devices, Inc. Setting power-state limits based on performance coupling and thermal coupling between entities in a computing device
US9811874B2 (en) 2012-12-31 2017-11-07 Nvidia Corporation Frame times by dynamically adjusting frame buffer resolution
US9633872B2 (en) 2013-01-29 2017-04-25 Altera Corporation Integrated circuit package with active interposer
US8710906B1 (en) 2013-02-12 2014-04-29 Freescale Semiconductor, Inc. Fine grain voltage scaling of back biasing
US9335809B2 (en) * 2013-03-15 2016-05-10 Seagate Technology Llc Volatile memory storing system data during low power mode operation and monitoring the voltage supplied to the memory during low power mode
US9411394B2 (en) * 2013-03-15 2016-08-09 Seagate Technology Llc PHY based wake up from low power mode operation
US10409353B2 (en) * 2013-04-17 2019-09-10 Qualcomm Incorporated Dynamic clock voltage scaling (DCVS) based on application performance in a system-on-a-chip (SOC), and related methods and processor-based systems
US9094013B2 (en) 2013-05-24 2015-07-28 The Board Of Trustees Of The University Of Arkansas Single component sleep-convention logic (SCL) modules
US9059696B1 (en) 2013-08-01 2015-06-16 Altera Corporation Interposer with programmable power gating granularity
US9172373B2 (en) * 2013-09-06 2015-10-27 Globalfoundries U.S. 2 Llc Verifying partial good voltage island structures
US9671844B2 (en) 2013-09-26 2017-06-06 Cavium, Inc. Method and apparatus for managing global chip power on a multicore system on chip
JP2015069333A (ja) * 2013-09-27 2015-04-13 富士通セミコンダクター株式会社 設計方法及び設計プログラム
US9594413B2 (en) * 2013-12-24 2017-03-14 Intel Corporation Interface for communication between circuit blocks of an integrated circuit, and associated apparatuses, systems, and methods
US9058459B1 (en) * 2013-12-30 2015-06-16 Samsung Electronics Co., Ltd. Integrated circuit layouts and methods to reduce leakage
KR101538458B1 (ko) 2014-01-03 2015-07-23 연세대학교 산학협력단 3차원 매니코어 프로세서를 위한 전압섬 형성 방법
US9329237B2 (en) 2014-01-10 2016-05-03 Freescale Semiconductor, Inc. Switch detection device and method of use
EP3113085A4 (en) * 2014-02-27 2017-01-18 Panasonic Intellectual Property Corporation of America Control method, information provision method and program
US9257839B2 (en) 2014-02-28 2016-02-09 Freescale Semiconductor, Inc. Systems and methods for managing multiple power domains
US9766684B2 (en) 2014-07-21 2017-09-19 Apple Inc. Telemetry for power and thermal management
KR102320399B1 (ko) 2014-08-26 2021-11-03 삼성전자주식회사 전원 관리 칩, 그것을 포함하는 모바일 장치 및 그것의 클록 조절 방법
CN105446653B (zh) 2014-08-27 2018-12-14 阿里巴巴集团控股有限公司 一种数据合并方法和设备
US10416750B2 (en) 2014-09-26 2019-09-17 Qualcomm Incorporated Algorithm engine for ultra low-power processing of sensor data
US9811142B2 (en) 2014-09-29 2017-11-07 Apple Inc. Low energy processor for controlling operating states of a computer system
CN105573463A (zh) * 2014-10-17 2016-05-11 深圳市中兴微电子技术有限公司 一种功耗管理方法及装置
US10101786B2 (en) * 2014-12-22 2018-10-16 Intel Corporation Holistic global performance and power management
US9829902B2 (en) * 2014-12-23 2017-11-28 Intel Corporation Systems and methods for dynamic temporal power steering
US9785211B2 (en) 2015-02-13 2017-10-10 Qualcomm Incorporated Independent power collapse methodology
CN108140058A (zh) 2015-06-05 2018-06-08 恩都冉科技 Pdn实施及数字共合成的集成系统
US10152112B2 (en) 2015-06-10 2018-12-11 Sonics, Inc. Power manager with a power switch arbitrator
US9608605B2 (en) * 2015-08-06 2017-03-28 Futurewei Technologies, Inc. Apparatus and scheme for IO-pin-less calibration or trimming of on-chip regulators
US10078356B2 (en) * 2015-08-20 2018-09-18 Intel Corporation Apparatus and method for saving and restoring data for power saving in a processor
US9576615B1 (en) * 2015-10-15 2017-02-21 Smart Modular Technologies, Inc. Memory module with power management system and method of operation thereof
FR3043476B1 (fr) * 2015-11-05 2018-09-28 Dolphin Integration Systeme et procede de gestion d'alimentation
US10516304B2 (en) * 2015-12-22 2019-12-24 Intel Corporation Wireless charging coil placement for reduced field exposure
US10411492B2 (en) 2015-12-23 2019-09-10 Intel Corporation Wireless power transmitter shield with capacitors
US10133341B2 (en) * 2016-06-06 2018-11-20 Arm Limited Delegating component power control
KR20180039463A (ko) * 2016-10-10 2018-04-18 삼성전자주식회사 이상 동작을 제어하기 위한 전자 장치 및 방법
US11068018B2 (en) * 2016-10-25 2021-07-20 Dolphin Design System and method for power management of a computing system with a plurality of islands
US10148270B2 (en) 2017-03-15 2018-12-04 Quicklogic Corporation Switchable power islands having configurably on routing paths
US10359954B2 (en) 2017-05-31 2019-07-23 Alibaba Group Holding Limited Method and system for implementing byte-alterable write cache
US10884926B2 (en) 2017-06-16 2021-01-05 Alibaba Group Holding Limited Method and system for distributed storage using client-side global persistent cache
US10229003B2 (en) 2017-06-16 2019-03-12 Alibaba Group Holding Limited Method and system for iterative data recovery and error correction in a distributed system
US10303241B2 (en) 2017-06-19 2019-05-28 Alibaba Group Holding Limited System and method for fine-grained power control management in a high capacity computer cluster
US10564856B2 (en) 2017-07-06 2020-02-18 Alibaba Group Holding Limited Method and system for mitigating write amplification in a phase change memory-based storage device
US10678443B2 (en) 2017-07-06 2020-06-09 Alibaba Group Holding Limited Method and system for high-density converged storage via memory bus
US10303601B2 (en) 2017-08-11 2019-05-28 Alibaba Group Holding Limited Method and system for rearranging a write operation in a shingled magnetic recording device
US10423508B2 (en) 2017-08-11 2019-09-24 Alibaba Group Holding Limited Method and system for a high-priority read based on an in-place suspend/resume write
US10496829B2 (en) 2017-09-15 2019-12-03 Alibaba Group Holding Limited Method and system for data destruction in a phase change memory-based storage device
US10642522B2 (en) 2017-09-15 2020-05-05 Alibaba Group Holding Limited Method and system for in-line deduplication in a storage drive based on a non-collision hash
US10503409B2 (en) 2017-09-27 2019-12-10 Alibaba Group Holding Limited Low-latency lightweight distributed storage system
US10789011B2 (en) 2017-09-27 2020-09-29 Alibaba Group Holding Limited Performance enhancement of a storage device using an integrated controller-buffer
US10642338B2 (en) * 2017-09-28 2020-05-05 Intel Corporation Hierarchical power management unit for low power and low duty cycle devices
US10860334B2 (en) 2017-10-25 2020-12-08 Alibaba Group Holding Limited System and method for centralized boot storage in an access switch shared by multiple servers
US10445190B2 (en) 2017-11-08 2019-10-15 Alibaba Group Holding Limited Method and system for enhancing backup efficiency by bypassing encoding and decoding
US10877898B2 (en) 2017-11-16 2020-12-29 Alibaba Group Holding Limited Method and system for enhancing flash translation layer mapping flexibility for performance and lifespan improvements
US10580730B2 (en) 2017-11-16 2020-03-03 International Business Machines Corporation Managed integrated circuit power supply distribution
US10340916B1 (en) * 2017-12-29 2019-07-02 Advanced Micro Devices, Inc. Using islands to control operating parameters for functional blocks in an electronic device
US10891239B2 (en) 2018-02-07 2021-01-12 Alibaba Group Holding Limited Method and system for operating NAND flash physical space to extend memory capacity
US10496548B2 (en) 2018-02-07 2019-12-03 Alibaba Group Holding Limited Method and system for user-space storage I/O stack with user-space flash translation layer
US10831404B2 (en) 2018-02-08 2020-11-10 Alibaba Group Holding Limited Method and system for facilitating high-capacity shared memory using DIMM from retired servers
US10402112B1 (en) 2018-02-14 2019-09-03 Alibaba Group Holding Limited Method and system for chunk-wide data organization and placement with real-time calculation
US10629533B2 (en) 2018-03-13 2020-04-21 Toshiba Memory Corporation Power island segmentation for selective bond-out
US11379155B2 (en) 2018-05-24 2022-07-05 Alibaba Group Holding Limited System and method for flash storage management using multiple open page stripes
US11816043B2 (en) 2018-06-25 2023-11-14 Alibaba Group Holding Limited System and method for managing resources of a storage device and quantifying the cost of I/O requests
US10921992B2 (en) 2018-06-25 2021-02-16 Alibaba Group Holding Limited Method and system for data placement in a hard disk drive based on access frequency for improved IOPS and utilization efficiency
US10740257B2 (en) * 2018-07-02 2020-08-11 International Business Machines Corporation Managing accelerators in application-specific integrated circuits
US10871921B2 (en) 2018-07-30 2020-12-22 Alibaba Group Holding Limited Method and system for facilitating atomicity assurance on metadata and data bundled storage
US10747673B2 (en) 2018-08-02 2020-08-18 Alibaba Group Holding Limited System and method for facilitating cluster-level cache and memory space
US10996886B2 (en) 2018-08-02 2021-05-04 Alibaba Group Holding Limited Method and system for facilitating atomicity and latency assurance on variable sized I/O
US11327929B2 (en) 2018-09-17 2022-05-10 Alibaba Group Holding Limited Method and system for reduced data movement compression using in-storage computing and a customized file system
US10852948B2 (en) 2018-10-19 2020-12-01 Alibaba Group Holding System and method for data organization in shingled magnetic recording drive
US10795586B2 (en) 2018-11-19 2020-10-06 Alibaba Group Holding Limited System and method for optimization of global data placement to mitigate wear-out of write cache and NAND flash
US10769018B2 (en) 2018-12-04 2020-09-08 Alibaba Group Holding Limited System and method for handling uncorrectable data errors in high-capacity storage
US10977122B2 (en) 2018-12-31 2021-04-13 Alibaba Group Holding Limited System and method for facilitating differentiated error correction in high-density flash devices
US10884654B2 (en) 2018-12-31 2021-01-05 Alibaba Group Holding Limited System and method for quality of service assurance of multi-stream scenarios in a hard disk drive
US11061735B2 (en) 2019-01-02 2021-07-13 Alibaba Group Holding Limited System and method for offloading computation to storage nodes in distributed system
US11132291B2 (en) 2019-01-04 2021-09-28 Alibaba Group Holding Limited System and method of FPGA-executed flash translation layer in multiple solid state drives
US11200337B2 (en) 2019-02-11 2021-12-14 Alibaba Group Holding Limited System and method for user data isolation
US10922234B2 (en) 2019-04-11 2021-02-16 Alibaba Group Holding Limited Method and system for online recovery of logical-to-physical mapping table affected by noise sources in a solid state drive
US10908960B2 (en) 2019-04-16 2021-02-02 Alibaba Group Holding Limited Resource allocation based on comprehensive I/O monitoring in a distributed storage system
EP3726231A1 (en) * 2019-04-17 2020-10-21 Volkswagen Aktiengesellschaft Electronic component and system with integrated self-test functionality
US11169873B2 (en) 2019-05-21 2021-11-09 Alibaba Group Holding Limited Method and system for extending lifespan and enhancing throughput in a high-density solid state drive
US10860223B1 (en) 2019-07-18 2020-12-08 Alibaba Group Holding Limited Method and system for enhancing a distributed storage system by decoupling computation and network tasks
US11093019B2 (en) 2019-07-29 2021-08-17 Microsoft Technology Licensing, Llc Integrated circuit power domains segregated among power supply phases
US11126561B2 (en) 2019-10-01 2021-09-21 Alibaba Group Holding Limited Method and system for organizing NAND blocks and placing data to facilitate high-throughput for random writes in a solid state drive
CN111143275A (zh) * 2019-12-27 2020-05-12 南方电网科学研究院有限责任公司 一种ip管理和功耗优化系统及方法
US11042307B1 (en) 2020-01-13 2021-06-22 Alibaba Group Holding Limited System and method for facilitating improved utilization of NAND flash based on page-wise operation
US11449455B2 (en) 2020-01-15 2022-09-20 Alibaba Group Holding Limited Method and system for facilitating a high-capacity object storage system with configuration agility and mixed deployment flexibility
US10923156B1 (en) 2020-02-19 2021-02-16 Alibaba Group Holding Limited Method and system for facilitating low-cost high-throughput storage for accessing large-size I/O blocks in a hard disk drive
US10872622B1 (en) 2020-02-19 2020-12-22 Alibaba Group Holding Limited Method and system for deploying mixed storage products on a uniform storage infrastructure
US11150986B2 (en) 2020-02-26 2021-10-19 Alibaba Group Holding Limited Efficient compaction on log-structured distributed file system using erasure coding for resource consumption reduction
US11144250B2 (en) 2020-03-13 2021-10-12 Alibaba Group Holding Limited Method and system for facilitating a persistent memory-centric system
US11200114B2 (en) 2020-03-17 2021-12-14 Alibaba Group Holding Limited System and method for facilitating elastic error correction code in memory
US11385833B2 (en) 2020-04-20 2022-07-12 Alibaba Group Holding Limited Method and system for facilitating a light-weight garbage collection with a reduced utilization of resources
US11281575B2 (en) 2020-05-11 2022-03-22 Alibaba Group Holding Limited Method and system for facilitating data placement and control of physical addresses with multi-queue I/O blocks
US11461262B2 (en) 2020-05-13 2022-10-04 Alibaba Group Holding Limited Method and system for facilitating a converged computation and storage node in a distributed storage system
US11494115B2 (en) 2020-05-13 2022-11-08 Alibaba Group Holding Limited System method for facilitating memory media as file storage device based on real-time hashing by performing integrity check with a cyclical redundancy check (CRC)
US11218165B2 (en) 2020-05-15 2022-01-04 Alibaba Group Holding Limited Memory-mapped two-dimensional error correction code for multi-bit error tolerance in DRAM
US11556277B2 (en) 2020-05-19 2023-01-17 Alibaba Group Holding Limited System and method for facilitating improved performance in ordering key-value storage with input/output stack simplification
US11507499B2 (en) 2020-05-19 2022-11-22 Alibaba Group Holding Limited System and method for facilitating mitigation of read/write amplification in data compression
US11263132B2 (en) 2020-06-11 2022-03-01 Alibaba Group Holding Limited Method and system for facilitating log-structure data organization
US11422931B2 (en) 2020-06-17 2022-08-23 Alibaba Group Holding Limited Method and system for facilitating a physically isolated storage unit for multi-tenancy virtualization
US11354200B2 (en) 2020-06-17 2022-06-07 Alibaba Group Holding Limited Method and system for facilitating data recovery and version rollback in a storage device
US11354233B2 (en) 2020-07-27 2022-06-07 Alibaba Group Holding Limited Method and system for facilitating fast crash recovery in a storage device
US11372774B2 (en) 2020-08-24 2022-06-28 Alibaba Group Holding Limited Method and system for a solid state drive with on-chip memory integration
US11487465B2 (en) 2020-12-11 2022-11-01 Alibaba Group Holding Limited Method and system for a local storage engine collaborating with a solid state drive controller
US11734115B2 (en) 2020-12-28 2023-08-22 Alibaba Group Holding Limited Method and system for facilitating write latency reduction in a queue depth of one scenario
US11416365B2 (en) 2020-12-30 2022-08-16 Alibaba Group Holding Limited Method and system for open NAND block detection and correction in an open-channel SSD
US11726699B2 (en) 2021-03-30 2023-08-15 Alibaba Singapore Holding Private Limited Method and system for facilitating multi-stream sequential read performance improvement with reduced read amplification
US11461173B1 (en) 2021-04-21 2022-10-04 Alibaba Singapore Holding Private Limited Method and system for facilitating efficient data compression based on error correction code and reorganization of data placement
US11476874B1 (en) 2021-05-14 2022-10-18 Alibaba Singapore Holding Private Limited Method and system for facilitating a storage server with hybrid memory for journaling and data storage
CN117242326A (zh) * 2021-06-25 2023-12-15 华为技术有限公司 一种交换芯片及供电方法
CN113555372B (zh) * 2021-06-30 2022-06-07 广芯微电子(广州)股份有限公司 一种隔断填充单元及多电压域低功耗芯片
US20230015697A1 (en) * 2021-07-13 2023-01-19 Citrix Systems, Inc. Application programming interface (api) authorization
US11573624B1 (en) * 2022-06-08 2023-02-07 Ambiq Micro, Inc. System for providing power to low power systems
KR102643032B1 (ko) * 2023-09-19 2024-03-04 주식회사 잇다반도체 전력 제어 시스템 및 이를 포함한 시스템 온 칩 장치

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1353454A (zh) * 2000-11-15 2002-06-12 国际商业机器公司 半导体芯片设计方法
US6523150B1 (en) * 2001-09-28 2003-02-18 International Business Machines Corporation Method of designing a voltage partitioned wirebond package

Family Cites Families (82)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63104443A (ja) * 1986-10-22 1988-05-09 Hitachi Ltd 大規模集積回路
US5440749A (en) * 1989-08-03 1995-08-08 Nanotronics Corporation High performance, low cost microprocessor architecture
JP3082103B2 (ja) * 1991-08-08 2000-08-28 富士通株式会社 プロセッサ
EP0632360A1 (en) 1993-06-29 1995-01-04 Xerox Corporation Reducing computer power consumption by dynamic voltage and frequency variation
JPH07105174A (ja) 1993-10-07 1995-04-21 Hitachi Ltd 1チップマイクロコンピュータ
US5918061A (en) 1993-12-29 1999-06-29 Intel Corporation Enhanced power managing unit (PMU) in a multiprocessor chip
WO1996025796A1 (en) 1995-02-17 1996-08-22 Intel Corporation Power dissipation control system for vlsi chips
US5640573A (en) 1994-02-02 1997-06-17 Advanced Micro Devices, Inc. Power management message bus for integrated processor
JP3718251B2 (ja) * 1994-02-28 2005-11-24 株式会社ルネサステクノロジ データ処理装置
US5778237A (en) 1995-01-10 1998-07-07 Hitachi, Ltd. Data processor and single-chip microcomputer with changing clock frequency and operating voltage
EP0809825A1 (en) * 1995-02-14 1997-12-03 Vlsi Technology, Inc. Method and apparatus for reducing power consumption in digital electronic circuits
JPH08234861A (ja) * 1995-02-28 1996-09-13 Fujitsu Ltd 低消費電力プロセッサ
US5719800A (en) 1995-06-30 1998-02-17 Intel Corporation Performance throttling to reduce IC power consumption
US5996083A (en) 1995-08-11 1999-11-30 Hewlett-Packard Company Microprocessor having software controllable power consumption
KR100468561B1 (ko) * 1996-01-17 2005-06-21 텍사스 인스트루먼츠 인코포레이티드 중앙처리장치의동작특성에따라컴퓨터의동작을제어하는방법및시스템
US6076141A (en) 1996-01-24 2000-06-13 Sun Microsytems, Inc. Look-up switch accelerator and method of operating same
US5940785A (en) * 1996-04-29 1999-08-17 International Business Machines Corporation Performance-temperature optimization by cooperatively varying the voltage and frequency of a circuit
US5887179A (en) * 1996-06-11 1999-03-23 Motorola, Inc. System power saving means and method
US6785826B1 (en) 1996-07-17 2004-08-31 International Business Machines Corporation Self power audit and control circuitry for microprocessor functional units
JPH10222253A (ja) * 1997-02-07 1998-08-21 Hitachi Ltd 情報処理システム
US6462976B1 (en) * 1997-02-21 2002-10-08 University Of Arkansas Conversion of electrical energy from one form to another, and its management through multichip module structures
US6115823A (en) * 1997-06-17 2000-09-05 Amphus, Inc. System and method for task performance based dynamic distributed power management in a computer system and design method therefor
US6411156B1 (en) 1997-06-20 2002-06-25 Intel Corporation Employing transistor body bias in controlling chip parameters
JP3524337B2 (ja) 1997-07-25 2004-05-10 キヤノン株式会社 バス管理装置及びそれを有する複合機器の制御装置
JP3150082B2 (ja) * 1997-08-08 2001-03-26 日本電気株式会社 高速伝送対応コネクタ
US6219796B1 (en) * 1997-12-23 2001-04-17 Texas Instruments Incorporated Power reduction for processors by software control of functional units
KR100321976B1 (ko) 1997-12-29 2002-05-13 윤종용 인텔프로세서를위한오류허용전압조절모듈회로
JP3573957B2 (ja) * 1998-05-20 2004-10-06 インターナショナル・ビジネス・マシーンズ・コーポレーション コンピュータ内のプロセッサの動作速度制御方法及びコンピュータ
WO2000002118A1 (en) 1998-07-02 2000-01-13 Hitachi, Ltd. Microprocessor
US6141762A (en) 1998-08-03 2000-10-31 Nicol; Christopher J. Power reduction in a multiprocessor digital signal processor based on processor load
DE69909924T2 (de) * 1998-09-09 2004-03-11 Texas Instruments Inc., Dallas Verfahren und Vorrichtung zur Reduzierung der Verlustleistung in einer Schaltung
US6496729B2 (en) 1998-10-28 2002-12-17 Medtronic, Inc. Power consumption reduction in medical devices employing multiple supply voltages and clock frequency control
US6415388B1 (en) 1998-10-30 2002-07-02 Intel Corporation Method and apparatus for power throttling in a microprocessor using a closed loop feedback system
US6484265B2 (en) 1998-12-30 2002-11-19 Intel Corporation Software control of transistor body bias in controlling chip parameters
US6345362B1 (en) 1999-04-06 2002-02-05 International Business Machines Corporation Managing Vt for reduced power using a status table
US6477654B1 (en) 1999-04-06 2002-11-05 International Business Machines Corporation Managing VT for reduced power using power setting commands in the instruction stream
US6166985A (en) 1999-04-30 2000-12-26 Intel Corporation Integrated circuit low leakage power circuitry for use with an advanced CMOS process
AU4290999A (en) * 1999-06-29 2001-01-31 Hitachi Limited System lsi
JP2001238190A (ja) * 2000-02-25 2001-08-31 Canon Inc 画像処理装置及びその制御処理方法
JP2001306196A (ja) * 2000-04-26 2001-11-02 Matsushita Electric Ind Co Ltd 画像処理集積回路及び画像通信装置及び画像通信方法
JP3878431B2 (ja) * 2000-06-16 2007-02-07 株式会社ルネサステクノロジ 半導体集積回路装置
EP1182552A3 (en) 2000-08-21 2003-10-01 Texas Instruments France Dynamic hardware configuration for energy management systems using task attributes
US6664775B1 (en) 2000-08-21 2003-12-16 Intel Corporation Apparatus having adjustable operational modes and method therefore
EP1182548A3 (en) 2000-08-21 2003-10-15 Texas Instruments France Dynamic hardware control for energy management systems using task attributes
US6968467B2 (en) * 2000-10-26 2005-11-22 Matsushita Electric Industrial Co., Ltd. Decentralized power management system for integrated circuit using local power management units that generate control signals based on common data
JP4181317B2 (ja) 2000-10-26 2008-11-12 松下電器産業株式会社 集積回路の電力管理システム
JP2002182776A (ja) 2000-12-18 2002-06-26 Kenwood Corp 動作周波数制御システム及び動作周波数制御方法
US20020087904A1 (en) * 2000-12-28 2002-07-04 Zhong-Ning (George) Cai Method and apparatus for thermal sensitivity based dynamic power control
JP3884914B2 (ja) 2001-01-30 2007-02-21 株式会社ルネサステクノロジ 半導体装置
US20020112193A1 (en) * 2001-02-09 2002-08-15 International Business Machines Corporation Power control of a processor using hardware structures controlled by a compiler with an accumulated instruction profile
JP3888070B2 (ja) * 2001-02-23 2007-02-28 株式会社ルネサステクノロジ 消費電力制御インタフェースを有する論理回路モジュール及び該モジュールを記憶した記憶媒体
US6895520B1 (en) 2001-03-02 2005-05-17 Advanced Micro Devices, Inc. Performance and power optimization via block oriented performance measurement and control
US6509788B2 (en) * 2001-03-16 2003-01-21 Hewlett-Packard Company System and method utilizing on-chip voltage controlled frequency modulation to manage power consumption
US6535735B2 (en) * 2001-03-22 2003-03-18 Skyworks Solutions, Inc. Critical path adaptive power control
US6836849B2 (en) * 2001-04-05 2004-12-28 International Business Machines Corporation Method and apparatus for controlling power and performance in a multiprocessing system according to customer level operational requirements
US7058834B2 (en) 2001-04-26 2006-06-06 Paul Richard Woods Scan-based state save and restore method and system for inactive state power reduction
US7254721B1 (en) 2001-05-01 2007-08-07 Advanced Micro Devices, Inc. System and method for controlling an intergrated circuit to enter a predetermined performance state by skipping all intermediate states based on the determined utilization of the intergrated circuit
JP2002366351A (ja) 2001-06-06 2002-12-20 Nec Corp スーパースカラ・プロセッサ
EP1421588B1 (en) * 2001-08-29 2012-01-18 MediaTek Inc. Method and apparatus utilizing flash burst mode to improve processor performance
JP2003086693A (ja) * 2001-09-12 2003-03-20 Nec Corp 半導体集積回路
JP4974202B2 (ja) * 2001-09-19 2012-07-11 ルネサスエレクトロニクス株式会社 半導体集積回路
JP2003099148A (ja) * 2001-09-19 2003-04-04 Sanyo Electric Co Ltd データ処理装置とこれに利用可能なシステム制御装置およびデータ変換方法
JP4050027B2 (ja) 2001-09-28 2008-02-20 株式会社日立製作所 情報処理装置及び情報処理装置の制御方法
US7111178B2 (en) * 2001-09-28 2006-09-19 Intel Corporation Method and apparatus for adjusting the voltage and frequency to minimize power dissipation in a multiprocessor system
US7111179B1 (en) * 2001-10-11 2006-09-19 In-Hand Electronics, Inc. Method and apparatus for optimizing performance and battery life of electronic devices based on system and application parameters
US6631502B2 (en) * 2002-01-16 2003-10-07 International Business Machines Corporation Method of analyzing integrated circuit power distribution in chips containing voltage islands
US6976182B1 (en) 2002-02-01 2005-12-13 Advanced Micro Devices, Inc. Apparatus and method for decreasing power consumption in an integrated circuit
US6667648B2 (en) * 2002-04-23 2003-12-23 International Business Machines Corporation Voltage island communications circuits
US6779169B1 (en) * 2002-05-31 2004-08-17 Altera Corporation Method and apparatus for placement of components onto programmable logic devices
US6908227B2 (en) 2002-08-23 2005-06-21 Intel Corporation Apparatus for thermal management of multiple core microprocessors
US6779163B2 (en) * 2002-09-25 2004-08-17 International Business Machines Corporation Voltage island design planning
US6820240B2 (en) * 2002-09-25 2004-11-16 International Business Machines Corporation Voltage island chip implementation
US6711447B1 (en) 2003-01-22 2004-03-23 Intel Corporation Modulating CPU frequency and voltage in a multi-core CPU architecture
US7085945B2 (en) 2003-01-24 2006-08-01 Intel Corporation Using multiple thermal points to enable component level power and thermal management
CN100416573C (zh) * 2003-05-07 2008-09-03 睦塞德技术公司 利用电源岛管理集成电路上的功率
WO2005024910A2 (en) * 2003-09-09 2005-03-17 Robert Eisenstadt Apparatus and method for integrated circuit power management
EP1759460B1 (en) * 2004-06-15 2012-08-01 ST-Ericsson SA Adaptive control of power supply for integrated circuits
US7279956B2 (en) * 2004-07-09 2007-10-09 Mosaid Technologies Incorporated Systems and methods for minimizing static leakage of an integrated circuit
US7382178B2 (en) * 2004-07-09 2008-06-03 Mosaid Technologies Corporation Systems and methods for minimizing static leakage of an integrated circuit
US7996814B1 (en) * 2004-12-21 2011-08-09 Zenprise, Inc. Application model for automated management of software application deployments
US8015426B2 (en) * 2008-03-27 2011-09-06 International Business Machines Corporation System and method for providing voltage power gating
US8390249B2 (en) * 2009-11-30 2013-03-05 Broadcom Corporation Battery with integrated wireless power receiver and/or RFID

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1353454A (zh) * 2000-11-15 2002-06-12 国际商业机器公司 半导体芯片设计方法
US6523150B1 (en) * 2001-09-28 2003-02-18 International Business Machines Corporation Method of designing a voltage partitioned wirebond package

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Managing Power and Performance for System-on-ChipDesign using Voltage Island. David E.Lackey,Paul S.Zuchowski,ThomasR.Bednar,Douglas W.Stout,Scott W.Gould,John M.Cohn.IEEE International Conference on Computer Aided Desig. 2002
Managing Power and Performance for System-on-ChipDesign using Voltage Island. David E.Lackey,Paul S.Zuchowski,ThomasR.Bednar,Douglas W.Stout,Scott W.Gould,John M.Cohn.IEEE International Conference on Computer Aided Desig. 2002 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101840446B (zh) * 2009-01-30 2016-01-27 技领半导体(上海)有限公司 从模拟拼片传输配置信息到另一拼片的方法

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