CN100431105C - Self-aligning metal silicide technology - Google Patents
Self-aligning metal silicide technology Download PDFInfo
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- CN100431105C CN100431105C CNB2005101069397A CN200510106939A CN100431105C CN 100431105 C CN100431105 C CN 100431105C CN B2005101069397 A CNB2005101069397 A CN B2005101069397A CN 200510106939 A CN200510106939 A CN 200510106939A CN 100431105 C CN100431105 C CN 100431105C
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Abstract
The technique of self-aligned metal silicides (salicide) includes following steps: first providing a surface of containing at least a substrate of a silicon conductive layer; next, carrying out a degas step for the said substrate, and a cooling step for the substrate; then, depositing a metal layer on surface of the substrate, and the metal layer is contacted to the surface of the silicon conductive layer; carrying out a heat treatment in order to form a silicate metal layer on surface of the silicon conductive layer of contacting with the metal layer; finally, removing unreacted the metal layer.
Description
Technical field
The present invention relates to a kind of semiconductor element technology, relate in particular to the method for a kind of making self-aligned metal silicate (salicide).
Background technology
In the technology of semiconductor integrated circuit, metal-oxide semiconductor (MOS) (metal-oxide-semiconductor, MOS) transistor is a kind of epochmaking electronic component, and along with the size of semiconductor element is more and more littler, the processing step of MOS transistor also has many improvement, to produce the little and high-quality MOS transistor of volume.
Existing MOS transistor technology is to form on Semiconductor substrate after the grid structure, in the substrate of the relative both sides of grid structure, form again ldd structure (lightly doped drain, LDD).Then form sidewall (spacer) in the grid structure side, and with this grid structure and sidewall as mask, carry out the ion implantation step, in Semiconductor substrate, to form source/drain regions.And for transistorized grid, source electrode and drain electrode suitably will being electrically connected in the circuit, therefore needing to form contact plunger (contactplug) and carry out conducting.Usually the material of contact plunger is metallic conductors such as tungsten (W), copper, and so the direct conducting between the materials such as polycrystalline such as itself and grid structure, source/drain regions or monocrystalline silicon is unsatisfactory; Therefore in order to improve the ohmic contact (Ohmicontact) between metal plug and grid structure, the source/drain regions, can form a metal silicide (silicide) again on the surface of grid structure, source/drain regions usually.
Be mostly at present utilize self-aligned metal silicate (self-aligned silicide, salicide) technology forms metal silicide; That is after forming source/drain regions, form a cobalt (Co), titanium (Ti), nickel metal levels such as (Ni) again and be covered in source/drain regions and grid structure top, carry out annealing (RTA) technology that is rapidly heated then and make pasc reaction in metal level and grid structure, the source/drain regions, form the sheet resistance (sheet resistance) that metal silicide reduces source/drain regions.
Yet, form metal silicide in this mode and also can produce some problems, be exactly when forming metal silicide, metallic atom in the metal level can diffuse in the silicon substrate and the silicon that consumes in the source/drain regions is finished, not only the lattice structure in the script source/drain regions can be destroyed, even can cause the PN junction between source/drain regions and the silicon substrate and the hypotelorism of metal silicide interlayer to react with the silicon in the source/drain regions, and the part-structure of destruction part source/drain regions, especially at super shallow junction (ultra shallow junction, USJ) in the design, even can cause metal silicide directly to contact, and then cause the situation of component failure with substrate.
Please refer to Fig. 1, Fig. 1 and Fig. 2 are the existing process schematic representation of making self-aligned metal silicate.As shown in Figure 1, at first on substrate 60, form after the grid structure 66 that is constituted by gate dielectric 62 and grid 64, then carry out an ion implantation step, in substrate 60, to form ldd structure 70.Sidewall in grid structure 66 forms laying 67 and sidewall 68 subsequently, and carries out another ion implantation step, to form regions and source 72 in the substrate 60 of sidewall 68 both sides.Carry out a wet-cleaned technology then, removing the impure particle or the native oxide on grid structure 66 and regions and source 72 surfaces, and carry out one and remove aqueous vapor (degas) step and remove because of the formed unnecessary aqueous vapor of wet-cleaned technology.Subsequently, in substrate 60 surperficial sputter one metal levels 74, a nickel metal layer for example, and cover grid 64, sidewall 68 and substrate 60 surfaces.As shown in Figure 2, then carry out one and be rapidly heated that (rapid thermal anneal RTA), makes metal level 74 become metal silicide layer 76 with the partial reaction that grid 64 and regions and source 72 contact to annealing process.Utilize a selectivity Wet-type etching at last again, for example with NH
4OH/H
2O
2/ H
2O or H
2SO
4/ H
2O
2Mixed solution remove the metal level 74 that unreacted becomes metal silicide.
As mentioned above, the MOS short-channel effect (short channel effects) of being derived after dwindling because of the increase of element integrated level for fear of transistorized design, and improve the intraconnections resistance value (interconnect resistance) of integrated circuit, therefore must dwindle the junction depth (junction depth) of transistorized source electrode and drain electrode and make the transistor that contains metal silicide.Yet when the junction depth of source electrode and drain electrode dwindles, if the thickness of the metal silicide in thinning source electrode and the drain electrode then may cause too high intraconnections resistance value (interconnect resistance) and contact resistance (contact resistance); But, then may cause the hypotelorism of 76 of PN junction between source/drain regions 72 and the silicon substrate 60 and metal silicide layers and make MOS transistor bring out junction leakage (junction leakage) if keep metal silicide in source electrode and the drain electrode at certain thickness.And the employed solvent of wet-cleaned technology before carrying out the metal silicide reaction also can cause erosion to the laying between grid and sidewall, make follow-up metal silicide when reaction of carrying out, metal silicide is easier of channel region, and produces what is called " nickle silicide conducting (nickel silicide piping) effect ".
In addition, the thermal stability (thermal stability) of the metal silicide of part is not good, even before the annealing in process that also is rapidly heated, the first plated film (as-deposition) that forms in metal sputtering technology at the beginning also can be owing to the technological temperature of the PVD reative cell that produces plasma is higher, or because metal deposition before the rapid high-temperature of the jia bombardier that dewaters and form the metal silicide that is polycrystalline shape (polycrystalline) structure, that is when temperature when too high or high-temperature process time is long slightly, the phenomenon of agglomerateization (agglomeration) will take place in metal silicide, become the dough that a piece does not link, cause the rising of sheet resistance (sheet resistance), even in follow-up high-temperature technology, change, consume too much silicon, and on shallow junction, cause the phenomenon of point prominent (spiking) or form the structure of high resistivity (resistivity), for example the nickle silicide of low-resistivity (NiSi) kenel (can be transformed into the nickel disilicide (NiSi of high resistivity approximately less than 20 μ Ω-cm)
2) kenel (about 50 μ Ω-cm).
Summary of the invention
Therefore main purpose of the present invention is to provide a kind of self-aligned metal silicate technology of improvement, to solve the problem of above-mentioned existing skill.
According to the present invention, disclosed a kind of self-aligned metal silicate (salicide) technology.At first provide a substrate, and this substrate surface comprises at least one silicon conducting layer, then this substrate is carried out one and remove aqueous vapor (degas) step, and this substrate is carried out a cooling step; Then deposit a metal level in this substrate surface, and this metal level contacts with this silicon conducting layer surface, carry out a thermal process then, form a metal silicide layer, remove unreacted this metal level at last so that contact this silicon conducting layer surface of this metal level.
According to the present invention, also disclose a kind of self-aligned metal silicate technology.At first provide a substrate, and this substrate surface comprises at least one silicon conducting layer, carry out one first low temperature depositing step then, forming a metal level in this substrate surface, and this metal level contacts with this silicon conducting layer surface; Then carry out one second low temperature depositing step,, carry out the annealing process (RTA) that is rapidly heated then, form a metal silicide layer so that contact this silicon conducting layer surface of this metal level to form a covering layer in this layer on surface of metal.Remove unreacted this metal level and this covering layer at last.
The present invention mainly provides a kind of new technology to lower heat budget, and when forming self-aligned metal silicate in substrate, promote the stability of this self-aligned metal silicate technology on heat budget, the too high or long slightly agglomerate phenomenon that takes place of high-temperature process time causes the sheet resistance rising because of temperature except lowering existing metal silicide, and can improve simultaneously follow-uply because of changing in the high-temperature technology, consume too much silicon and on shallow junction, cause point to appear suddenly to resemble or nickle silicide (NiSi) kenel of low-resistivity can be transformed into the nickel disilicide (NiSi of high resistivity
2) problem of kenel.
Description of drawings
Fig. 1 and Fig. 2 are the existing process schematic representation of making self-aligned metal silicate;
Fig. 3 to Fig. 5 is the process schematic representation of self-aligned metal silicate process application of the present invention in MOS transistor;
Fig. 6 makes a schematic flow sheet with transistor unit of metal silicide for the present invention.
The main element symbol description
60 substrates, 62 gate dielectrics
64 grids, 66 grid structures
67 layings, 68 sidewall
70 ldd structures, 72 regions and source
74 metal levels, 76 metal silicide layers
100 substrates, 102 gate dielectrics
104 grids, 106 grid structures
107 layings, 108 sidewall
110 ldd structures, 112 regions and source
114 metal levels, 116 covering layers
118 metal silicide layers
161～164: flow and method
Embodiment
Please refer to Fig. 3 to Fig. 5, Fig. 3 to Fig. 5 is the process schematic representation of self-aligned metal silicate process application of the present invention in MOS transistor.As shown in Figure 3, at first provide a substrate 100, for example a wafer (wafer) or silicon-coated insulated (SOI) substrate, and substrate 100 surfaces have at least one silicon conducting layer of being made up of monocrystalline silicon, polysilicon or epitaxial silicon (not shown).Wherein, this silicon conducting layer can include structures such as grid, regions and source, word line or resistance at different product demand and technological design, is that the grid structure 102 with MOS transistor describes with regions and source 112 in the preferred embodiment of Fig. 3 to Fig. 5 of the present invention.As shown in Figure 3, grid structure 102 includes gate dielectric 102 and grid 104, and gate dielectric 102 is made of dielectric materials such as silicon dioxide, and grid 104 is made of doped polycrystalline silicon electric conducting materials such as (doped polysilicon).
Carry out a light dope ion implantation technology subsequently, utilize grid 104, in substrate 100, to form source/drain elongated area 110 as in a mask and the substrate 100 with light dope matter (not shown) injector grid 104 relative both sides.Then sidewall forms a laying 107 around grid structure 106, and a silica layer for example forms sidewall 108 of being made up of the nitrogen silicon compound then again on laying 107.Then carry out a heavy doping ion injection technology, utilize grid 104 and sidewall 108 to inject in the substrate 100, in substrate 100, to form the higher regions and source 112 of a doping content as a mask and with a heavily doped impurity (not shown).And then carry out a high annealing (thermal annealing) technology, utilize 1000 to 1050 ℃ high temperature to activate doping in the substrate 100, and repair the lattice structure on substrate impaired in each ion implantation technology 100 surfaces simultaneously.
Then carry out a wet-cleaned step (wet cleaning step), residue in the native oxide (native oxide) and other foreign bodys on grid 104 tops and regions and source 112 surfaces in order to removing.Then after substrate 100 is inserted a physical vapor deposition (PVD) reative cell, utilize 100 ℃ to 400 ℃ temperature that substrate 100 is carried out one except that aqueous vapor (degas) step immediately, in order to remove wet-cleaned step remnants in the unnecessary aqueous vapor in substrate 100 surfaces.Then carry out a cooling step again, for example utilize an inert gas or wafer cooling device (wafer cooling chiller) to contact with substrate 100, in order to cooling substrate 100 to one predetermined temperatures, for example below 50 ℃, and preferred predetermined temperature of the present invention is a room temperature.
Then utilize the mode of original position (in-situ) deposition, technological temperature in the control PVD reative cell is below 150 ℃, with one metal level 114 of sputter on substrate 100, and be covered in grid structure 106, sidewall 108 and regions and source 112 surfaces, as shown in Figure 3.Wherein, metal level 114 is the alloys that are selected from tungsten, cobalt, titanium, nickel, platinum, palladium, molybdenum etc. or above-mentioned metal.In addition; because the metal silicide of part is after forming, NiSi for example, regular meeting causes great junction leakage; therefore the recycling covering layer of the present invention oxygen atom avoiding being rapidly heated in annealing (RTA) technology diffuses into, and improvement is at the material stress of element separation area edge.As shown in Figure 4, the technological temperature that continues to keep in this PVD reative cell is lower than 150 ℃, and deposit a covering layer 116 of forming by titanium or titanium nitride simultaneously in metal level 114 surfaces, utilizing covering layer 116 to suppress the oxygen content of the follow-up metal level 114 during annealing process of being rapidly heated, and then improve leakage current characteristic.
As shown in Figure 5, then carry out the annealing process (RTA) that is rapidly heated, the mode that can utilize original position (in-situ) to heat up equally is heated to about 200～400 degree with substrate 100.When carrying out heating steps, metal silicide layer 118 will be reacted and form in any grid 104 and regions and source 112 surfaces that touched with metal level 114.Then after the annealing in process that is rapidly heated, utilize typical wet etching chemical solution again, for example mixed solution such as ammoniacal liquor, hydrogen peroxide, hydrochloric acid, sulfuric acid, nitric acid and acetic acid are carried out an etching step, in order to remove unreacted metal layer 114 and covering layer 116.
Because the present invention will place the substrate 100 of PVD reative cell, finish 100 ℃ to 400 ℃ remove after aqueous vapor (degas) step, just earlier substrate 100 is carried out a step that is cooled to room temperature, the technological temperature of keeping this reative cell then is lower than under 150 ℃ the condition, deposit the covering layer 116 that a metal level 114 of being made up of atoms such as nickel and titanium or titanium nitride are formed in regular turn, so can reduce first plated film (as-deposition) forms agglomerateization (agglomeration) and sheet resistance (sheet resistance) rising in metal sputtering and deposition step phenomenon in a large number, and then lower the situation that sharp dash forward (spiking) takes place on the shallow junction.In addition, the present invention is removing aqueous vapor (degas) cooling step and low temperature sputtering process afterwards, more can effectively improve having in carrying out metal deposition process the too high and problem of living leakage current that causes binding up one's hair of Yin Wendu now, and reduce the puncture (spiking) of self-aligned metal silicate and the generation of conducting effects such as (piping) simultaneously.
Comprehensive above-mentioned explanation please refer to Fig. 6, and Fig. 6 makes a schematic flow sheet with transistor unit of metal silicide for the present invention.As shown in Figure 6, self-aligned metal silicate of the present invention (salicide) technology can be sketched and be the following step: at first a silicon wafer substrate is placed a process reaction chamber, the process reaction chamber of a physical vapor deposition (PVD) for example, rapid 161 to carry out the jia bombardier that dewaters, wherein the temperature of this process reaction chamber is between 100 ℃ to 400 ℃.Then carry out a cooling step 162, in order to cool off this silicon wafer substrate to one predetermined temperature, for example below 50 ℃, and this preferred predetermined temperature is room temperature, uses and reduces the chip temperature that dewaters jia bombardier rapid 161 and raise.Control the indoor temperature of technological reaction then in below 150 ℃, and carry out a metal sputtering step 163, on this silicon wafer substrate, to form a metal level, for example nickel or nickel alloy metal level.At last, keep equally under the environment that the indoor temperature of technological reaction is lower than 150 ℃, carry out a deposition step 164, in order to form a cap layer of forming by titanium or titanium nitride on nickel metal layer.
Than existing method of making self-aligned silicide, the present invention mainly provides a kind of new technology to lower heat budget, and when forming self-aligned metal silicate in substrate, promote the stability of this self-aligned metal silicate technology on heat budget, the too high or long slightly agglomerate phenomenon that takes place of high-temperature process time causes the sheet resistance rising because of temperature except lowering existing metal silicide, and can improve simultaneously follow-uply because of changing in the high-temperature technology, consume too much silicon and on shallow junction, cause point to appear suddenly to resemble or nickle silicide (NiSi) kenel of low-resistivity can be transformed into the nickel disilicide (NiSi of high resistivity
2) problem of kenel.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (22)
1. a self-aligned metal silicate technology comprises the following steps:
Provide a substrate, and this substrate surface comprises at least one silicon conducting layer;
It is rapid under first temperature this substrate to be carried out the jia bombardier that dewaters;
After this jia bombardier that dewaters is rapid, under second temperature, this substrate is carried out a cooling step, and this second temperature is lower than this first temperature;
After this cooling step, in this substrate surface, and this metal level contacts with this silicon conducting layer surface at the 3rd temperature deposit one metal level, and this second temperature is lower than the 3rd temperature;
Carry out a thermal process, form a metal silicide layer so that contact this silicon conducting layer surface of this metal level; And
Remove unreacted this metal level.
2. self-aligned metal silicate technology as claimed in claim 1, wherein this substrate comprises wafer or silicon-coated insulated substrate.
3. self-aligned metal silicate technology as claimed in claim 1, wherein the composition of this silicon conducting layer comprises monocrystalline silicon, polysilicon or epitaxial silicon, is used for forming grid structure, regions and source, word line or resistance.
4. self-aligned metal silicate technology as claimed in claim 3, wherein this grid structure comprises that also a gate dielectric, a polysilicon gate and at least one sidewall are arranged at the sidewall on every side of this polysilicon gate.
5. self-aligned metal silicate technology as claimed in claim 1, wherein the rapid temperature of this jia bombardier that dewaters is between 100 ℃ to 400 ℃.
6. self-aligned metal silicate technology as claimed in claim 1, wherein this cooling step is to be used for cooling off finishing this rapid substrate to a predetermined temperature of this jia bombardier that dewaters.
7. self-aligned metal silicate technology as claimed in claim 6, wherein this predetermined temperature is to be lower than 50 ℃.
8. self-aligned metal silicate technology as claimed in claim 7, wherein the optimum temperature of this predetermined temperature is a room temperature.
9. self-aligned metal silicate technology as claimed in claim 1, wherein this metal level comprises the alloy of tungsten, cobalt, titanium, nickel, platinum, palladium, molybdenum or above-mentioned metal.
10. self-aligned metal silicate technology as claimed in claim 1 wherein after forming this metal level, also comprises the step that forms a covering layer, is used to form on this layer on surface of metal a covering layer.
11. self-aligned metal silicate technology as claimed in claim 10, wherein this covering layer comprises titanium or titanium nitride.
12. a self-aligned metal silicate technology comprises the following steps:
Provide a substrate, and this substrate surface comprises at least one silicon conducting layer;
This substrate is carried out a cleaning step;
It is rapid under first temperature this substrate to be carried out the jia bombardier that dewaters;
After this jia bombardier that dewaters is rapid, under second temperature, this substrate is carried out a cooling step, and this second temperature is lower than this first temperature;
After this cooling step, under the 3rd temperature, carry out one first low temperature depositing step, forming a metal level in this substrate surface, and this metal level contacts with this silicon conducting layer surface, and this second temperature is lower than the 3rd temperature;
Carry out one second low temperature depositing step, to form a covering layer in this layer on surface of metal;
Carry out the annealing process that is rapidly heated, form a metal silicide layer so that contact this silicon conducting layer surface of this metal level; And
Remove unreacted this metal level and this covering layer.
13. self-aligned metal silicate technology as claimed in claim 12, wherein this substrate comprises a wafer or silicon-coated insulated substrate.
14. self-aligned metal silicate technology as claimed in claim 12, wherein the composition of this silicon conducting layer comprises monocrystalline silicon, polysilicon or epitaxial silicon, is used for forming grid structure, regions and source, word line or resistance.
15. self-aligned metal silicate technology as claimed in claim 14, wherein this grid structure comprises that also a gate dielectric, a polysilicon gate and at least one sidewall are arranged at the sidewall on every side of this polysilicon gate.
16. self-aligned metal silicate technology as claimed in claim 12, wherein this metal level comprises the alloy of tungsten, cobalt, titanium, nickel, platinum, palladium, molybdenum or above-mentioned metal.
17. self-aligned metal silicate technology as claimed in claim 12, wherein the temperature of this first low temperature depositing step is to be less than or equal to 150 ℃.
18. self-aligned metal silicate technology as claimed in claim 12, wherein this covering layer comprises titanium or titanium nitride.
19. self-aligned metal silicate technology as claimed in claim 12, wherein the temperature of this second low temperature depositing step is to be less than or equal to 150 ℃.
20. self-aligned metal silicate technology as claimed in claim 12, wherein the rapid temperature of this jia bombardier that dewaters is between 100 ℃ to 400 ℃.
21. self-aligned metal silicate technology as claimed in claim 12, wherein the temperature of this cooling step is to be lower than 50 ℃, is used for cooling off finishing this rapid substrate to a predetermined temperature of this jia bombardier that dewaters.
22. self-aligned metal silicate technology as claimed in claim 21, wherein the optimum temperature of this predetermined temperature is a room temperature.
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| CN101140871B (en) * | 2006-09-04 | 2010-11-10 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of metallic silicide in semiconductor device |
| CN102176414A (en) * | 2011-03-15 | 2011-09-07 | 上海集成电路研发中心有限公司 | Preparation method of metal silicide |
| CN103515217A (en) * | 2012-06-26 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Formation method of metal silicide layer and formation method of NMOS transistor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030124843A1 (en) * | 2001-12-28 | 2003-07-03 | Keiichi Hashimoto | Forming method of silicide film |
| US6740585B2 (en) * | 2001-07-25 | 2004-05-25 | Applied Materials, Inc. | Barrier formation using novel sputter deposition method with PVD, CVD, or ALD |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6740585B2 (en) * | 2001-07-25 | 2004-05-25 | Applied Materials, Inc. | Barrier formation using novel sputter deposition method with PVD, CVD, or ALD |
| US20030124843A1 (en) * | 2001-12-28 | 2003-07-03 | Keiichi Hashimoto | Forming method of silicide film |
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