CN100433697C - Multi-channel high-speed data processor and processing method - Google Patents
Multi-channel high-speed data processor and processing method Download PDFInfo
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- CN100433697C CN100433697C CNB2006100407691A CN200610040769A CN100433697C CN 100433697 C CN100433697 C CN 100433697C CN B2006100407691 A CNB2006100407691 A CN B2006100407691A CN 200610040769 A CN200610040769 A CN 200610040769A CN 100433697 C CN100433697 C CN 100433697C
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Abstract
A method for processing multichannel high-speed data includes issuing read/write information and data information by network processor and obtaining said information by queue dispatch module, carrying out relevant write operation on buffer area by receiving module after it receives write command from queue dispatch module then sending processed data to frame calibration-sequence module and sending calibrated data to data buffer storage module, writing data in buffer area and outputting data by operating buffer area. The processor of multichannel high-speed data is also disclosed.
Description
Technical field
Present device is the high-speed data treatment facility in a kind of wireless network secure field, and it adopts field programmable gate array (FPGA) is basic platform, is a kind of multi-channel high-speed data treatment system.
Background technology
The application of business such as HRPD (high rate packet data), multi-medium data and Internet is promoting code division multiple access (CDMA) and is upgrading to CDMA20001X from IS-95.The 3GPP2 of International Standards Organization has formulated the relevant criterion of CDMA20001X packet data network, adopted IETF existing achievement on mobile IP technology, network is had provides the IP operation ability of the ability of IP access, the intercommunication ability with other IP networks, better roaming capacity and private network fast, and makes system that the 144Kbps of providing, 384Kbps and 2Mbps access rate and simple IP and mobile IP service function are provided.
In the CDMA20001X network, adopt end-to-end protocol (PPP) agreement between mobile station MS or cell phone and the packet data serving node (PDSN) as SDL.Wrap for the IP from the wide area network to the mobile node, packet data serving node can correspond to it a concrete end-to-end protocol and connect, by IP address of searching the purpose cell phone and the mapping relations that corresponding A10 connects, the IP bag is sent to the cell phone terminal; When receiving an IP bag for the home agent home agent (HA) of the mobile phone terminal of having registered from, packet data serving node can find corresponding R-P to be connected according to the IP address of HA and the IP address of mobile phone terminal, sends packet; For IP packet from cell phone, mobile phone terminal is encapsulated in it in the end-to-end protocol packet and sends to network, after wireless air interface and base station transmits, transmit to packet data serving node in generalized routing protocol (GRE) tunnel by Packet Control Function (PCF) parts of base station controller end-to-end protocol data encapsulation again portable terminal, packet data serving node by network side unpacks the tunnel encapsulation packet then, re-assembly the IP backbone that is routed to network side after the processing, or send to its home agent HA place by reverse tunnel.
The mobile Internet content monitoring equipment of processor Network Based is when the information of interception, filtration and analysis CDMA packet data domain, high speed data link control protocol (HDLC) frame of end-to-end protocol need be linked to be a complete packet, at this moment need escape of high speed data link control protocol Frame or counter-rotating justice are recovered original data.If but this work transfers to network processing unit and finishes, will strengthen the expense of system, greatly influence the performance of system.
Summary of the invention
Technical problem: the purpose of this invention is to provide a kind of multi-channel high-speed data treatment system, we have designed the multi-channel high-speed data treatment system and have come secondary master work, thereby the high-speed real-time of realizing mobile Internet content supervision data is handled, and reduces the burden of main frame, raises the efficiency.
Technical scheme: the present invention adopts the mode that adds the field programmable gate array coprocessor to finish multi-path asynchronous high speed data link control protocol processing capacity, and by 4 haplotype data speed (QDR) interface and main-machine communications, the a few thing of former cause software processes is finished by hardware, reduce the burden of main frame, raise the efficiency.
Along with the development of microelectric technique, Field Programmable Gate Array has obtained develop rapidly, because this device has that operating rate is fast, integrated level is high and characteristics such as field-programmable, thereby has obtained using widely in Digital Signal Processing.The present invention is based on the basic principle of high speed data link control protocol, finished design of the present invention at the field programmable gate array chip Spartan of Xil inx company family device (XC3S2000-4FG676C).High speed data link control protocol is an agreement towards the position, supports half-duplex and full-duplex communication, and it is widely used and data communication field, is the technology of other many data link control protocols.It has the characteristics of very strong mistake error detection, efficient and synchronous transmission.Present many network routing devices and switch all utilize high speed data link control protocol as its link protocol.
High-speed data processor of the present invention is mainly handled decapsulation and end-to-end protocol bag counter-rotating justice that the multipath high-speed data link control protocol frame from main frame walks abreast, at last the result is fed back main frame and carry out next step reorganization and protocol processes, thereby it is overweight to have alleviated burden of main machine, the pressure that overhead is excessive has guaranteed running up of whole mobile Internet supervisory control system.The multi-channel high-speed data treatment system that the present invention proposes, one side has been followed the international standard of IEEE, has realized basic function---the escape/counter-rotating justice and cyclic redundancy code effect (CRC) verification of high speed data link control protocol frame of standard code; Extendible, flexible excuse also is provided on the other hand,, processor has been expanded according to later actual needs; In addition, after this processor design finishes, can be by on software of now having developed or hardware, revising a little, this processor can be transform as other communication products, frame relay system for example, Integrated Service Digital Network(ISDN) (ISDN), X.25 data network, in the various data environment net environment such as backbone and edge router, so this high speed data link control protocol processor still has suitable application prospects.
The structure of present device is as follows:
The present invention comprises the field programmable gate array hardware module, 4 haplotype data rate interface modules, four parts such as programmable read only memory application configuration module and software system module.Wherein:
1, field programmable gate array hardware module
Adopt 2,000,000 field programmable gate arrays,, in this equipment, occupy core status as the coprocessor of main frame.Communicate by the LA_1 agreement between field programmable gate array and the 4 haplotype data rate interfaces.HSTL_1_DCI (1.5V) standard is followed in the output of I/O level, and extra 0.75V reference level need be provided for this reason.Field programmable gate array by and Flash programmable read only memory (FLASH PROM) between serial line interface accept configuration information, in addition, can also directly be configured and debug by jtag interface to field programmable gate array.After powering on, field programmable gate array is reading of data in programmable read-only memory (prom) voluntarily, can also reconfigure by reset signal in the time of in working order.
2,4 haplotype data rate interface modules
Connect mainboard and this equipment, for this equipment provide with main frame between communicate by letter and data interaction.In addition, all power supplies of this equipment are all provided by this interface.
(1) internal integrate circuit bus interface, interface obtains facility informations such as this device identifier, operation level and temperature by the internal integrated circuit E2PROM on internal integrated circuit (I2C) the bus access card, thereby discerns this equipment.
(2) 4 haplotype data rate interfaces, 16 bit data interface of this equipment frequency multiplication under doubleclocking drives becomes 32 of logics.Bus provides four times of fast input/output ports and the 24 bit address live widths that can work simultaneously.
(3) JTAG debugging interface, though comprise jtag interface in the LA_1 standard, but only limit to provide test interface (not supporting programming) to programmable read only memory and field programmable gate array, so in design, introduced the JTAG slot in addition, by the PC programmable read only memory that directly downloads.
(4) peripheral supply module, 4 haplotype data rate interfaces for this equipment provide+3.3V ,+1.8V and+the 1.5V direct voltage.In addition, all pass through+the local generation of 3.3V such as 2.5V, 1.2V, 0.75V voltage by this equipment.
3, programmable read only memory application configuration module
(1) internal integrate circuit bus programmable read only memory circuit, record coprocessor device information, comprise parameters such as device id, operation level and temperature, during system start-up, 4 haplotype data rate interfaces detect to discern this equipment it by internal integrate circuit bus.In addition, internal integrated circuit programmable read only memory itself is also supported password encryption and cryptoguard.
(2) Flash programmable read only memory circuit is configured field programmable gate array when powering on automatically, and its configuration mode divides the principal and subordinate two kinds of patterns, and its main distinction is the difference of configurable clock generator signal source.In the programmable gate array master mode, field programmable gate array provides the configurable clock generator signal for programmable read only memory at the scene, in the programmable gate array controlled mode, provides the configurable clock generator signal by external crystal-controlled oscillation at the scene.
4, software system module:
Software system module is realized the multi-channel data processing capacity of entire field programmable gate array.The mode that each driver module all adopts dynamic module to load is write.
Software system module has mainly comprised following several sections: the queue scheduling module receives data cache module, transmission data cache module, high speed data link control protocol packet counter-rotating justice and banner word thereof and handles mould, frame effect block.
Structurally, this processor specifically comprises four following modules: the field programmable gate array hardware module; 4 haplotype data rate interface modules; Programmable read only memory application configuration module and software system module; Described 4 haplotype data rate interface modules comprise: internal integrate circuit bus interface, 4 haplotype data rate interfaces, jtag interface and peripheral supply module; The field programmable gate array hardware module connects outside main frame, is connected with peripheral supply module and joins by the Flash programmable read only memory circuit in jtag interface and the programmable read only memory application configuration module by power line by 4 haplotype data rate interfaces, and Flash programmable read only memory circuit also joins by the PC of jtag interface and outside; Internal integrate circuit bus programmable read only memory circuit in the programmable read only memory application configuration module connects outside main frame by internal integrate circuit bus interface; Software system module, comprised: queue scheduling module, reception data cache module, transmission data cache module, high speed data link control protocol packet counter-rotating justice and banner word thereof are handled mould and Frame Check Sequence module, link together by the signal transmission between each module that software system module comprises; Software system module resides in the programmable read only memory application configuration module, after the multi-channel high-speed data processor work, program is loaded in the field programmable gate array hardware module, and the program of field programmable gate array hardware module by 4 haplotype data rate interface modules and main frame links together.
The field programmable gate array hardware module adopts the coprocessor of 2,000,000 " XC3S2000 " field programmable gate arrays as main frame.
In the 4 haplotype data rate interface modules, peripheral supply module has adopted " TPS75525 " voltage transitions chip when generating 2.5V voltage; When generating 1.2v voltage, adopted " TPS54312 " voltage transitions chip; When generating 0.75V voltage, adopt " MAX1589EZTAFJ " chip.
In the programmable read only memory application configuration module; adopt internal integrate circuit bus programmable read only memory circuit to write down the facility information of described processor; comprise device identifier, operation level and temperature parameter; main frame detects with the identification multi-channel high-speed data processor by internal integrate circuit bus programmable read only memory circuit, and internal integrate circuit bus programmable read only memory circuit itself is also supported password encryption and cryptoguard.In the programmable read only memory application configuration module, adopt Flash programmable read only memory circuit automatically the field programmable gate array hardware module to be configured when powering on, configuration mode has two kinds of master mode and controlled modes.
The high-speed data processing method of multi-channel high-speed data processor is: in the software system module, at first send reading writing information and data message by high-speed data processor, the queue scheduling module is obtained reading writing information and data message from network processing unit, after the reception data cache module is obtained corresponding write order from the queue scheduling module, the buffering area that receives data cache module is carried out corresponding write operation, so that high speed data link control protocol packet counter-rotating justice and banner word thereof are handled the processing of mould, control signal valid frame signal after the processing, escape signal and high-speed data processor dateout are imported the Frame Check Sequence module in the lump into, after verification, produce control signal and write buffering signals, the postamble signal, data after check errors signal and the verification, import the transmission data cache module into, send and after the data cache module integrated treatment is judged data data after the verification are write the buffering area that sends data cache module, in conjunction with the read message of queue scheduling module, export by the data after will handling the read operation of this buffering area.Software system module carries out the monitoring of frame head search, CRC, counter-rotating justice, the detection that abandons sequence, frame length and the search of postamble to the data of each passage, in case detecting the current information transmitted figure place of a certain frame reaches maximum frame length or detects when abandoning sequence, state machine in the software system module finishes the processing of present frame, and again a new frame is carried out the frame head search, and the remaining data in the present frame will be not processed.Software system module is handled the high speed data link control protocol data flow up to the transmission of 128 channel parallels simultaneously, its realization is to adopt time-multiplexed mode, wherein the channel status memory is used to realize time division multiplexing, each passage all has a fixing memory space among this channel status memory, in order to store the processing condition data of this passage, it is channel status information, be processed one segment length regular hour of the data allocations sheet of each each section of passage needs, when each timeslice finishes, when the up-to-date state information of prepass will be deposited in respective stored space in the channel status memory, when new one piece of data arrives, the state information that passage under this segment data is refreshed in a last timeslice will be read and be loaded into from the channel status memory in the state machine, for the data processing of a new round is prepared.
Beneficial effect: multi-channel high-speed data treatment facility of the present invention has reached the good function characteristic: the high speed data link control protocol function that has realized the RFC1662 regulation, banner word detection, escape/counter-rotating justice, frame effect sequence (FCS) function have been realized, the characteristics that have extensibility and flexibility simultaneously, convenient later upgrading expansion; Present device also receives and sending module realization multi-channel parallel processing high speed data link control protocol data by increasing, and has improved the efficient of processor; By the address bus of 4 haplotype data rate interfaces as the control signal utilization, realized that bus is multiplexing, improved total line use ratio.
The present invention mainly is based on the field programmable gate array of the high-speed data processing of mobile Internet content monitoring equipment high speed data link control protocol packet and realizes.The present invention is proposing new project organization and implementation method aspect the hardware realization; Escape/counter-rotating justice, the CRC function of high speed data link control protocol frame, the search and the removal thereof of frame head postamble on function, have been realized, especially crucial is by with the communicating by letter of main frame, realize the processing of end-to-end protocol bag when a plurality of users are simultaneously online, and reached the high speed processing ability of 200Mbps.On function, realized the high speed processing of end-to-end protocol bag in the mobile Internet content supervisory systems.
Description of drawings
Fig. 1 is based on the multi-channel high-speed data treatment facility structured flowchart of Field Programmable Gate Array;
Figure 24 haplotype data rate interface module 2 schematic diagrames;
Fig. 3 Flash programmable read only memory circuit 3.2 and field programmable gate array hardware module 1 connection layout;
Fig. 4 programmable read only memory application configuration module 3 configuration flow figure;
Fig. 5 software module connection layout;
The application state figure of Fig. 6 present device;
Fig. 7 single channel high-speed data processor state transition diagram.
Have among the above figure: field programmable gate array hardware module 1,4 haplotype data rate interface module 2, programmable read only memory application configuration module 3 and software system module 4; Internal integrate circuit bus interface 2.1,4 haplotype data rate interfaces 2.2, JTAG debugging interface 2.3, peripheral supply module 2.4; Internal integrate circuit bus programmable read only memory circuit 3.1 and Flash programmable read only memory circuit 3.2; Queue scheduling module 4.1 receives data cache module 4.2, transmission data cache module 4.3, high speed data link control protocol packet counter-rotating justice and banner word thereof and handles mould 4.4, frame effect block 4.5.
Embodiment
Below in conjunction with accompanying drawing, the structure and the flow process of each module of present device is elaborated.
Present device is a kind of multi-channel high-speed data treatment facility based on field programmable gate array.
System architecture of the present invention as shown in Figure 1 as can be known, this processor specifically comprises four following modules: field programmable gate array hardware module 1; 4 haplotype data rate interface modules 2; Programmable read only memory application configuration module 3 and software system module 4; Described 4 haplotype data rate interface modules 2 comprise: internal integrate circuit bus interface 2.1,4 haplotype data rate interfaces 2.2, jtag interface 2.3 and peripheral supply module 2.4; Field programmable gate array hardware module 1 connects outside main frame, is connected with peripheral supply module 2.4 and joins by jtag interface 2.3 and Flash programmable read only memory circuit 3.2 in the programmable read only memory application configuration module 3 by power line by 4 haplotype data rate interfaces 2.2, and Flash programmable read only memory circuit 3.2 also joins by the PC of jtag interface 2.3 and outside; Internal integrate circuit bus programmable read only memory circuit 3.1 in the programmable read only memory application configuration module 3 connects outside main frame by internal integrate circuit bus interface 2.1; Software system module 4, comprised: queue scheduling module 4.1, reception data cache module 4.2, transmission data cache module 4.3, high speed data link control protocol packet counter-rotating justice and banner word thereof are handled mould 4.4 and Frame Check Sequence module 4.5, link together by the signal transmission between each module that software system module 4 comprises; Software system module 4 resides in the programmable read only memory application configuration module 3, after the multi-channel high-speed data processor work, program is loaded in the field programmable gate array hardware module 1, and field programmable gate array hardware module 1 links together by the program of 4 haplotype data rate interface modules 2 with main frame.
2,000,000 Spartan3 XC3S2000 of processor adopting of the present invention field programmable gate array.Field programmable gate array reaches the processing speed of 200Mbps, adopts standard internal integrated circuit mode to finish that signal is connected and the sequential matching process between access interface part and the main frame; Adopt digital control impedance matching (DCI) the technology I/O holding wire short circuit of programmable gate array internal realization at the scene; 2M system door structure, the distributed RAM of 320K, 720K Block RAM, 40 special multiplier, 4 groups of digital dock managerial structures (DCM) can externally provide 4 different clock signals, reach as high as 565 user I/O reach as high as 270 pairs of differential signals to, support 18 kinds of single file I/O standards and 8 kinds of difference I/O standards.In the design of native system, adopt LA 14 haplotype data rate interface modules 2 to connect main frame and present devices, for present device provide with main frame between communicate by letter and data interaction.In addition, all power supplies of present device are all provided by this interface.Internal integrate circuit bus interface 2.1 obtains the facility informations such as identifier, operation level and temperature of present device by the I2C E2PROM on the internal integrate circuit bus access card, thereby discerns present device.16 bit data interface of 4 haplotype data rate interfaces 2.2 frequency multiplication under doubleclocking drives becomes 32 of logics, its utilization LA_1 agreement, and the space of selecting in practice and customizing is bigger; JTAG debugging interface 2.3 only limits to provide test interface (not supporting the programming to programmable read only memory and field programmable gate array), thus in design, introduced the JTAG slot in addition, by the PC programmable read only memory that directly downloads; Peripheral supply module 2.4 is when generating 2.5V voltage, and we have adopted the TPS75525 voltage transitions chip of TI, 5Pin TO-263 (KTT) encapsulation; When generating 1.2v voltage, we have adopted the TPS54312 voltage transitions chip of TI, 20Pin PWP encapsulation; When generating 0.75V voltage, we adopt MAX1589EZTAFJ, the TDFN encapsulation; Adopt internal integrate circuit bus programmable read only memory circuit 3.1 minute book invention facility informations, comprise parameters such as device identifier, operation level and temperature.In addition, internal integrate circuit bus programmable read only memory circuit 3.1 itself is also supported password encryption and cryptoguard; Adopt Flash programmable read only memory circuit 3.2 when powering on, automatically field programmable gate array to be configured, two kinds of master mode and controlled modes are arranged.
The external equipment that is associated with present device mainly contains main frame and PC.Present device connects main frame by the socket of one 114 pin, and interface signal is followed the LA_1 agreement, and the power supply of present device is also introduced by this socket in addition.With being connected between the outer computer mainly by jtag interface, by this interface debugging and programming field programmable gate array and programmable read only memory.In the visit to field programmable gate array, the JTAG pattern is enjoyed limit priority.
Hardware reset and software reset's port on our invention equipment, have also been designed at field programmable gate array, hardware reset by to field programmable gate array PROG_B pin set remove configuration store district internal memory, can dispose automatically again by JTAG pattern programming again or programmable read only memory then.Software reset's port is mainly used in resetting of program and debugs, and its function can be defined voluntarily by the user.
The work clock of field programmable gate array carries crystal oscillator by the 40MHz plate and provides, the 200Mhz 4 haplotype data rate interface clocks that also can adopt 114 slots to provide, more than two kinds of clocks all introduce by the global clock port, programmable gate array internal carries out frequency division and frequency multiplication generation system clock by digital dock managerial structure module at the scene.
Below each module is launched explanation.
1, the field programmable gate array hardware module 1
(1) configuration mode of field programmable gate array hardware module 1
The compatible various configurations pattern of the Spartan field programmable gate array that we adopt, the selection of each configuration mode realizes being provided with of pattern pin high-low level by toggle switch.The pin level configuration of different mode correspondence sees the following form 1:
| Configuration mode | M0 | M1 | M2 | Synchronised clock | Data width | Serial output |
| The master control serial mode | 0 | 0 | 0 | |
1 | Be |
| Controlled |
1 | 1 | 1 | The |
1 | Be |
| The master control |
1 | 1 | 0 | |
8 | Not |
| Controlled parallel schema | 0 | 1 | 1 | The |
8 | Not |
| The |
1 | 0 | 1 | The |
1 | Not |
Table 1: the MODE pin configuration of each pattern correspondence
Illustrate: the JTAG pattern is not subjected to the restriction of model selection and available all the time, for it distributes preference pattern just in order to prevent that the configuration mode with other clashes in layoutprocedure.
The system resource of field programmable gate array hardware module 1
In single board design, we have adopted the Spartan3XC3S2000 field programmable gate of Xilinx company
Array, its main hardware parameter is as follows:
2M system door structure;
The distributed RAM of 320K, 720K Block RAM;
40 special multiplier;
4 groups of digital dock managerial structures can externally provide 4 different clock signals;
Reach as high as 565 user I/O;
It is right to reach as high as 270 pairs of differential signals;
Support 18 kinds of single file I/O standards and 8 kinds of difference I/O standards.
The I/O of field programmable gate array is divided into 8 Bank, and the I/O output power supply of each Bank is relatively independent, can support 8 kinds of different I/O standards in principle simultaneously.
(2) the power supply explanation of field programmable gate array hardware module 1
The power supply of field programmable gate array mainly is divided into following components: field programmable gate array core power supply V
CcintField programmable gate array auxiliary power supply V
CcauxOutput drive level V
CcoInput reference level V
Ref
Wherein, voltage that has such as Vccint and Vccaux relative fixed, other voltage changes with the corresponding with it I/O standard that Bank adopted.Powering on is that each level must satisfy corresponding requirement.In the design, Bank1 to Bank3 owing to adopted the HSTL_I standard consistent, so in these Bank, must adopt 1.5Vcco and 0.75V Vref with 4 haplotype data rate interfaces.
In the design, Bank1 to Bank3 owing to adopted the HSTL_I standard consistent, so in these Bank, must adopt 1.5Vcco and 0.75V Vref with 4 haplotype data rate interfaces.Detailed level configuration is as shown in the table:
| Input voltage | Bank1/Bank2/Bank3 | Bank0/Bank4～Bank7 |
| Vccint | 1.2V | 1.2V |
| Vccaux | 2.5V | 2.5V |
| Vcco | 1.5V | 2.5V |
| Vref | 0.75V |
Table 2: field programmable gate array incoming level tabulation
Digital control impedance match technique is the I/O holding wire termination that realizes of programmable gate array internal at the scene, for different I/O standards different implementation methods is often arranged, mainly draw or drop-down reference resistance by providing to the VRN of each Bank of field programmable gate array and VRP pin, field programmable gate array provides digital control impedance matching according to the termination mode of each Bank correspondence and the characteristic impedance value that provides to each I/O pin.
In the design, be primarily aimed at the digital control impedance matching of HSTL_I standard configuration, the HSTL_I standard does not start termination when exporting as signal, enable termination when importing as signal, and is to comprise the both-end that draws with drop-down reference resistance to connect form.
Comprise also on the circuit of field programmable gate array hardware module 1 that direct current 1.2V is the peripheral power supply of field programmable gate array module for power supply, 2.5V and three peripheral DC voltage converting circuit of 0.75V reference voltage and several peripheral circuits such as 40MHz global clock signal generating unit and reset switch circuit.Wherein, the 40MHz crystal oscillator provides global clock for field programmable gate array, and can realize frequency inverted by on-site programmable gate array internal digital dock managerial structure module.At the scene in the programmable gate array controlled mode, for programmable read only memory provides the configurable clock generator signal.Internal integrated circuit programmable read only memory and 4 haplotype data rate interfaces communicate with internal integrated circuit, and main frame obtains this device parameter with this.
2,4 haplotype data rate interface modules 2
4 haplotype data rate interface modules 2 are fed back the result main frame at last and are carried out next step reorganization and protocol processes for high speed data link control protocol decapsulation and end-to-end protocol bag counter-rotating justice that the logic interfacing field programmable gate array hardware module between field programmable gate array and the main frame 1 mainly walks abreast to the multipath high-speed data link control protocol frame from main frame.
(1) interface operation summary
4 haplotype data rate interface modules 2 are followed following several principles:
The data transmission structure and the time sequential routine thereof of (2) 4 haplotype data rate interface modules 2
The data write structure: the word write signal has BW1# and two control signals of BW0#, the most-significant byte of difference control data input pin (D[15:8]) and least-significant byte (D[7:0]), corresponding with it check digit is DP1 and DP0.Write cycle time W# when detecting the K rising edge is that low level begins.The address of write cycle time is provided by A at K# rising edge subsequently.In the same cycle, write data and obtain at the rising edge of K and K#.Concrete data write sequential and are: at the rising edge of K, the most-significant byte of BW1 control (D[15:8]) writes byte 0Bits[31:24], the least-significant byte of BW0 control (D[7:0]) writes byte 1Bits[23:16]; At the rising edge of K#, the most-significant byte of BW1 control (D[15:8]) writes byte 2Bits[15:8], the least-significant byte of BW0 control (D[7:0]) writes byte 0 Bits[7:0].
The data export structure: the data export structure is corresponding with the data write structure, and read cycle, R# when detecting the K rising edge was that low level begins.Meanwhile, read on A the address of read operation.Data are reference clock output with C and C# later at next K rising edge.
(3) output register control (slave unit attribute)
4 haplotype data rate interface modules 2 provide two kinds of mechanism for depositing dateout.Usually, this provides the difference input clock control beat by C and C#, and they are by small phase deviation, allows user's data is exported several nanoseconds on the basis of subsequently K and K# clock signal delay.Thereby the mode that makes equipment read equipment with similar conventional flow waterline is come work.Burst1 and Burst2 based on the byte write control signal are alternative mode; In read operation, offer Echo Clock signal CQ, the CQ# of main frame; Produce the output verification position.
(4) LA_1 agreement utilization of the present invention
The LA_1 agreement provides a reference scheme for the utilization of 4 haplotype data rate interfaces, and the space of selecting in practice and customizing is bigger.In the design of slave of the present invention, because the relative independentability of scheduling memory, address signal has only played the effect of sheet optional equipment, does not have the mapping one by one with the actual memory space.Yet based on the versatility of equipment, the design of interface routine also must comprise:
● based on the Burst1 and the Burst2 alternative mode of byte write control signal
● in read operation, offer Echo Clock signal CQ, the CQ# of main frame
● produce the output verification position
(5) interface supply module detailed design
The three-way direct current power supply that the main power supply of this equipment provides from Mictor 114 sockets, magnitude of voltage is respectively: 3.3V, 1.5V, 1.8V.In addition,, provide HSTL_I reference level for 1 to 3Bank simultaneously, also will on card, utilize local 1.2V, 2.5V, the 0.75V level of generating of voltage control chip in order to drive the Spartan field programmable gate array.Wherein, 1.2V is the power supply of field programmable gate array kernel, and 2.5V is field programmable gate array auxiliary power supply and 4 to 7Bank and 0Bank I/O power supply, and 0.75V is 1 to 3Bank reference level.When producing this ground level, 3.3V generates 1.2V and 2.5V, and 1.8V generates 0.75V.
TPS75525 3.3/2.5V voltage transitions chip is when generating 2.5V voltage, and we have adopted the TPS75525 voltage transitions chip of TI, 5Pin TO-263 (KTT) encapsulation.Wherein pin one (EN) enables for input, and pin two (IN) is an incoming level, and pin 3 (GND) is ground, and pin 4 (OUTPUT) is an output level, and pin 5 (FB/PG) is PG output under the input feedback/AD HOC.
TPS543123.3/1.2V voltage transitions chip is when generating 1.2V voltage, and we have adopted the TPS54312 voltage transitions chip of TI, 20Pin PWP encapsulation.Wherein pin one (AGND) is simulated ground, and pin 5 (BOOT) keeps, and pin one 9 (FSEL) is that the frequency input is selected, and pin 3 (NC) nothing connects; Pin one 1-13 (PGND) is a Power Groud, pin 6-10 (PH) is the phase place I/O, pin 4 (PWRGD) is Power Good indication, the input of pin two 0 (RT) frequency configuration resistance, pin one 8 (SS/ENA) startup/input slowly enables/exports complexing pin, pin one 7 (VBIAS) internal bias output control, pin one 4-16 (VIN) incoming level, pin (VSENSE) Error Feedback is amplified input.
The 1.8V power drives that MAX1589 1.8/0.75V voltage transitions chip provides by Mictor 114 sockets, the HSTL_I reference level of output 0.75V, complete chip part label is MAX1589EZTAFJ, adopts standard TDFN encapsulation.Wherein pin 6 (IN) is the power supply input, pin 4 (GND) is ground, pin 5 (SHDN) is used for shutdown signal, low level is effective, and pin 3 (RESET) is a Restart Signal, and low level is effective, pin two (I.C.) is inner the connection, put sky or ground connection, pin one (OUT) is voltage output, and middle part pad EP is ground.
3, programmable read only memory application configuration module 3
Flash programmable read only memory circuit 3.2 has two kinds of configuration modes to field programmable gate array automatically when powering on: master mode and controlled mode, its main distinction is the difference of configurable clock generator signal source.In the programmable gate array master mode, field programmable gate array provides the configurable clock generator signal for programmable read only memory at the scene, in the programmable gate array controlled mode, provides the configurable clock generator signal by external crystal-controlled oscillation at the scene.In design, can switch two kinds of patterns of principal and subordinate by regulating field programmable gate array configuration mode selector switch.The acquiescence mode is the field programmable gate array master mode, and we regulate the programmable read only memory configured rate by the speed config option is set in the Xilinx BitGen software.Fig. 3 is the connection layout of field programmable gate array hardware module 1 and Flash programmable read only memory module 3.2 under the field programmable gate array master mode.
Field programmable gate array by and the FLASH programmable read only memory between serial line interface accept configuration information, in addition, can also directly be configured and DEBUG by jtag interface to field programmable gate array.After powering on, field programmable gate array is reading of data in programmable read only memory voluntarily, can also reconfigure by reset signal in the time of in working order.
Fig. 4 is programmable read only memory application configuration module 3 configuration flow figure, is at first powered on by system, if power supply satisfies condition of power supply, be Vccin＞1V, Vccaux＞2V, three conditions of VccoBank4＞1V satisfy simultaneously, then remove configuration store district internal memory, judge then whether pin INT_B is high level, if high level then detects the configuration mode pin automatically, then according to associative mode download configuration information, if errorless after the CRC check, then configuration finishes, and enters user model.If under user model, need to reconfigure field programmable gate array, then put PROG_B pin level low.If in layoutprocedure, detecting the PROG_B pin is low level, then removes configuration store district internal memory, enters new configuration flow; If after first configuration was finished, detecting the INT_B pin was low level, then needs to carry out again CRC check, detect configuration information.
4, software module 4 of the present invention
Fig. 5 is the connection layout between software module.Each intermodule transmits information by signal: at first send reading writing information and data message by network processing unit, queue scheduling module 4.1 is obtained read-write and data message thereof from network processing unit, after receiver module 4.2 obtains corresponding write order from queue scheduling module 4.1, buffering area is carried out corresponding write operation, so that high speed data link control protocol packet counter-rotating justice and banner word thereof are handled the processing of mould 4.4, control signal valid frame signal after the processing, escape signal and processor dateout thereof are imported frame effect block 4.5 in the lump into, after verification, produce control signal and write buffering signals, the postamble signal, data after effect rub-out signal and the effect thereof, import into and send data cache module 4.3, integrated treatment writes buffering area with data after judging, in conjunction with the read message of queue scheduling module 4.1, export by the data after will handling the read operation of this buffering area.
In the software system module 4, at first send reading writing information and data message by network processing unit, queue scheduling module 4.1 is obtained read-write and data message thereof from network processing unit, after receiver module 4.2 obtains corresponding write order from queue scheduling module 4.1, buffering area is carried out corresponding write operation, so that high speed data link control protocol packet counter-rotating justice and banner word thereof are handled the processing of mould 4.4, control signal valid frame signal after the processing, escape signal and processor dateout thereof are imported frame effect block 4.5 in the lump into, after verification, produce control signal and write buffering signals, the postamble signal, data after effect rub-out signal and the effect thereof, import into and send data cache module 4.3, integrated treatment writes buffering area with data after judging, in conjunction with the read message of queue scheduling module 4.1, export by the data after will handling the read operation of this buffering area.Software system module 4 carries out the monitoring of frame head search, CRC, counter-rotating justice, the detection that abandons sequence, frame length and the search of postamble to the data of each passage, in case detecting the current information transmitted figure place of a certain frame reaches maximum frame length or detects when abandoning sequence, state machine finishes the processing of present frame, and again a new frame is carried out the frame head search, and the remaining data in the present frame will be not processed.Software system module 4 is handled the high speed data link control protocol data flow up to the transmission of 128 channel parallels simultaneously, its realization is to adopt time-multiplexed mode, wherein the channel status memory is to realize time-multiplexed key, each passage all has a fixing memory space among this channel status memory, in order to store the processing condition data of this passage, it is channel status information, be processed one segment length regular hour of the data allocations sheet of each each section of passage needs, when each timeslice finishes, when the up-to-date state information of prepass will be deposited in respective stored space in the channel status memory, when new one piece of data arrives, the state information that passage under this segment data is refreshed in a last timeslice will be read and be loaded into from the channel status memory in the state machine, for the data processing of a new round is prepared.
Fig. 6 is the design's a software design state transition diagram.The present invention can handle the high speed data link control protocol data flow up to the transmission of 128 channel parallels simultaneously, its realization is to adopt time-multiplexed mode, but the core is made of a high speed data link control protocol processor and a channel status memory of receiving and dispatching independent and time-division processing.Wherein the channel status memory is to realize time-multiplexed key, and each passage all has a fixing memory space among this channel status memory, in order to store the processing condition data of this passage, i.e. channel status information.The present invention is the processed data allocations of each each section of passage needs one a segment length regular hour sheet.When each timeslice finishes, when the up-to-date state information of prepass (comprising: the residing state of state machine when processing finishes, to this passage the CRC check sign indicating number and the length of stub data not thereof of data processed, handled in the current time sheet but the reception data that do not have enough time as yet to be output etc.) will be deposited in the respective stored space in the channel status memory.When new one piece of data arrives, the state information that the passage under this segment data is refreshed in a last timeslice will be read and be loaded into from the channel status memory in the state machine, for the data processing of a new round is prepared.
In order to realize the monitoring function of main frame to the transfer of data of each passage, in the design, in idle condition, added branch's state, if main frame (host) is found the wrong or long-time data that do not receive this passage of the transfer of data of certain passage, the state information that can and can only inquire about this passage in this multichannel wait idle condition is to guarantee not interrupt the normal running to the rest channels data.
We are the methods of " Top to Down " (" from the top to bottom ") what Field Programmable Gate Array is carried out function when design adopt, that is function as requested designs the theory diagram of top layer earlier, and this figure is made up of the several function module usually.Again each module is refined as submodule, also can be divided into from level to level subordinate's submodule to each submodule to complicated design, the function of each layer can realize with hardware description language or circuit diagram.
Fig. 7 is a single channel high-speed data processor state transition diagram.The data of each passage are carried out the monitoring of frame head search, CRC check, counter-rotating justice, the detection that abandons sequence, frame length and the search of postamble.Reach maximum frame length or detect when abandoning sequence in case detect the current information transmitted figure place of a certain frame, state machine finishes the processing of present frame, and again a new frame is carried out the frame head search, and the remaining data in the present frame will be not processed.
S1: default setting, carry out the search of frame head;
S2: the processing of data, comprise counter-rotating justice, the verification of CRC abandons the detection of sequence;
S3: CRC check sign indicating number and frame length are judged, mode bit is identified.
Be in default setting S1 when state machine is started working, carry out the search of frame head.The data of storing in the bonding state register, after the displacement, be judged as (7E) by logical relation after, state machine thinks that just oneself searches frame head, and jumps into state S2 immediately, carries out the processing of data, comprises counter-rotating justice, abandons the detection of sequence.If state machine detects and abandons sequence, the remaining data of this passage present frame will be dropped, and will be promptly neither processed, also not send among the FIFO, and state directly transfers S1 to by S2, carry out the frame head search of a new frame, provide error condition simultaneously.Among the state S2,, jump into state S3, at first carry out the judgement of CRC check sign indicating number and final frame length, provide various false judgment accordingly if when having searched the frame head of the postamble of present frame or next frame.Because the postamble of former frame is the frame head of back one frame in the design, the frame head search in therefore need not S1, and directly jump into S2; Because the calculating of frame length is in (but still in major state " processing ") outside this sub-state machine, carry out synchronously and independently with the processing of data, so when state machine is in state S2, in the positive deal with data, surpassed the length of maximum permission, abandoned sequence as detecting in case find frame length, directly jump into S1, carry out the frame head search of next frame, provide the long error condition of frame length simultaneously, and the remaining data of present frame will be not processed.State machine is jumped into by S2 after the S3, at first carries out the judgement of various mistakes.When finding that there is a plurality of mistake simultaneously in the Frame that receives, state machine is the highest error condition of priority with frame effect sequence errors.Because except normal condition (receive data neither at frame head, also not at postamble), most of state all when finding postamble (in the S3 state) judge, and export in the lump in company with receiving data.And the beginning of a high speed data link control protocol frame, can only in S1, judge, this moment, shift register can not have output, so be necessary in the mid-state flag bit start of frame delimiter position of channel status RAM, when finding frame head, it is changed to 1, by the time shift register is when expiring for the first time, the output state position.
In order to realize the adopted function of reversing, when state machine detects 0x7D, be about to the output of next data and 0X20 XOR.
In order to realize multichannel time division multiplexing, equally also control the processing time of a passage with the variable frame length in state machine, promptly handle the one digit number certificate at every turn, length subtracts 1, until being 0, thereby has finished the processing of this passage.
We are by means of the way of multi-channel high-speed data LCP, during reception, append channel number at the data front end and (consider our specific design object, this channel number adopt KEY number more reasonable), each passage is furnished with a channel status register, record this passage last time (being corresponding KEY number) disposition, and CRC check value, so that on this basis, continue to calculate the CRC check value, thereby finished verifying function next time.
Data processed promptly sends out the ready signal corresponding.The information that is obtained when writing state: the number and the length thereof that comprise complete end-to-end protocol bag in the bag of this processing, and data are read, the residue stub then is deposited with on-site programmable gate array internal, when treating identical next time KEY number data input, constitute complete end-to-end protocol bag and export again.
Should be understood that, for those of ordinary skills, can preferred embodiments according to the present invention with and technical conceive make various possible changes or replacement, and all these changes or replace the protection range that all should belong to claims of the present invention.
Claims (8)
1, a kind of multi-channel high-speed data processor is characterized in that this processor specifically comprises four following modules: field programmable gate array hardware module (1); 4 haplotype data rate interface modules (2); Programmable read only memory application configuration module (3) and software system module (4); Described 4 haplotype data rate interface modules (2) comprising: internal integrate circuit bus interface (2.1), 4 haplotype data rate interfaces (2.2), jtag interface (2.3) and peripheral supply module (2.4); Field programmable gate array hardware module (1) connects external host, is connected with peripheral supply module (2.4) and joins by the Flash programmable read only memory circuit (3.2) in jtag interface (2.3) and the programmable read only memory application configuration module (3) by power line by 4 haplotype data rate interfaces (2.2), and Flash programmable read only memory circuit (3.2) also joins by the PC of jtag interface (2.3) and outside; Internal integrate circuit bus programmable read only memory circuit (3.1) in the programmable read only memory application configuration module (3) connects external host by internal integrate circuit bus interface (2.1); Software system module (4), comprised: queue scheduling module (4.1), reception data cache module (4.2), transmission data cache module (4.3), high speed data link control protocol packet counter-rotating justice and banner word processing module (4.4) and Frame Check Sequence module (4.5) link together by the signal transmission between each module that software system module (4) comprises; Software system module (4) resides in the programmable read only memory application configuration module (3), after the multi-channel high-speed data processor work, program is loaded in the field programmable gate array hardware module (1), and field programmable gate array hardware module (1) links together by the program of 4 haplotype data rate interface modules (2) with external host.
2, multi-channel high-speed data processor according to claim 1 is characterized in that field programmable gate array hardware module (1) adopts the coprocessor of 2,000,000 " XC3S2000 " field programmable gate arrays as external host.
3, multi-channel high-speed data processor according to claim 1 is characterized in that in the 4 haplotype data rate interface modules (2), and peripheral supply module (2.4) has adopted " TPS75525 " voltage transitions chip when generating 2.5V voltage; When generating 1.2v voltage, adopted " TPS54312 " voltage transitions chip; When generating 0.75V voltage, adopt " MAX1589EZTAFJ " chip.
4; multi-channel high-speed data processor according to claim 1; it is characterized in that in the programmable read only memory application configuration module (3); adopt the facility information of the described processor of internal integrate circuit bus programmable read only memory circuit (3.1) record; comprise device identifier; operation level and temperature parameter; external host detects with the identification multi-channel high-speed data processor by internal integrate circuit bus programmable read only memory circuit (3.1), and internal integrate circuit bus programmable read only memory circuit (3.1) itself is also supported password encryption and cryptoguard.
5, multi-channel high-speed data processor according to claim 1, it is characterized in that in the programmable read only memory application configuration module (3), adopt Flash programmable read only memory circuit (3.2) automatically field programmable gate array hardware module (1) to be configured when powering on, configuration mode has two kinds of master mode and controlled modes.
6, a kind of high-speed data processing method of multi-channel high-speed data processor as claimed in claim 1, it is characterized in that in the software system module (4), at first send reading writing information and data message by external host processor, queue scheduling module (4.1) is obtained reading writing information and data message from external host processor, after reception data cache module (4.2) is obtained corresponding write order from queue scheduling module (4.1), the buffering area that receives data cache module (4.2) is carried out corresponding write operation, so that the processing of high speed data link control protocol packet counter-rotating justice and banner word processing module (4.4) thereof, control signal valid frame signal after the processing, escape signal and external host processor dateout are imported Frame Check Sequence module (4.5) in the lump into, after verification, produce control signal and write buffering signals, the postamble signal, data after check errors signal and the verification, import into and send data cache module (4.3), send and after data cache module (4.3) integrated treatment is judged data after the verification are write the buffering area that sends data cache module (4.3), in conjunction with the read message of queue scheduling module (4.1), export by the data after will handling the read operation of the buffering area that sends data cache module (4.3).
7, the high-speed data processing method of multi-channel high-speed data processor according to claim 6, it is characterized in that software system module (4) carries out the frame head search to the data of each passage, CRC, counter-rotating justice, abandon the detection of sequence, the monitoring of frame length and the search of postamble, in case detecting the current information transmitted figure place of a certain frame reaches maximum frame length or detects when abandoning sequence, state machine in the software system module (4) finishes the processing of present frame, and again a new frame is carried out the frame head search, and the remaining data in the present frame will be not processed.
8, the high-speed data processing method of multi-channel high-speed data processor according to claim 6, it is characterized in that software system module (4) handles the high speed data link control protocol data flow up to 128 channel parallels transmission simultaneously, its realization is to adopt time-multiplexed mode, wherein the channel status memory is used to realize time division multiplexing, each passage all has a fixing memory space among this channel status memory, in order to store the processing condition data of this passage, it is channel status information, be processed one segment length regular hour of the data allocations sheet of each each section of passage needs, when each timeslice finishes, when the up-to-date state information of prepass will be deposited in respective stored space in the channel status memory, when new one piece of data arrives, the state information that passage under this segment data is refreshed in a last timeslice will be read and be loaded into from the channel status memory in the state machine, for the data processing of a new round is prepared.
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| US8578084B2 (en) * | 2009-04-08 | 2013-11-05 | Google Inc. | Data storage device having multiple removable memory boards |
| CN101582884B (en) * | 2009-06-15 | 2012-05-23 | 东南大学 | System and method for 3G data packet reorganization based on FPGA |
| CN102662686B (en) * | 2012-03-09 | 2015-05-13 | 中国科学院微电子研究所 | Loading method of FPGA and device thereof |
| CN102999350B (en) * | 2012-10-24 | 2016-10-05 | 绵阳市维博电子有限责任公司 | A kind of FPGA program upgrading download online method in digital signal processing platform |
| CN103235770B (en) * | 2013-04-25 | 2016-05-04 | 杭州华澜微电子股份有限公司 | Based on the solid-state memory at the wide digital interface of carry interface |
| CN104618083B (en) * | 2015-02-12 | 2017-09-29 | 浪潮电子信息产业股份有限公司 | A kind of method of multichannel message forwarding |
| US9246492B1 (en) * | 2015-06-24 | 2016-01-26 | Xilinx, Inc. | Power grid architecture for voltage scaling in programmable integrated circuits |
| CN109511275A (en) * | 2016-12-31 | 2019-03-22 | 深圳配天智能技术研究院有限公司 | A kind of numerical control system and its data transmission method based on field programmable gate array |
| CN106899386B (en) * | 2017-02-09 | 2020-11-03 | 武汉米风通信技术有限公司 | Method for demodulating fragmented frame signals based on multi-channel communication receiving system |
| CN113553280B (en) * | 2021-06-21 | 2023-04-28 | 上海机电工程研究所 | Based on I 2 Multi-module time-sharing power-on method and system for integrated electronic platform of C bus |
| CN113641612B (en) * | 2021-08-16 | 2022-07-26 | 中国科学院近代物理研究所 | Multichannel data real-time processing equipment |
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