CN100437945C - Method for producing transistor and semiconductor device circuit - Google Patents
Method for producing transistor and semiconductor device circuit Download PDFInfo
- Publication number
- CN100437945C CN100437945C CNB2005100919197A CN200510091919A CN100437945C CN 100437945 C CN100437945 C CN 100437945C CN B2005100919197 A CNB2005100919197 A CN B2005100919197A CN 200510091919 A CN200510091919 A CN 200510091919A CN 100437945 C CN100437945 C CN 100437945C
- Authority
- CN
- China
- Prior art keywords
- silicon fiml
- crystallization
- silicon
- catalytic elements
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Abstract
The invention provides a thin-film transistor forming process, which includes the following steps: forming an silicon film on the substrate, which belongs to the amorphous-type; supplying for the silicon film, a catalysis element for promoting the crystallization; annealing the silicon film using the catalysis element, so as to crystallize the silicon film; forming an gate on the crystallized silicon film; supplying impurity for the crystallized silicon film; forming the substance containing the catalysis element at a plurality of parts of the silicon film; and removing part of the substance.
Description
The application is dividing an application of application number is 98116320.3, the applying date is on March 12nd, 1994 original bill application, and the first application number formerly of this original bill is JP1993-079000, and first priority date is on March 12nd, 1993.
Technical field
The present invention relates to thin-film transistor (TFT) and make this transistorized method, also relate to and have a plurality of thin-film transistors (TFTs) and semiconductor circuit and manufacture method thereof.The thin-film transistor that produces according to the present invention can form on the dielectric substrate such as glass and on one of Semiconductor substrate such as monocrystalline silicon.Especially, the present invention relates to a kind of like this semiconductor circuit, it is included in matrix circuit and the external circuit that drives this active matrix circuit and work of work such as monolithic active matrix circuit (the available Chu LCD) under the low speed under high speed.The invention still further relates to the thin-film transistor that produces by according to heat treatment crystalization and activation.
Background technology
Recently, people have carried out all research to the insulated gate semiconductor device with film active layer (active layer) (also being referred to as the region of activation).Especially to film-insulated gate semiconductor device or be called thin-film transistor (TFTs) and carried out making great efforts research.This class thin-film transistor so forms so that can be used to control the pixel in drive circuits such as LCD with matrix structure on the transparent insulation substrate.Thin-film transistor is divided into non-crystalline silicon TFT and silicon metal two classes according to the kind and the crystalline state of used semi-conducting material.
General its penetration of electric field rate (field mobility) of amorphous semiconductor is little, thus can not with Chu must TFT with high speed operation in.Moreover, because the electric field mobility of P type amorphous silicon is extremely low, so can not produce P channel TFT (PMOS TFT).Therefore, can not make by P channel TFT and N channel TFT (NMOS TFT) and be combined into a complete MOS circuit (CMOS).
On the contrary, crystalline semiconductor has the electric field mobility more higher than non-crystalline semiconductor, thereby can be with high speed operation.When adopting silicon metal, also can make PMOS TFT because NMOSTFT can both can have been made in the same manner, so might make cmos circuit.For example, a kind of known liquid crystal display device of active array type has so-called single chip architecture, has promptly both constituted the active matrix district by CMOS crystal TFT and has also constituted external circuit (comprising drive circuit etc.).Because these reasons, people have carried out strong research and development to the TFT that uses silicon metal.
In for a kind of method example that obtains silicon metal, be with laser or be equivalent to the high light irradiation non-crystalline silicon of laser and make its crystalization.Yet because the unsteadiness of laser output and because the unsteadiness in utmost point short processes cycle, this method does not possess to be produced in batches or the prospect of practical application.
Nowadays but a kind of method of practice is the method that amorphous silicon is made its crystallization through heating.By this method, might obtain to change between each batch output very little silicon metal.But this method has a problem.
In general, the formation of silicon metal requires to heat-treat under about 600 ℃ for a long time, or at 1000 ℃ of high temperature or more heat-treat under the high temperature.Under the situation of a kind of method after the utilization, optional substrate is limited to the quartzy substrate of making, and causes the cost of substrate high.Before application under a kind of method situation, the optional scope of substrate is wide but cause another problem.
When using cheap first alkali glass substrate (for example, produced by corning company No. 7059), traditional production TFT technology is roughly carried out in the following manner:
(1) forms amorphous silicon film;
(2) crystallization of amorphous silicon film (600 ℃ or higher, 24 hours or longer);
(3) form the insulated gate film;
(4) form gate electrode;
(5) introduce mix (with ionic-implantation or ion doping method);
(6) activate mix (600 ℃ or higher, 24 hours or longer);
(7) form insulating barrier; With
(8) form source electrode and drain electrode.
In this technical process, there are some problems step (2) and (6).Multiple alkali-free glass has about 600 ℃ distortion temperature (being 593 ℃) under Cornign 7059 situations.Technical process under this temperature causes the problem such as substrate contraction and bending.In step (2), this is first heat treatment step, owing to also form pattern process (patte-rning process), the contraction of substrate can not cause serious problems.Yet,, form technology through pattern at that time in step (6).So in step (6), when substrate shrinks, in series of steps after this, can not correctly carry out mask alignment, thereby constitute the main cause of damaging finished product.Therefore, people wish the technology of carrying out step (2) under the substrate distortion temperature being lower than, with under lower temperature (be preferably in and be lower than 50 ℃ of temperature of glass distortion or lower temperature, preferable be lower than 50 ℃ of the maximum technological temperatures of step (2) or more under the low temperature) carry out the operation of step (6).
For satisfying these requirements, can use a kind of method of aforesaid use laser and so on.Yet, except laser output problem of unstable, another problem that people have awared be since be excited beam irradiation that part of (source and drain region) and be not excited that part of (active area of beam irradiation, be that zone below the grid) between the stress that temperature difference produced that occurs, thereby the reliability of impairing.
On the other hand, the TFT that is made by non-crystalline semiconductor has the low characteristic of cut-off current.Therefore this TFT is applied to not require that in this display, only single conductivity type is just enough, and need have the ability that highly keeps electric charge in the purposes of transistor and so in the active matrix of LCD of very high service speed and the pixel circuit.Yet this TFT can not be applied in the external circuit of necessary high speed operation.
In a kind of crystalline solid silicon TFT, and when no-voltage is applied to grid (, during the non-selection cycle), the leakage current that flows through is greater than the leakage current in non-crystalline silicon tft.When using silicon metal TFT in the LCD, take to dispose and be used to compensate the auxiliary capacitor of leakage current and the measure that two TFT are connected in series, to reduce leakage current.
Fig. 5 illustrates a kind of calcspar that is used for the active matrix circuit of LCD.Dispose column decoder 101 and row decoder 102 on the substrate 107 as external circuit.The pixel circuit 104 that respectively comprises a transistor and a capacitor is formed in the matrix district 103.Matrix district and external circuit are connected to each other by lead 105 and 106.The TFT that is used for external circuit need have high speed performance, and used TFT needs the performance of low leakage current in pixel circuit.Though these performances are actually mutual contradiction, but require on same substrate, also to form two types TFT by same technology.
In general, the formation of silicon metal requires long period and the heat treatment under about 600 ℃, or in 1000 ℃ of high temperature or the more heat treatment of high temperature.For example, it is impossible making the external circuit that multi-crystal TFT with high mobility forms at the bottom of the same village and utilize high non-crystalline silicon tft structure by (OFF) resistance because amorphous silicon in above-mentioned heat treatment step by crystalization.
Summary of the invention
Therefore, from the viewpoint of producing in batches, be used in and produce that the method with laser is difficult in the TFT process.On the other hand, the present situation of this area is to can not find other effective methods.For these difficult problems of solution, derived the present invention.An object of the present invention is to when keeping the property produced in batches, addressing these problems.
For solving these difficult problems, now implemented this invention.Yet a kind of improvement structure causes complex process, and it is not desired that output is hanged down higher with cost.An object of the present invention is by when keeping the property produced in batches, making the TFT that requires high mobility and require these two kinds of TFT of TFT of low-leakage current to produce with plain mode selectively to change technical process minimumly.
The inventor's achievement in research shows: add a small amount of catalytic specie to amorphous silicon membrane, just strengthened crystallization, reduced the temperature of crystal formation and shortened crystallization time.To the Chu catalysis material, resemble nickel (Ni), iron (Fe), cobalt (Co), the simple material of platinum (Pt) and so on or its compound are suitable as silicide.In fact, amorphous silicon membrane can by below amorphous silicon film or above the formation film, crystal grain, or the family of these catalytic elements (cluster) or by introducing the mode of these catalytic elements at amorphous silicon film with resembling method that ion injects and so on; Then under proper temperature, generally under 580 ℃ or lower temperature, amorphous silicon film is heat-treated and crystallization.
Forming under the situation of amorphous silicon film, these catalyst can be added in certain material gas with chemical vapor deposition method (CVD method); Forming under the situation of amorphous silicon film with the physical vapor method that resembles sputter and so on, these catalyst can be added in the deposition materials that resembles rake or deposit source.Though this is a kind of natural result, heat treated temperature is high more, and the time of crystallization is just short more.In addition, nickel, iron, cobalt, the concentration of platinum is high more, and then the temperature of crystallization is low more and time crystallization process is short more.Research through the inventor finds that for strengthening crystallization, the concentration of at least a element should be
Or more, be preferably
Or it is more.
In addition, should note: the zone that does not resemble this catalysis material can not strengthen the crystallization effect, and can keep amorphous state.For example, concentration is
Or littler, be preferably
Or littler noncrystally under 600 ℃ or higher temperature, begin crystallization, but at 580 ℃ or more do not strengthen crystallization under the low temperature at all.But, because the required hydrogen of balance dead key (neutra-lizing dangling bonds) is released in 300 ℃ or higher environment in the amorphous silicon, so heat-treat for the suitable characteristic of semiconductor of acquisition is preferably in the hydrogen atmosphere.
In the present invention, utilize the crystallization characteristic under above-mentioned catalysis material effect to remove to form amorphous silicon film.Its part is by crystallization selectively and as the silicon metal TFT in the external circuit of active matrix circuit.Amorphous another part is used as the non-crystalline silicon tft in the matrix district (pixel circuit).As a result, can on same substrate, form transistor circuit simultaneously with low leakage current and quick acting opposite characteristic.
Because any of above-mentioned catalysis material all is unfavorable material to silicon, so best their concentration is low as much as possible.In the inventor's research, for especially using it as the active region, the best total amount of the concentration of these catalysis materials is not higher than
To obtain gratifying reliability and characteristic.On the other hand, the fact shows: even in the source, there are quite a large amount of catalysis materials in leakage and so on, and neither problem.
The inventor finds, above-mentioned all problems can be by on the effect that attentiveness is concentrated on this catalytic elements and be used and solved.The manufacture method brief description of TFT of the present invention is as follows:
1) deposition of amorphous silicon film
1 ') importing catalytic elements (injecting or the ion doping method with ion)
2) crystallization of amorphous silicon film (at 600 ℃ or low, in 8 hours scopes)
3) deposit insulated gate film
4) form gate electrode
5) guide the impurity (injecting or the ion doping method) that mixes with ion
5 ') deposition of materials of catalytic elements will be arranged to silicon fiml
6) activate the impurity (600 ℃ or low, in 8 hours scopes) that mixes
7) form the interlayer insulation body
8) form source-drain electrode
Or,
1) deposition of amorphous silicon film
1 ') guiding catalytic elements (using from injecting or the ion doping method)
2) crystallization of amorphous silicon film (600 ℃ or low slightly, in 8 hours scopes)
3) deposit of insulated gate film
4) form grid
5) introduce the impurity (injecting or the ion doping method) that mixes with ion
5 ') introducing catalytic elements (injecting or the ion doping method with ion)
6) activate the impurity (600 ℃ or low slightly, in 8 hours scopes) that mixes
7) form the interlayer insulation body
8) formation source, drain electrode
In these operations, order 5) and 5 ') can put upside down.Operation 1 ') can be replaced by that " film that will contain catalytic elements and so on is bonded on the amorphous silicon film or following operation.From the concentration viewpoint of accurate control catalytic elements, the method that resembles ion injection and so on is desirable.But,, then can utilize this method if resulting TFT characteristic is gratifying from simplifying working process and tightening the viewpoint of equipment funds.
In the present invention, by described operation 1 ') catalytic elements that is incorporated into amorphous silicon film strengthened its crystallization greatly.On the other hand, by 5 ') mainly import to the source, the catalytic elements in drain region strengthened greatly should the zone recrystallization.Therefore, for crystallization with activate, 600 ℃ or low, be generally 550 ℃ or low temperature is just much of that slightly.8 hours heat treatment time scope, also much of that in general 4 hours.Special when beginning evenly to distribute catalytic elements with ion implantation or ion doping method, crystallization process very easily carries out.
In the present invention owing to adopt arbitrary process that grid is present on the region of activation, so the catalytic elements general not operation 5 ') directly adhered to or be injected into the region of activation.Therefore, the concentration of the catalytic elements in change region of activation and the impurity range is possible.For example, the concentration of the catalytic elements by reducing to be added to the region of activation has relatively reduced the bad influence to characteristic and the reliability of TFT to greatest extent.By increasing the concentration of the catalytic elements that will be added to impurity range, suppressed the contraction and the distortion of substrate, quite activating under the low temperature, and can increase output.The almost free of losses of the reliability of TFT and characteristic.
In the present invention, thickness is 1000
Or thin slightly amorphous silicon film is also through catalytic elements and crystallization.The not crystallization of this amorphous silicon film by common heat treatment.From the defective of the pin hole (pinhole) of this step part of preventing TFT and insulating properties with avoid the viewpoint of the disconnecting of grid one grid, the thickness requirement 1000A of crystal silicon film or thinner is preferably 500
Or it is thinner.This be non-be unavailable with laser crystallization method, but the present invention be by in addition at low temperatures heat treated obtain this point.Naturally this helps the further improvement of product.Now utilize several embodiment to further specify the present invention in more detail.
Description of drawings
Fig. 1 (A) is the cross sectional view that shows all steps of production process of being carried out among the embodiment 1 to 1 (E);
Fig. 2 (A) is the cross sectional view that shows all steps of production process of being carried out among the embodiment 2 to 2 (E);
Fig. 3 (A) is the cross sectional view that shows all steps of production process of being carried out among the embodiment 3 to 3 (E);
Fig. 4 (A) is the cross sectional view that shows all steps of production process of being carried out among the embodiment 4 to 4 (E); With
Fig. 5 is the schematic diagram that shows an example of monolithic active matrix circuit.
Embodiment
Fig. 1 is the cross sectional view that shows all steps of production process that embodiment 1 carries out.At first, forming the thickness of being made by silica with sputtering method on substrate (Corning 7059) 10 is 2000
Basilar memebrane 11.Use plasma CVD method deposit inherence (I-type) amorphous silicon film 12 then, its thickness is 500 to 1500
, for example be 1500
With ionic-implantation with
Extremely
For example be
Dosage nickel ion is implanted amorphous silicon film.As a result, being present in amorphous silicon film (Fig. 1 (A)) nickel ion concentration is about
Then, for making the silicon fiml crystallization, be placed on and carry out 550 ℃ of following heat treatment steps of 4 hours in the nitrogen atmosphere.Give the silicon fiml graphing then, to form silicon island district 13.With sputtering method deposit 1000
Thick silicon oxide film 14 is as gate insulating film.In this sputter procedure, as target, underlayer temperature is 200 to 400 ℃, for example is 250 ℃ with silica.This sputtering process carries out in oxygen and argon gas atmosphere, and argon is 0 to 0.5 to the ratio of oxygen.For example 0.1 or littler.
After this, reach 3000 to 8000 with decompression CVD method deposit silicon fiml (comprising 0.1 to 2% phosphorus)
Thickness for example is 6000
Preferably form the step of silica and silicon fiml continuously.Give the silicon fiml graphing then, to form grid 15 (Fig. 1 (B)).
Then, utilize grid impurity (phosphorus) to be implanted silicon area with the plasma doping method as mask.In this operation, phosphine (pH3) is as impurity gas, and accelerating voltage is 60 to 90kv, for example is 80kv, and dosage is
For example be
Therefore, form N-type impurity range 16a and 16b (Fig. 1 (C)).
Then, the silicon oxide film 14 on the impurity range is etched away, to expose impurity range 16.Being formed uniformly thickness with sputtering method on the whole zone shown in Fig. 1 (D) is 5 to 200
(for example 20
) nickel silicide film (molecular formula is Ni Six, wherein 0.4≤X≤2.5, for example X=20) 17.When this film with about 20
The thickness that has reduced when forming, it is not continuous but presents the particle cluster appearance of gathering.Yet in this embodiment (Fig. 1 (D)) these can not produce any problem.
After this, under nitrogen atmosphere, carry out under 480 ℃ (it is than low 70 ℃ of the temperature of above-mentioned Crystallization Procedure) thus 4 hours heat treatment step activator impurity.In this heat treatment process, at first, nickel diffuses to N type impurity range 16a and 16b from the nickel silicide film that covers impurity range.So heat treatment makes crystallization again be easy to carry out.So just, impurity range 16a and 16b have been activated.
Then, form as the thick silicon oxide layer 18 of the 6000A of insulating barrier with plasma CVD method and in this insulating barrier, form contact hole.Source and drain region at TFT form electrode/lead 19a and 19b by the multiple layer metal material membrane such as titanium nitride and aluminium.At last, in the hydrogen atmosphere of 1atm, under 350 ℃, heat-treated 30 minutes,, finished the manufacturing (Fig. 1 (E)) of a thin-film transistor as the result of said process.
Measure the concentration of nickel in the active region (grid is with lower area) of the TFT so produce with ion microprobe (SIMS), its result is about
The concentration of nickel is approximately in impurity range 16
Embodiment 2
Fig. 2 is the cross sectional view that shows the production process step that present embodiment carried out.At first use sputtering method to go up and form 2000 at substrate (Corning 7059)
Thick, as to make by Si oxide counterdie 21.Then, be 500 to 1500 by the plasma CVD method deposition thickness
, for example be 1500
Inherence (I-type) amorphous silicon film 22 and be 200 with the sputtering method deposition thickness
Silicon oxide layer 23.With ionic-implantation with
Dosage nickel ion is implanted amorphous silicon film (Fig. 2 (A)).
Then, the heat treatment step that amorphous silicon film is carried out under 550 ℃ the nitrogen atmosphere reaches 8 hours, with this amorphous silicon film of crystallization.After this, this silicon fiml is made figure, to form silicon island district 24.
Utilize tetraethoxy-silicane (
TEOS) and oxygen as raw material, forming thickness with plasma CVD method is 1000
Silicon oxide film 25, as the gate insulating film of silicon metal TFT.Except that these unstrpped gases, also used trichloroethylene (
) as one of raw material.Generating before this film, the oxygen that makes 400SCCM is 300 ℃ by a cell at underlayer temperature, and total pressure is 5Pa, and RF power is to produce plasma under the condition of 150W.This state was kept 10 minutes.After this with the oxygen of 300SCCM, the TEOS of 15SCCM and the trichloroethylene of 2SCCM import cell and are shaped with the film that carries out silicon oxide layer.In the film forming process, underlayer temperature, RF power and total pressure are respectively 300 ℃, 75W and 5Pa.Film be shaped finish after, 100Torr hydrogen is imported cell, and under 350 ℃, carries out hydrogen heat and handle and reach 35 minutes.
After this, be 3000 to 8000 by the sputtering method deposition thickness
, for example be 6000
Tantalum film.Can use titanium, tungsten, molybdenum or silicon substitute tantalum.It but, require this material that enough thermal endurances will be arranged, so that can stand activation operation afterwards.Preferably form the step of Si oxide 25 and tantalum film continuously.Then to the tantalum film graphing, to form the grid 26 of TFT.The surface of tantalum lead is through anodic oxidation, to form oxide layer 27 thereon.This anodic oxidation is to carry out in the Tartaric acid solution of 1 to 5% ethylene glycol.Resulting oxide layer has 2000
Thickness (Fig. 2 (B)).
By the plasma doping method, utilize grid impurity (phosphorus) to be implanted silicon area then as mask.In this operation, with hydrogen phosphide (
) as impurity gas, intensifying ring voltage is 80kv, dosage is
The result forms N type impurity range 28a and 28b.By the event of Chu anodic oxidation, grid 26 is moved apart impurity range 28 (Fig. 2 (C)).
By ionic-implantation, utilize grid as mask, with
Dosage (for example be
Nickel ion is implanted silicon area, the result, the concentration of N type impurity range 28a and 28b is approximately
(Fig. 2 (D)).
After this, under nitrogen atmosphere, carry out 450 ℃ of heat treatments of 4 hours, thus activator impurity.In this heat treatment step, because the implanted N type of nickel ion impurity range 28a and 28b, so heat treatment causes crystallization again to be easy to carry out.Like this, impurity range 28a and 28b are activated.
Then, with plasma CVD method TEOS being formed thickness as raw material is 2000
Silicon oxide layer 29 as one deck dielectric film, and in insulating barrier, form contact hole.Form source and drain electrode/ lead 30a and 30b by the metal material multilayer such as titanium nitride and the aluminium.The result of said process has promptly finished a semiconductor circuit (Fig. 2 (E)).
The thin-film transistor of Chan Shenging like this, when its grid voltage is 10V, field effect permeability (field effect mobility) be 70 to
Threshold voltage is that 2.5 to 4.0V leakage currents are
Or be added with-leakage current during 20V less than grid.
In the present embodiment, silicon metal TFT and non-crystalline silicon tft are formed on the same substrate with essentially identical method.Fig. 3 is the cross sectional view of all steps of production process that present embodiment carries out.At first, forming thickness with sputtering method on substrate (Corning 7059) 110 is 2000
The counterdie of making by Si oxide 111.Then, with plasma CVD method deposit 500 to 1500
Thick inherence (I type) amorphous silicon film 112 (for example 1500
Thick), then forming thickness selectively with sputtering method is 5 to 200
For example be 20
Nickel silicide film (molecular formula is Ni Six, wherein 0.4≤X≤2.5, for example X=2.0) 113 (Fig. 3 (A)).
Then, under a kind of hydrogen reducing atmosphere (partial pressure of hydrogen preferably from 0.1 to 1atm), carry out 500 ℃ of heat treatment steps of 4 hours, to realize crystallization.The result makes the amorphous silicon film crystallization below the nickel silicide film 113, to become crystal silicon film 112a.On the contrary, do not exist the silicon fiml district of nickel silicide film still shown in 112b, to be in amorphous state (Fig. 3 (B)).
With the silicon fiml graphing of photoetching process, to form silicon island district 114a (crystallization silicon area) and another silicon island district 114b (amorphous silicon region) to such acquisition.With sputtering method deposit 1,000
Thick silicon oxide film 115 is as gate insulating film.In this sputter procedure, as target, underlayer temperature is 200 to 400 ℃, for example is 350 ℃ with silica.This sputtering process carries out in the atmosphere of oxygen and argon, and wherein argon is 0 to 0.5 to the ratio of oxygen, and for example 0.1 or littler.After this, with decompression CVD method deposit silicon fiml (containing 0.1 to 2% phosphorus), its thickness is 6000 to 8000
, for example be 6000
Preferably form the step of silica and silicon fiml continuously.Then to the silicon fiml graphing, to form grid 116a, 116b and 116c (Fig. 3 (C)).
Then, with the plasma doping method and utilize grid impurity (phosphorus and boron) to be implanted silicon area as mask.Hydrogen phosphide in this operation (
) and diborane
As impurity gas, accelerating voltage is 60 to 90kv under former instance, for example be 80kv and be 40 to 80kv under latter instance, and for example be 65kv, dosage is
For example be to phosphorus
To boron be
As a result, form p type impurity district 117a and N type impurity range 117b and 117c.In the case, after mixing phosphorus impurities, with
Extremely
For example be
Dosage mix nickel impurity (Fig. 3 (D)).
Then, under hydrogen reduction atmosphere, carry out 500 ℃ of heat treatment steps of 4 hours, with activator impurity.In this process, because nickel ion spreads in the regional 114a that gives earlier crystallization, this heat treatment makes crystallization again be easy to carry out.In silicon island district 114b, also be mixed with nickel owing to mix among the phosphorus district 117C, equally so even under this degree heat treatment, also be enough to carry out crystallization.Like this, impurity range 117a to 117c is activated.The active region of non-crystalline silicon tft, then, forms as one deck dielectric film with plasma CVD method not by crystallization owing to do not have nickel in it, and thickness is 6000
Silicon oxide film 118, and in this dielectric film, form contact hole.Be formed for electrode/lead 119a of silicon metal TFT by the multiple layer metal material membrane such as titanium nitride and aluminium, 119b and 119c and be used for the electrode/lead 119d and the 119e of non-crystalline silicon tft.At last, under the 1atm hydrogen atmosphere, carry out 30 minutes heat treatment steps under 350 ℃.As the result of above-mentioned technology, finish semiconductor circuit (Fig. 3 (E)).
Measured the nickel concentration in each active region of TFT so obtain by ion microprobe (SIMS), the result observes simultaneously in silicon metal T FT, and nickel ion is
And in non-crystalline silicon tft the concentration of nickel less than the measuring limit value (
).
In the present embodiment, silicon metal TFT is used for external drive circuit and non-crystalline silicon tft is used for pixel circuit.Fig. 4 is the cross sectional view that shows all steps of production process that this embodiment carried out.Form tantalum film with sputtering method on substrate (Corning 7059) 120, its thickness is 500 to 2000
, for example be 1000
To the grid connection 121 of tantalum film graphing with the formation non-crystalline silicon tft.Is 1000 to 3000 the peripheral shape of tantalum wiring to form thickness with anode oxidation method
, for example be 1500
Anode oxide film 122.
Then, forming thickness with sputter is 2000
Silicon oxide film 123.The gate insulating film that silicon oxide film 123 had both served as non-crystalline silicon tft also serves as the underlying insulation film of silicon metal TFT.After this, with plasma CVD method deposition of amorphous silicon film 124, thickness is 200 to 1500
, for example be 500
When sheltering amorphous silicon film 124 with photoetching resist 125 when, by ionic-implantation nickel ion is implanted silicon fiml, comprise with generation
For example be
Nickel district 126.
The degree of depth in zone 126 is 200 to 500
Select acceleration energy to realize this degree of depth with the best approach.Prevent to serve as in the zone of active region among the implanted silicon metal TFT of nickel ion.Channel length is 20um or littler, is preferably 10 μ m or littler.When channel length is worth greater than this, just can not make the equal crystallization in whole active region (Fig. 4 (A)).
Under 0.1 to 1atm hydrogen atmosphere, carry out 8 hours heat treatment steps of 550 ℃ then, to realize crystallization.As the result of this crystallization operation, implant the district of nickel, be inserted in zone between two nickel implantation regions and their periphery (these districts are indicated by the 124a among Fig. 4 (B)) also by crystallization.550 ℃ of heat treatment results of following 8 hours laterally produce the crystalline solid of about 10um.On the contrary, the regional 124b that does not also implant nickel still is in amorphous state (Fig. 4 (B)).
To the silicon fiml graphing, to form silicon island district 127a (crystallization silicon area) and another silicon island district 127b (amorphous silicon region).With plasma CVD method with tetraethoxy-silicane (TEDS,
) and oxygen form 1000 as raw material
Thick silicon oxide film 128 is as the gate insulating film of silicon metal TFT.Except that these unstrpped gases, also have trichloroethylene (
) also as one of raw material.Forming before the film, the oxygen that makes 400SCCM is 300 ℃ at underlayer temperature then by a cell, and total pressure 5Pa and RF power are to produce plasma under the condition of 150W.This state was kept 10 minutes.After this, with the oxygen of 300SCCM, the TEOS of 15SCCM and the trichloroethylene of 2SCCM import cell and are shaped with the film that carries out silicon oxide film.In this film forming process, underlayer temperature, RF power and total pressure are respectively 300 ℃, 75W and 5Pa.Finish after this film shaping,, and under 350 ℃, carry out 35 minutes hydrogen heat treatment the hydrogen importing cell of 100Torr.
After this, be 6000 to 8000 with the sputtering method deposition thickness
, for example 6000
Aluminium film (containing 2% silicon).Also available tantalum, titanium, tungsten or molybdenum substitution of Al.Preferably form the step of silica 128 and aluminium film continuously.Then, to grid 129a and the 129b of aluminium film graphing with formation TFT.Anodic oxidation is carried out on aluminum steel bar surface, to form oxide layer thereon.Anodic oxidation is to carry out in the Tartaric acid solution of 1 to 5% ethylene glycol.Resulting oxidated layer thickness is 2000A.By exposing,, on the silica of non-crystalline silicon tft, form photoetching mask 130 against corrosion (Fig. 4 (C)) with respect to grid 121 self-aligned manners from substrate back
By the plasma doping method and utilize grid to make mask, a kind of impurity (phosphorus) is injected silicon area then.In this operation, with hydrogen phosphide (
) as impurity gas, accelerating voltage is 60 to 90kv, for example is 80kv, dosage is
For example be
As a result, form N type impurity range 131a and 131c.After this, the silicon metal TFT in left side (N-channel TFT) and non-crystalline silicon tft (matrix district) are sheltered by a kind of photoresist and the silicon area of the silicon metal TFT (P-channel TFT) on the implanted right side of impurity (boron).In this operation, as impurity gas, accelerating voltage is 50 to 80kv, for example is 65kv with diborane.Dosage is
For example be
It is greater than the dosage of the phosphorus of having implanted in advance.So just, formed p type impurity district 131b.
After this, activate these impurity by the laser heat facture.Adopted KrF excimer laser (wavelength is 248nm, and pulsewidth is 20ns) as for laser.Also available on the other hand such as XeF excimer laser (wavelength is 353nm), Xecl excimer laser (wavelength is 308nm), or ArF excimer laser (wavelength is 193nm) waits other lasers.The energy density of laser be 200 to
For example be
Every 2 to 10 ranges by the irradiation laser device for example are 2 ranges.During laser irradiation, substrate can be heated to about 200 to 450 ℃.Under the situation of heated substrate, should notice that optimum capacity density becomes with temperature is different.The active region of non-crystalline silicon tft not by crystallization because of mask 130 is arranged on it.Therefore, the impurity range of the impurity range 131a of silicon metal TFT and 131b and non-crystalline silicon tft be activated (Fig. 4 (D)).
Then, by plasma CVD method, adopting TEOS to form thickness as raw material is 2000
Silicon oxide film 132 as one deck dielectric film.With the sputtering method deposition thickness is 500 to 1000
, for example be 800
Indium tin oxidation (ITO) film.The ITO film is carried out etching, in insulating film layer 132, form contact hole to form pixel capacitors 133.Use the source and the drain electrode/lead 134a of multiple layer metal material membrane formation silicon metal TFT (external drive circuit) usefulness such as titanium nitride power aluminium, 134b and 134c and electrode/lead 134d and the 134e that is used for non-crystalline silicon tft (pixel circuit).The said process result just produces a semiconductor circuit (Fig. 4 (E)).
In the semiconductor circuit of producing like this, all performances of silicon metal TFT (external drive circuit) are all no less than all performances of the TFT that all steps produced by 600 ℃ of traditional heat treatment crystallization processes.For example, confirmed under drain voltage 15v, to be operated in by the shift register that this embodiment produces
And under drain voltage 17v condition, operate in 16MHz, moreover with regard to reliability test, also not finding has any difference between the shift register of this shift register and prior art.
With regard to the performance of non-crystalline silicon tft (pixel circuit), leakage current is
Or it is littler.
According to the present invention, because the activation of the impurity of mixing in the crystallization of amorphous silicon and the silicon all is carrying out under 400 to 550 ℃ low temperature and lasting short period such as 4 hours, so can improve productivity ratio.When with 600 ℃ of conventional method utilizations or more during the technology of high temperature, can cause glass substrate to be shunk and cause the problem that finished product damages.Can easily solve this class problem according to the present invention.
This means and to handle a large-sized substrate at one time.In other words, when handling large-sized substrate, can from a substrate, cut out many semiconductor circuits (matrix circuit etc.) thus can reduce unit cost greatly.When this characteristic is applied to LCD, just might promotes mass productivity and improve all characteristics.Just as described above, the present invention industrial be very favourable.
Moreover can form with the silicon metal TFT of high speed operation with low leakage current by same technical process on same substrate according to the present invention is the non-crystalline silicon tft of feature.When this characteristic was applied to LCD, it was possible strengthening mass productivity and improving properties of product.
Claims (11)
1. the formation method of a thin-film transistor is characterized in that may further comprise the steps:
Form a silicon fiml, this silicon fiml belongs to armorphous on substrate;
Supply to give a kind of catalytic elements that promotes crystallization to silicon fiml;
Make the silicon fiml annealing of having adopted described catalytic elements, and with the silicon fiml crystallization;
On the silicon fiml of crystallization, form a grid;
Silicon fiml to crystallization is provided with impurity;
On a plurality of parts of the silicon fiml of crystallization, form the material that contains catalytic elements; And
Remove the part of material.
2. the formation method of a thin-film transistor is characterized in that may further comprise the steps:
Form a silicon fiml, this silicon fiml belongs to armorphous on substrate;
On silicon fiml, form a gate insulating film;
Supply to give a kind of catalytic elements that promotes crystallization to silicon fiml;
Make the silicon fiml annealing of having adopted described catalytic elements, and with the silicon fiml crystallization;
On the silicon fiml of crystallization, form a grid;
By described gate insulating film the silicon fiml of crystallization is provided with impurity;
On a plurality of parts of the silicon fiml of crystallization, form the material that contains catalytic elements; And
Remove the part of material.
3. the formation method of a thin-film transistor is characterized in that may further comprise the steps:
Form a silicon fiml, this silicon fiml belongs to armorphous on substrate;
On silicon fiml, form a gate insulating film;
Supply to give a kind of catalytic elements that promotes crystallization to silicon fiml;
Make the silicon fiml annealing of having adopted described catalytic elements, and with the silicon fiml crystallization;
On the silicon fiml of crystallization, form a grid;
Silicon fiml to crystallization is provided with impurity;
The part of etch-gate dielectric film;
On a plurality of parts of the silicon fiml of crystallization, form the material that contains catalytic elements; And
Remove the part of material.
4. according to the formation method of the described thin-film transistor of arbitrary claim of claim 1-3, it is characterized in that: from the set that nickel, iron, cobalt, platinum are formed, select described catalytic elements.
5. according to the formation method of the described thin-film transistor of arbitrary claim of claim 1-3, it is characterized in that: described material is a kind of nickel silicide film.
6. according to the formation method of the described thin-film transistor of arbitrary claim of claim 1-3, it is characterized in that: described material is a kind of compound of being made up of described catalytic elements and silicon.
7. according to the formation method of the described thin-film transistor of arbitrary claim of claim 1-3, it is characterized in that: the described catalytic elements that promotes crystallization with ion implantation for giving described silicon fiml.
8. according to the formation method of the described thin-film transistor of arbitrary claim of claim 1-3, it is characterized in that also comprising: after removing described material part, make silicon fiml annealing, this impurity is activated under than the also low temperature of the temperature that makes the silicon fiml crystallization simultaneously.
9. according to the formation method of the described thin-film transistor of arbitrary claim of claim 1-3, it is characterized in that: include source region, source region and drain region for the silicon fiml that gives impurity, the catalytic elements concentration of the catalytic elements concentration ratio active area in source region and drain region is taller.
The 10 formation methods according to the described thin-film transistor of arbitrary claim of claim 1-3, it is characterized in that: described impurity is phosphorus or boron.
11 formation methods according to the described thin-film transistor of arbitrary claim of claim 1-3, it is characterized in that: the described material that contains described catalytic elements is by on the full wafer area on the substrate silicon and catalytic elements being set, and on described a plurality of parts of silicon fiml, form.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP79000/93 | 1993-03-12 | ||
| JP07899993A JP3369244B2 (en) | 1993-03-12 | 1993-03-12 | Thin film transistor |
| JP78999/93 | 1993-03-12 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB981163203A Division CN1221018C (en) | 1993-03-12 | 1994-03-12 | Transistor, semiconductor circuit and making method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1741257A CN1741257A (en) | 2006-03-01 |
| CN100437945C true CN100437945C (en) | 2008-11-26 |
Family
ID=13677596
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100919197A Expired - Lifetime CN100437945C (en) | 1993-03-12 | 1994-03-12 | Method for producing transistor and semiconductor device circuit |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP3369244B2 (en) |
| CN (1) | CN100437945C (en) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3535205B2 (en) * | 1993-03-22 | 2004-06-07 | 株式会社半導体エネルギー研究所 | Method for manufacturing thin film transistor |
| JP3347804B2 (en) * | 1993-03-22 | 2002-11-20 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor circuit |
| JP3329512B2 (en) * | 1993-03-22 | 2002-09-30 | 株式会社半導体エネルギー研究所 | Semiconductor circuit and manufacturing method thereof |
| JP3402380B2 (en) * | 1993-03-22 | 2003-05-06 | 株式会社半導体エネルギー研究所 | Semiconductor circuit and manufacturing method thereof |
| JP3190520B2 (en) | 1994-06-14 | 2001-07-23 | 株式会社半導体エネルギー研究所 | Semiconductor device and manufacturing method thereof |
| US6300659B1 (en) | 1994-09-30 | 2001-10-09 | Semiconductor Energy Laboratory Co., Ltd. | Thin-film transistor and fabrication method for same |
| KR100531556B1 (en) * | 1994-11-26 | 2006-02-28 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device manufacturing method |
| JPH08153879A (en) | 1994-11-26 | 1996-06-11 | Semiconductor Energy Lab Co Ltd | Fabrication of semiconductor device |
| US5977559A (en) * | 1995-09-29 | 1999-11-02 | Semiconductor Energy Laboratory Co., Ltd. | Thin-film transistor having a catalyst element in its active regions |
| TW451284B (en) * | 1996-10-15 | 2001-08-21 | Semiconductor Energy Lab | Semiconductor device and method of manufacturing the same |
| US6541793B2 (en) | 1997-05-30 | 2003-04-01 | Semiconductor Energy Laboratory Co., Ltd. | Thin-film transistor and semiconductor device using thin-film transistors |
| JP3376247B2 (en) * | 1997-05-30 | 2003-02-10 | 株式会社半導体エネルギー研究所 | Thin film transistor and semiconductor device using thin film transistor |
| JP4389359B2 (en) | 2000-06-23 | 2009-12-24 | 日本電気株式会社 | Thin film transistor and manufacturing method thereof |
| KR101084242B1 (en) * | 2010-01-14 | 2011-11-16 | 삼성모바일디스플레이주식회사 | Organic light emitting diode display and method for manufacturing the same |
| CN109599343A (en) * | 2018-12-25 | 2019-04-09 | 惠科股份有限公司 | Thin film transistor and its manufacturing method |
| CN109727875A (en) * | 2018-12-25 | 2019-05-07 | 惠科股份有限公司 | A kind of production method and display panel of thin film transistor (TFT) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4727044A (en) * | 1984-05-18 | 1988-02-23 | Semiconductor Energy Laboratory Co., Ltd. | Method of making a thin film transistor with laser recrystallized source and drain |
| US4746628A (en) * | 1983-08-26 | 1988-05-24 | Sharp Kabushiki Kaisha | Method for making a thin film transistor |
| US5124769A (en) * | 1990-03-02 | 1992-06-23 | Nippon Telegraph And Telephone Corporation | Thin film transistor |
| US5147826A (en) * | 1990-08-06 | 1992-09-15 | The Pennsylvania Research Corporation | Low temperature crystallization and pattering of amorphous silicon films |
| US5165075A (en) * | 1990-12-10 | 1992-11-17 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optic device having pairs of complementary transistors |
-
1993
- 1993-03-12 JP JP07899993A patent/JP3369244B2/en not_active Expired - Lifetime
-
1994
- 1994-03-12 CN CNB2005100919197A patent/CN100437945C/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4746628A (en) * | 1983-08-26 | 1988-05-24 | Sharp Kabushiki Kaisha | Method for making a thin film transistor |
| US4727044A (en) * | 1984-05-18 | 1988-02-23 | Semiconductor Energy Laboratory Co., Ltd. | Method of making a thin film transistor with laser recrystallized source and drain |
| US5124769A (en) * | 1990-03-02 | 1992-06-23 | Nippon Telegraph And Telephone Corporation | Thin film transistor |
| US5147826A (en) * | 1990-08-06 | 1992-09-15 | The Pennsylvania Research Corporation | Low temperature crystallization and pattering of amorphous silicon films |
| US5165075A (en) * | 1990-12-10 | 1992-11-17 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optic device having pairs of complementary transistors |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1741257A (en) | 2006-03-01 |
| JPH06267980A (en) | 1994-09-22 |
| JP3369244B2 (en) | 2003-01-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1221018C (en) | Transistor, semiconductor circuit and making method thereof | |
| CN100437945C (en) | Method for producing transistor and semiconductor device circuit | |
| CN1542929B (en) | Process for fabricating Semiconductor device | |
| CN1136612C (en) | Semiconductor circuits and manufacture thereof | |
| JP3637069B2 (en) | Method for manufacturing semiconductor device | |
| CN1054942C (en) | Semiconductor device and method of manufacturing the same | |
| US5677549A (en) | Semiconductor device having a plurality of crystalline thin film transistors | |
| US6028326A (en) | Thin film transistor including a catalytic element for promoting crystallization of a semiconductor film | |
| CN1893001B (en) | Method for manufacturing semiconductor device | |
| JP3869189B2 (en) | Method for manufacturing thin film transistor | |
| JPH08213634A (en) | Semiconductor device and its manufacture | |
| JP3359691B2 (en) | Method for manufacturing thin film transistor | |
| JP3535465B2 (en) | Method for manufacturing semiconductor device | |
| JP3333489B2 (en) | Method for manufacturing thin film transistor | |
| JP3535463B2 (en) | Method for manufacturing semiconductor circuit | |
| JP3362023B2 (en) | Method for manufacturing semiconductor device | |
| JP2000269514A (en) | Thin film transistor and its manufacture | |
| JP2000269502A (en) | Semiconductor device | |
| JPH11330488A (en) | Semiconductor device and its manufacture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CX01 | Expiry of patent term |
Expiration termination date: 20140312 Granted publication date: 20081126 |