CN100437981C - Non-volatility memory body and mfg. method and operating method thereof - Google Patents
Non-volatility memory body and mfg. method and operating method thereof Download PDFInfo
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- CN100437981C CN100437981C CNB2005100694051A CN200510069405A CN100437981C CN 100437981 C CN100437981 C CN 100437981C CN B2005100694051 A CNB2005100694051 A CN B2005100694051A CN 200510069405 A CN200510069405 A CN 200510069405A CN 100437981 C CN100437981 C CN 100437981C
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Abstract
The present invention relates to a non-volatile memory, and the production and the operation methods thereof. The production method of the non-volatile memory is that a stacking structure is formed on a substrate first, and the stacking structure comprises a grid dielectric layer on the lower layer and a control grid positioned on the grid dielectric layer. Then, a first, a second and a third dielectric layers are formed respectively on the top and a lateral wall of the stacking structure, and the exposed part of the substrate. Finally, one pair of charge storage layers by which part of the top of the stacking structure and the lateral wall of the stacking structure are covered respectively are formed on the substrate, wherein a gap is formed between the charge storage layers.
Description
Technical field
The present invention relates to a kind of memory component and manufacture method thereof and method of operation, particularly relate to a kind of nonvolatile memory and manufacture method thereof and method of operation.
Background technology
Nonvolatile memory is owing to have and can repeatedly carry out the actions such as depositing in, read, wipe of data, and the data that deposits in the advantage that also can not disappear after outage.Therefore, become PC and electronic equipment a kind of non-volatile memory device of extensively adopting.
Typical non-volatile memory device is to make floating grid (FloatingGate) and the control grid (Control Gate) that is positioned at the floating grid top with doped polycrystalline silicon.And floating grid and control are to be separated by with gate dielectric layer between the grid, and between floating grid and substrate being that tunneling layer is separated by.In addition, more there are source area and drain region to be configured in the control grid substrate on two sides.
When memory being write the operation of (Write) data, be by applying bias voltage, so that electronics injects floating grid in control grid, source area and drain region.During data in reading memory, be on the control grid, to apply operating voltage, the electriferous state of floating grid can influence the ON/OFF of its lower channel (Channel) at this moment, and is used as the foundation of interpretation data value for " 0 " or " 1 " by the ON/OFF of this passage.When memory carry out data wipe (Erase) time, it is relative current potential raising with substrate, source area, drain region or control grid, utilizing tunneling effect to make electronics pass tunneling layer and to drain into (being Substrate Erase) in the substrate, or pass gate dielectric layer and drain in the control grid by floating grid.
Summary of the invention
The objective of the invention is to, a kind of manufacture method of new nonvolatile memory is provided, technical problem to be solved is to make it can simplify processing procedure, thereby reduces the cost expenditure, thereby is suitable for practicality more.
Another object of the present invention is to, a kind of nonvolatile memory of new structure is provided, technical problem to be solved is to make its integration that element can be provided, and this nonvolatile memory can be used as multistage memory and use, thereby is suitable for practicality more.
A further object of the present invention is, a kind of method of operation of nonvolatile memory is provided, and technical problem to be solved is to make it can reduce the required voltage of control grid, thereby is suitable for practicality more.
An also purpose of the present invention is, a kind of method of operation of nonvolatile memory is provided, and technical problem to be solved is to make it can reduce the required voltage of control grid, thereby is suitable for practicality more, and has the value on the industry.
The present invention proposes a kind of manufacture method of nonvolatile memory, and the method is to form stacked structure prior to substrate, and this stacked structure comprises the gate dielectric and position control grid thereon of lower floor.Then, in the top of stacked structure, sidewall and exposed substrate, form first dielectric layer, second dielectric layer and the 3rd dielectric layer respectively.Afterwards, in substrate, form a pair of electric charge storage layer, cover the part top and the sidewall of stacked structure respectively, wherein between each electric charge storage layer at a distance of one first gap.
Manufacture method according to the described nonvolatile memory of preferred embodiment of the present invention, above-mentioned when forming electric charge storage layer, more be included in this to forming a pair of auxiliary grid on the electric charge storage layer substrate on two sides, wherein one second gap apart between each auxiliary grid and each electric charge storage layer.
According to the manufacture method of the described nonvolatile memory of preferred embodiment of the present invention, more be included in this to forming source area and drain region in the substrate on two sides of electric charge storage layer respectively.
The present invention proposes a kind of nonvolatile memory, and it is by substrate, stacked structure, a pair of electric charge storage layer, first dielectric layer, second dielectric layer and the 3rd dielectric layer.Wherein, stacked structure is configured in the substrate, and this stacked structure comprises the gate dielectric and position control grid thereon of lower floor.This covers respectively on stacked structure part top and the sidewall electric charge storage layer, and between each electric charge storage layer at a distance of one first gap.First dielectric layer is configured between stacked structure top and each electric charge storage layer.Second dielectric layer is configured between stacked structure sidewall and each electric charge storage layer.The 3rd dielectric layer is configured between each electric charge storage layer and the substrate.
According to the described nonvolatile memory of preferred embodiment of the present invention, more comprise a pair of auxiliary grid and the 4th dielectric layer.Wherein, auxiliary grid is configured in this on the electric charge storage layer substrate on two sides, and with each electric charge storage layer at a distance of second gap.The 4th dielectric layer is configured between each auxiliary grid and the substrate.
According to the described nonvolatile memory of preferred embodiment of the present invention, more comprise an one source pole district and a drain region, be configured in this respectively in the electric charge storage layer substrate on two sides.
The present invention proposes a kind of method of operation of nonvolatile memory, be suitable for a nonvolatile memory, this nonvolatile memory comprises at least and is positioned at suprabasil control grid, respectively first electric charge storage layer and second electric charge storage layer of Coverage Control grid part top and sidewall, be positioned at control the grid both sides and with each electric charge storage layer apart first auxiliary grid and second auxiliary grid in a gap.This method of operation comprises: when carrying out first programming, apply first voltage in the control grid, apply second voltage and make the substrate that is positioned at first auxiliary grid below form the drain electrode reversal zone in first auxiliary grid, apply tertiary voltage in the drain electrode reversal zone, and setting second auxiliary grid becomes it to float, wherein magnitude of voltage, is entered in first electric charge storage layer by the drain electrode reversal zone so that electronics is worn tunnel by FN to being tertiary voltage, second voltage and first voltage greatly in regular turn by little.When carrying out second programming, apply first voltage in the control grid, apply second voltage and make the substrate that is positioned at second auxiliary grid below form the source electrode reversal zone in second auxiliary grid, apply tertiary voltage in the source electrode reversal zone, and setting first auxiliary grid becomes it to float, entered in second electric charge storage layer by the source electrode reversal zone so that electronics is worn tunnel by FN.
The present invention proposes a kind of method of operation of nonvolatile memory, be suitable for a nonvolatile memory, this nonvolatile memory comprises at least and is positioned at suprabasil control grid, first electric charge storage layer and second electric charge storage layer of Coverage Control grid part top and sidewall lay respectively at source area and drain region in second electric charge storage layer and the first electric charge storage layer substrate on two sides respectively.This method of operation comprises: when carrying out first programming, apply the 15 voltage in the control grid, apply the 16 voltage in the drain region, and the setting source area becomes it and floats, wherein magnitude of voltage, is entered in first electric charge storage layer by the drain region so that electronics is worn tunnel by FN to being the 16 voltage and the 15 voltage greatly in regular turn by little.Carrying out second when programming, applying the 15 voltage, applying the 16 voltage, and setting the drain region and it is become float, enter in second electric charge storage layer by source area so that electronics is worn tunnel by FN in source area in the control grid.
Because the present invention is made in electric charge storage layer on the control grid, therefore can solve when carrying out memory erase, the problem of over-erasure, thus improve the element reliability.And, because therefore the close together between control grid and the substrate is controlled the required voltage of grid and can be reduced.In addition, because the present invention has two electric charge storage layers separated from one another, therefore can be used as multistage memory and use.
The present invention compared with prior art has tangible advantage and beneficial effect.Via as can be known above-mentioned, the invention relates to a kind of nonvolatile memory and manufacture method thereof and method of operation.The manufacture method of this nonvolatile memory is to form stacked structure prior to substrate, and this stacked structure comprises the gate dielectric and position control grid thereon of lower floor.Then, in the top of stacked structure, sidewall and exposed substrate, form first dielectric layer, second dielectric layer and the 3rd dielectric layer respectively.Afterwards, in substrate, form a pair of electric charge storage layer, cover the part top and the sidewall of stacked structure respectively, wherein between each electric charge storage layer at a distance of a gap.
By technique scheme, nonvolatile memory of the present invention and manufacture method thereof and method of operation have following advantage at least:
1. because the present invention is disposed at electric charge storage layer on the control grid, therefore can solve when carrying out memory erase, the problem of over-erasure, thus improve the element reliability.
2. because the present invention has two electric charge storage layers separated from one another, therefore can use and make memory of the present invention can be used as multi-memory respectively at storing one in this two electric charge storage layer.
Since the present invention with the usefulness of formed auxiliary grid as bit line, and apply the voltage of appropriateness in auxiliary grid, can make the substrate of its below become the source area or the drain region of counter-rotating, so the size that can effectively dwindle memory component, thereby the element integration improved.
4. owing to the close together between its control grid of nonvolatile memory of the present invention and the substrate, therefore control the required voltage of grid and also can reduce.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Figure 1A to Fig. 1 D is the manufacturing process generalized section according to a kind of nonvolatile memory of a preferred embodiment of the present invention.
Fig. 2 A to Fig. 2 D is the manufacturing process generalized section according to a kind of nonvolatile memory of another preferred embodiment of the present invention.
Fig. 3 A to Fig. 3 E is the manufacturing process generalized section according to a kind of nonvolatile memory of the another preferred embodiment of the present invention.
Fig. 4 A is the generalized section according to a kind of nonvolatile memory of a preferred embodiment of the present invention.
Fig. 4 B is the generalized section according to a kind of nonvolatile memory of another preferred embodiment of the present invention.
Fig. 5 A is the generalized section according to a kind of nonvolatile memory of the another preferred embodiment of the present invention.
Fig. 5 B is according to the present invention's generalized section of a kind of nonvolatile memory of a preferred embodiment again.
Fig. 6 A is the generalized section according to a kind of nonvolatile memory of another preferred embodiment of the present invention.
Fig. 6 B is the generalized section according to a kind of nonvolatile memory of the another preferred embodiment of the present invention.
Fig. 7 A and 7B are its schematic diagrames of programming of nonvolatile memory of Fig. 4 A.
Fig. 8 A and 8B are its schematic diagrames in the programming of carrying out another form of nonvolatile memory of Fig. 4 A.
Fig. 9 A and 9B are its schematic diagrames of wiping of nonvolatile memory of Fig. 4 A.
Figure 10 A and 10B are its schematic diagrames that is reading of nonvolatile memory of Fig. 4 A.
Figure 11 A and 11B are its schematic diagrames of programming of nonvolatile memory of Fig. 4 B.
Figure 12 A and 12B are its schematic diagrames in the programming of carrying out another form of nonvolatile memory of Fig. 4 B.
Figure 13 A and 13B are its schematic diagrames of wiping of nonvolatile memory of Fig. 4 B.
Figure 14 A and 14B are its schematic diagrames that is reading of nonvolatile memory of Fig. 4 B.
100,400: substrate 102,300,402: stacked structure
104,412: gate dielectric 106,414: the control grid
108,200,202,206,310,312,316: dielectric materials layer
110: conductor material layer
112a, 112b, 404a, 404b: electric charge storage layer
114a, 114b, 418a, 418b: auxiliary grid
113,116,416,420,422: the gap
115a, 424a: source area 115b, 424b: drain region
204,314: composite dielectric clearance wall 302,500,600: dielectric stack lamination
304,308,502,506,602,606: silicon oxide layer
306,504,604: silicon nitride layer 406,408,410,420: dielectric layer
700a: drain electrode reversal zone 700b: source electrode reversal zone
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to nonvolatile memory and manufacture method and its embodiment of method of operation, structure, method, step, feature and the effect thereof that foundation the present invention proposes, describe in detail as after.
Figure 1A to Fig. 1 D is the manufacturing process generalized section that illustrates according to a kind of nonvolatile memory of a preferred embodiment of the present invention.
Please refer to Figure 1A, form stacked structure 102 in substrate 100, this stacked structure 102 comprises the gate dielectric 104 and position control grid 106 thereon of lower floor.In the present embodiment, gate dielectric 104 can be the individual layer dielectric layer, and it for example is a silicon oxide layer.In another embodiment, gate dielectric 104 can be the dielectric stack lamination of multilayer, and it for example is the silicon oxide/silicon nitride/silicon oxide stack layer.In addition, the material of control grid 106 for example is polysilicon, doped polycrystalline silicon or other suitable conductor materials.
Then, please refer to Figure 1B, in substrate 100, form dielectric materials layer 108, cover stacked structure 102 and substrate 100.The material of dielectric materials layer 108 for example is silica or other suitable materials, and its formation method for example is thermal oxidation method, the long-pending method in chemical gaseous phase Shen or other suitable methods.
Then, in substrate 100, form conductor material layer 110.The material of conductor material layer 110 for example is polysilicon, doped polycrystalline silicon or other suitable conductor materials, and its formation method long-pending processing procedure that for example is chemical gaseous phase Shen.
Afterwards, please refer to Fig. 1 C, definition conductor material layer 110 to form a pair of electric charge storage layer 112a, 112b in substrate 100, covers the part top and the sidewall of stacked structure 102, and between electric charge storage layer 112a, the 112b at a distance of a gap 113.And on this electric charge storage layer 112a, 112b substrate on two sides 100, form a pair of auxiliary grid 114a, 114b, wherein a gap 116 apart between auxiliary grid 114a, 114b and electric charge storage layer 112a, the 112b.
What deserves to be mentioned is that above-mentioned its material of electric charge storage layer 112a, 112b is not limited to conductor material, it also can be high dielectric constant materials, and it for example is the material that silicon nitride or aluminium oxide etc. can be used as Charge Storage.When if the material of electric charge storage layer 112a, 112b is high dielectric constant materials, then electric charge storage layer 112a, 112b need to carry out in different steps with the making of auxiliary grid 114a, 114b.That is to say that electric charge storage layer 112a, 112b need to define it respectively by different light shield processing procedures with auxiliary grid 114a, 114b.
In addition, in another embodiment, more can shown in Fig. 1 D, only define electric charge storage layer 112a, 112b among Fig. 1 C.And, after electric charge storage layer 112a, 112b form, on electric charge storage layer 112a, 112b substrate on two sides 100, form source area 115a and drain region 115b more respectively, to form the memory of another kind of kenel of the present invention.Wherein, the formation method of source area 115a and drain region 115b for example is to serve as that cover curtain carries out ion implantation manufacture process with stacked structure 102, electric charge storage layer 112a, 112b.
In addition, it should be noted that, this moment, the dielectric materials layer 108 between stacked structure 102 tops and electric charge storage layer 112a, 112b can be used as gate dielectric layer usefulness, be positioned at the usefulness that substrate 100 lip-deep dielectric materials layers 108 can be used as tunneling layer, the dielectric materials layer 108 between stacked structure 102 sidewalls and electric charge storage layer 112a, 112b can be used as the usefulness of insulating gap wall.And, being not limited to one deck as its rete number of dielectric materials layer of gate dielectric layer or insulating gap wall, it also can be the dielectric stack lamination of multilayer.Below be to explain for two example two.
In the following embodiments, the dielectric materials layer of insulating gap wall for example is the dielectric stack lamination of multilayer.Please refer to Fig. 2 A, be to form in the substrate 100 after the stacked structure 102, in substrate 100, form dielectric materials layer 200 and 202, cover stacked structure 102 and substrate 100.Wherein, the material of dielectric materials layer 200 for example is a silica, and the material of dielectric materials layer 202 for example is a silicon nitride.Afterwards, please refer to Fig. 2 B, remove the dielectric materials layer 200 and 202 of part, form a pair of composite dielectric clearance wall 204 with the sidewall in stacked structure 102, this moment can come out in stacked structure 102 tops.Then, please refer to Fig. 2 C, in substrate 100, form dielectric materials layer 206, cover stacked structure 102, composite dielectric clearance wall 204 and substrate 100.Wherein, the material of dielectric materials layer 206 for example is a silica.Then, part top and the sidewall in stacked structure 102 forms electric charge storage layer 112a, 112b again, and forms a pair of auxiliary grid 114a, 114b on this electric charge storage layer 112a, 112b substrate on two sides 100.Perhaps, in another embodiment, can shown in Fig. 2 D, on electric charge storage layer 112a, 112b substrate on two sides 100, form source area 115a and drain region 115b respectively.
In following another embodiment, the dielectric materials layer of gate dielectric layer and insulating gap wall for example all is the dielectric stack lamination of multilayer.Please refer to Fig. 3 A, form stacked structure 300 in substrate 100, this stacked structure 300 is gate dielectric 104, control grid 106 and dielectric stack lamination 302 by substrate 100 in regular turn.Wherein dielectric stack lamination 302 for example is silicon oxide layer 304/ silicon nitride layer 306/ silicon oxide layer 308 stack layers.Then, please refer to Fig. 3 B, in substrate 100, form dielectric materials layer 310 and 312, cover stacked structure 300 and substrate 100.Wherein, the material of dielectric materials layer 310 for example is a silica, and the material of dielectric materials layer 312 for example is a silicon nitride.Afterwards, please refer to Fig. 3 C, remove the dielectric materials layer 310 and 312 of part, form a pair of composite dielectric clearance wall 314 with the sidewall in stacked structure 300, can come out in silicon nitride layer 306 tops in the stacked structure 300 at this moment.Then, please refer to Fig. 3 D, in substrate 100, form dielectric materials layer 316, cover stacked structure 300, composite dielectric clearance wall 314 and substrate 100.Wherein, the material of dielectric materials layer 316 for example is a silica.Then, part top and the sidewall in stacked structure 300 forms electric charge storage layer 112a, 112b again, and forms a pair of auxiliary grid 114a, 114b on this electric charge storage layer 112a, 112b substrate on two sides 100.Perhaps, in another embodiment, can shown in Fig. 3 E, on electric charge storage layer 112a, 112b substrate on two sides 100, form source area 115a and drain region 115b respectively.
It below is the structure of explanation nonvolatile memory of the present invention.
Please refer to Fig. 4 A, nonvolatile memory of the present invention is to be made of substrate 400, stacked structure 402, a pair of electric charge storage layer 404a, 404b, 406,408,410 of dielectric layers.
Wherein, stacked structure 402 is configured in the substrate 400, and this stacked structure 402 comprises the gate dielectric 412 and position control grid 414 thereon of lower floor.In the present embodiment, gate dielectric 412 can be the individual layer dielectric layer, and it for example is a silicon oxide layer.In another embodiment, gate dielectric 412 can be the dielectric stack lamination of multilayer, and it for example is the silicon oxide/silicon nitride/silicon oxide stack layer.In addition, the material of control grid 414 for example is polysilicon, doped polycrystalline silicon or other suitable conductor materials.
In addition, electric charge storage layer 404a, 404b cover respectively on the part top and sidewall of stacked structure 402, and between each electric charge storage layer 404a, the 404b at a distance of a gap 416.Wherein the material of electric charge storage layer 404a, 404b comprises polysilicon or high dielectric constant materials, and high dielectric constant materials for example is the material that silicon nitride or aluminium oxide etc. can be used as Charge Storage.
In addition, dielectric layer 406 is configured between stacked structure 402 tops and each electric charge storage layer 404a, the 404b, and this dielectric layer 406 can be used as the usefulness of gate dielectric layer.The material of dielectric layer 406 for example is silica or other suitable materials.
In addition, dielectric layer 408 is configured between stacked structure 402 sidewalls and each electric charge storage layer 404a, the 404b, and this dielectric layer 408 can be used as the usefulness of insulating gap wall.The material of dielectric layer 408 for example is silica or other suitable materials.
In addition, dielectric layer 410 is configured between each electric charge storage layer 404a, 404b and the substrate 400, and this dielectric layer 410 can be used as the usefulness of tunneling layer.The material of dielectric layer 410 for example is silica or other suitable materials.
What deserves to be mentioned is that in one embodiment, nonvolatile memory of the present invention more includes a pair of auxiliary grid 418a, 418b and dielectric layer 420.Wherein, auxiliary grid 418a, 418b are configured in this on electric charge storage layer 404a, the 404b substrate on two sides 400, and with each electric charge storage layer 404a, 404b at a distance of gap 422.The material of auxiliary grid 418a, 418b for example is polysilicon or doped polycrystalline silicon.In addition, dielectric layer 420 is configured between each auxiliary grid 418a, 418b and the substrate 400.The material of dielectric layer 420 for example is silica or other suitable materials.
In addition, in another embodiment, nonvolatile memory of the present invention more can include source area 424a and drain region 424b shown in Fig. 4 B.This source area 424a and drain region 424b are configured in this respectively in electric charge storage layer 404a, the 404b substrate on two sides 200.
What deserves to be mentioned is that above-mentioned dielectric layer 408 is not limited to the dielectric layer of individual layer, it also can be the dielectric stack lamination 500 of multilayer shown in Fig. 5 A and Fig. 5 B.In Fig. 5 A and Fig. 5 B, dielectric stack lamination 500 for example is that silicon oxide layer 502/ silicon nitride layer 504/ silicon oxide layer 506 constitutes.In addition, can the dielectric stack lamination 500 of configuring multi-layer except stacked structure 402 sidewalls, its top is the dielectric stack lamination 600 of configurable multilayer (shown in Fig. 6 A and Fig. 6 B) also.That is to say that the dielectric layer 406 in Fig. 4 A and Fig. 4 B is the dielectric stack lamination 600 of multilayer, and this dielectric stack lamination 600 for example is that silicon oxide layer 602/ silicon nitride layer 604/ silicon oxide layer 606 constitutes.
Because the present invention is made in electric charge storage layer on the control grid, therefore can solve when carrying out memory erase, the problem of over-erasure, thus improve the element reliability.And, because therefore the close together between control grid and the substrate is controlled the required voltage of grid and can be reduced.
In addition, because the formed auxiliary grid of the present invention can be used as bit line, and on auxiliary grid, apply the voltage of appropriateness, can make the substrate of its below become the source area or the drain region of counter-rotating, so the size that can effectively dwindle memory component, thereby improve the element integration.
It below is the method for operation of the nonvolatile memory of key diagram 4A.Please refer to Fig. 7 A, when carrying out first programming, apply control voltage (Vg) in control grid 414; Apply boost voltage (Vag) and make the substrate 400 that is positioned at auxiliary grid 418a below form drain electrode reversal zone 700a in auxiliary grid 418a; Reversal zone 700a applies drain voltage (Vd) in drain electrode, and sets auxiliary grid 418b and it is become float, wherein magnitude of voltage by little to being drain voltage, boost voltage and control voltage greatly in regular turn.So can make electronics wear tunnel by FN is entered among the electric charge storage layer 404a by drain electrode reversal zone 700a.In one implemented, control voltage for example was 14 volts, and boost voltage for example is 8 volts, and drain voltage for example is 0 volt.
Then, please refer to Fig. 7 B, when carrying out second programming, can apply control voltage (Vg) in control grid 414; Apply boost voltage (Vag) and make the substrate 400 that is positioned at auxiliary grid 418b below form source electrode reversal zone 700b in auxiliary grid 418b; Apply source voltage (Vs) in source electrode reversal zone 700b, and set auxiliary grid 418a and it is become float, wherein magnitude of voltage by little to being source voltage, boost voltage and control voltage greatly in regular turn.So can make electronics wear tunnel by FN is entered among the electric charge storage layer 404b by source electrode reversal zone 700b.In one implemented, control voltage for example was 14 volts, and boost voltage for example is 8 volts, and source voltage for example is 0 volt.
Particularly,, therefore can in this two electric charge storage layer, deposit one respectively in, use and make memory of the present invention can be used as multistage memory because the present invention has two electric charge storage layer 404a, 404b.
Please refer to Fig. 8 A, in another embodiment, when carrying out first programming, can apply control voltage (Vg) in control grid 414; Apply boost voltage (Vag) in auxiliary grid 418a and 418b, and make the substrate 400 that is positioned at auxiliary grid 418a and 418b below form drain electrode reversal zone 700a and source electrode reversal zone 700b respectively; Reversal zone 700a applies drain voltage (Vd) in drain electrode, applies source voltage (Vs) in source electrode reversal zone 700b, wherein magnitude of voltage by little to being source voltage, drain voltage, control voltage and boost voltage greatly in regular turn.So can make electronics pass through the substrate 400 (channel region) of control grid 414 belows by source electrode reversal zone 700b, and enter among the electric charge storage layer 404a by channel hot electron effect (CHE).In one embodiment, control voltage for example is 5 volts, and boost voltage for example is 8 volts, and drain voltage for example is 4 volts, and source voltage for example is 0 volt.
Then, please refer to Fig. 8 B, when carrying out second programming, can apply control voltage (Vg) in control grid 414; Apply boost voltage (Vag) in auxiliary grid 418a and 418b, and make the substrate 400 that is positioned at auxiliary grid 418a and 418b below form drain electrode reversal zone 700a and source electrode reversal zone 700b respectively; Reversal zone 700a applies drain voltage (Vd) in drain electrode, applies source voltage (Vs) in source electrode reversal zone 700b, wherein magnitude of voltage by little to being drain voltage, source voltage, control voltage and boost voltage greatly in regular turn.So can make electronics pass through the substrate 400 (channel region) of control grid 414 belows by drain electrode reversal zone 700a, and enter among the electric charge storage layer 404b by channel hot electron effect (CHE).In one embodiment, control voltage for example is 5 volts, and boost voltage for example is 8 volts, and source voltage for example is 4 volts, and drain voltage for example is 0 volt.
In addition, please refer to Fig. 9 A, carrying out first when wiping, can apply control voltage (Vg) in control grid 414; Apply boost voltage (Vag) and make the substrate 400 that is positioned at auxiliary grid 418a below form drain electrode reversal zone 700a in auxiliary grid 418a; Reversal zone 700a applies drain voltage (Vd) in drain electrode; And set auxiliary grid 418b and it become float, wherein magnitude of voltage by little to being drain voltage, boost voltage and control voltage greatly in regular turn.So can make electronics wear tunnel by entering drain electrode reversal zone 700a among the electric charge storage layer 404a by-FN.In one embodiment, control voltage for example is-9 volts, and boost voltage for example is 8 volts, and drain voltage for example is 5 volts.
Then, please refer to Fig. 9 B, carrying out second when wiping, can apply control voltage (Vg) in control grid 414; Apply boost voltage (Vag) and make the substrate 400 that is positioned at auxiliary grid 418b below form source electrode reversal zone 700b in auxiliary grid 418b; Apply source voltage (Vs) in source electrode reversal zone 700b; And set auxiliary grid 418a and it become float, wherein magnitude of voltage by little to being source voltage, boost voltage and control voltage greatly in regular turn.So can make electronics wear tunnel by entering source electrode reversal zone 700b among the electric charge storage layer 404b by-FN.In one embodiment, control voltage for example is-9 volts, and boost voltage for example is 8 volts, and source voltage for example is 5 volts.
Particularly,, therefore can solve when carrying out memory erase because the present invention is disposed at electric charge storage layer 404a, 404b on the control grid 414, the problem of over-erasure, thus improve the element reliability.
In addition, please refer to Figure 10 A, carrying out first when reading, apply control voltage (Vg) in control grid 414; Apply boost voltage (Vag) in auxiliary grid 418a and 418b, and make the substrate 400 that is positioned at auxiliary grid 418a and 418b below form drain electrode reversal zone 700a and source electrode reversal zone 700b respectively; Apply source voltage (Vs) in source electrode reversal zone 700b; Reversal zone 700a applies drain voltage (Vd) in drain electrode, wherein magnitude of voltage by little to be drain voltage, source voltage, control voltage and boost voltage greatly in regular turn, with read be stored in electric charge storage layer 404a.In one embodiment, control voltage for example is 3 volts, and boost voltage for example is 8 volts, and drain voltage for example is 0 volt, and source voltage for example is 1.6 volts.
Then, please refer to Figure 10 B, carrying out second when reading, apply control voltage (Vg) in control grid 414; Apply boost voltage (Vag) in auxiliary grid 418a and 418b, and make the substrate 400 that is positioned at auxiliary grid 418a and 418b below form drain electrode reversal zone 700a and source electrode reversal zone 700b respectively; Apply source voltage (Vs) in source electrode reversal zone 700b; Reversal zone 700a applies drain voltage (Vd) in drain electrode, wherein magnitude of voltage by little to be source voltage, drain voltage, control voltage and boost voltage greatly in regular turn, with read be stored in electric charge storage layer 404b.In one embodiment, control voltage for example is 3 volts, and boost voltage for example is 8 volts, and source voltage for example is 0 volt, and drain voltage for example is 1.6 volts.
The method of operation of the nonvolatile memory of Fig. 4 B of the present invention below is described.Please refer to Figure 11 A, when carrying out first programming, apply control voltage (Vg) in control grid 414; Apply drain voltage (Vd) in drain region 424b, and set source area 424a and it is become float, wherein magnitude of voltage by little to be drain voltage greatly in regular turn and control voltage.So can make electronics wear tunnel by FN is entered among the electric charge storage layer 404a by drain region 424b.In one implemented, control voltage for example was 14 volts, and drain voltage for example is 0 volt.
Then, please refer to Figure 11 B, when carrying out second programming, can apply control voltage (Vg) in control grid 414; Apply source voltage (Vs) in source area 424a, and set drain region 424b and it is become float, wherein magnitude of voltage by little to be source voltage greatly in regular turn and control voltage.So can make electronics wear tunnel by FN is entered among the electric charge storage layer 404b by source area 424a.In one implemented, control voltage for example was 14 volts, and source voltage for example is 0 volt.
Particularly,, therefore can in this two electric charge storage layer, deposit one respectively in, use and make memory of the present invention can be used as multistage memory because the present invention has two electric charge storage layer 404a, 404b.
Please refer to Figure 12 A, in another embodiment, when carrying out first programming, can apply control voltage (Vg) in control grid 414; Apply drain voltage (Vd) in drain region 424b; Apply source voltage (Vs) in source area 424a, wherein magnitude of voltage by little to being source voltage, drain voltage and control voltage greatly in regular turn.So can make electronics pass through the substrate 400 (channel region) of control grid 414 belows by source area 424a, and enter among the electric charge storage layer 404a by channel hot electron effect (CHE).In one embodiment, control voltage for example is 5 volts, and drain voltage for example is 4 volts, and source voltage for example is 0 volt.
Then, please refer to Figure 12 B, when carrying out second programming, can apply control voltage (Vg) in control grid 414; Apply drain voltage (Vd) in drain region 424b; Apply source voltage (Vs) in source area 424a, wherein magnitude of voltage by little to being drain voltage, source voltage and control voltage greatly in regular turn.So can make electronics pass through the substrate 400 (channel region) of control grid 414 belows by drain region 424b, and enter among the electric charge storage layer 404b by channel hot electron effect (CHE).In one embodiment, control voltage for example is 5 volts, and source voltage for example is 4 volts, and drain voltage for example is 0 volt.
In addition, please refer to Figure 13 A, carrying out first when wiping, can apply control voltage (Vg) in control grid 414; Apply drain voltage (Vd) in drain region 424b; And set source area 424a and it become float, wherein magnitude of voltage by little to be drain voltage greatly in regular turn and control voltage.So can make electronics wear tunnel by entering drain region 424b among the electric charge storage layer 404a by-FN.In one embodiment, control voltage for example is-9 volts, and drain voltage for example is 5 volts.
Then, please refer to Figure 13 B, carrying out second when wiping, can apply control voltage (Vg) in control grid 414; Apply source voltage (Vs) in source area 424a; And set drain region 424b and it become float, wherein magnitude of voltage by little to be source voltage greatly in regular turn and control voltage.So can make electronics wear tunnel by entering source area 424a among the electric charge storage layer 404b by-FN.In one embodiment, control voltage for example is-9 volts, and source voltage for example is 5 volts.
Particularly,, therefore can solve when carrying out memory erase because the present invention is disposed at electric charge storage layer 404a, 404b on the control grid 414, the problem of over-erasure, thus improve the element reliability.
In addition, please refer to Figure 14 A, carrying out first when reading, apply control voltage (Vg) in control grid 414; Apply source voltage (Vs) in source area 424a; Apply drain voltage (Vd) in drain region 424b, wherein magnitude of voltage by little to be drain voltage, source voltage and control voltage greatly in regular turn, with read be stored in electric charge storage layer 404a.In one embodiment, control voltage for example is 3 volts, and drain voltage for example is 0 volt, and source voltage for example is 1.6 volts.
Then, please refer to Figure 14 B, carrying out second when reading, apply control voltage (Vg) in control grid 414; Apply source voltage (Vs) in source area 424a; Apply drain voltage (Vd) in drain region 424b, wherein magnitude of voltage by little to be source voltage, drain voltage and control voltage greatly in regular turn, with read be stored in electric charge storage layer 404b.In one embodiment, control voltage for example is 3 volts, and source voltage for example is 0 volt, and drain voltage for example is 1.6 volts.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the method that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, but every content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (18)
1, a kind of manufacture method of nonvolatile memory is characterized in that it may further comprise the steps:
Form a stacked structure in a substrate, this stacked structure comprises a gate dielectric and a position control grid thereon of lower floor;
In the top of this stacked structure, sidewall and exposed this substrate, form one first dielectric layer, one second dielectric layer and one the 3rd dielectric layer respectively;
In this substrate, form a pair of electric charge storage layer, cover the part top and the sidewall of this stacked structure respectively, wherein respectively between this electric charge storage layer at a distance of one first gap.
2, the manufacture method of nonvolatile memory according to claim 1, it is characterized in that wherein when forming this electric charge storage layer, more be included in this to forming a pair of auxiliary grid in this substrate of electric charge storage layer both sides, wherein respectively this auxiliary grid and one second gap apart between this electric charge storage layer respectively.
3, the manufacture method of nonvolatile memory according to claim 1, it is characterized in that wherein form this to electric charge storage layer after, more be included in this this substrate and form an one source pole district and a drain region respectively the both sides of electric charge storage layer.
4, the manufacture method of nonvolatile memory according to claim 1 is characterized in that the material of wherein said electric charge storage layer comprises polysilicon, silicon nitride or other high dielectric constant materials.
5, the manufacture method of nonvolatile memory according to claim 1 is characterized in that wherein said gate dielectric, this first dielectric layer and this second dielectric layer are the dielectric stack lamination of an individual layer dielectric layer or a multilayer.
6, a kind of nonvolatile memory is characterized in that it comprises:
One substrate;
One stacked structure is configured in this substrate, and this stacked structure comprises a gate dielectric and a position control grid thereon of lower floor;
A pair of electric charge storage layer covers respectively on this stacked structure part top and the sidewall, and respectively between this electric charge storage layer at a distance of one first gap;
One first dielectric layer is configured in this stacked structure top and respectively between this electric charge storage layer;
One second dielectric layer is configured in this stacked structure sidewall and respectively between this electric charge storage layer;
One the 3rd dielectric layer is configured in respectively between this electric charge storage layer and this substrate.
7, nonvolatile memory according to claim 6 is characterized in that more comprising:
A pair of auxiliary grid is configured in this this substrate to the electric charge storage layer both sides, and with this electric charge storage layer respectively at a distance of one second gap; And
One the 4th dielectric layer is configured in respectively between this auxiliary grid and this substrate.
8, nonvolatile memory according to claim 6 is characterized in that more comprising an one source pole district and a drain region, is configured in respectively in this this substrate to the electric charge storage layer both sides.
9, nonvolatile memory according to claim 6 is characterized in that the material of wherein said electric charge storage layer comprises polysilicon, silicon nitride or other high dielectric constant materials.
10, nonvolatile memory according to claim 6 is characterized in that wherein said gate dielectric, this first dielectric layer and this second dielectric layer are the dielectric stack lamination of an individual layer dielectric layer or a multilayer.
11, a kind of method of operation of nonvolatile memory, be suitable for a nonvolatile memory, this nonvolatile memory comprises that at least being positioned at one suprabasil one controls grid, cover one first electric charge storage layer and one second electric charge storage layer of this control grid part top and sidewall respectively, be positioned at these control grid both sides and with one first auxiliary grid and one second auxiliary grid of this electric charge storage layer respectively at a distance of a gap, it is characterized in that this method of operation comprises:
When carrying out first programming, apply one first voltage in this control grid, apply one second voltage and make this substrate that is positioned at this first auxiliary grid below form a drain electrode reversal zone in this first auxiliary grid, apply a tertiary voltage in this drain electrode reversal zone, and setting this second auxiliary grid becomes it to float, wherein magnitude of voltage, is entered in this first electric charge storage layer by this drain electrode reversal zone so that electronics is worn tunnel by FN to being this tertiary voltage, this second voltage and this first voltage greatly in regular turn by little; And
When carrying out second programming, apply this first voltage in this control grid, apply this second voltage and make this substrate that is positioned at this second auxiliary grid below form the one source pole reversal zone in this second auxiliary grid, apply this tertiary voltage in this source electrode reversal zone, and setting this first auxiliary grid becomes it to float, entered in this second electric charge storage layer by this source electrode reversal zone so that electronics is worn tunnel by FN.
12, the method for operation of nonvolatile memory according to claim 11 is characterized in that wherein
When carrying out first programming, apply one the 4th voltage in this control grid, apply one the 5th voltage in this first auxiliary grid and this second auxiliary grid, and make this substrate that is positioned at this first auxiliary grid and this second auxiliary grid below form a drain electrode reversal zone and an one source pole reversal zone respectively, apply one the 6th voltage in this drain electrode reversal zone, apply one the 7th voltage in this source electrode reversal zone, wherein magnitude of voltage by little to being the 7th voltage greatly in regular turn, the 6th voltage, the 4th voltage and the 5th voltage are so that electronics is entered in this first electric charge storage layer by this source electrode reversal zone by channel hot electron effect (CHE); And
When carrying out second programming, apply the 4th voltage in this control grid, apply the 5th voltage in this first auxiliary grid and this second auxiliary grid, and make this substrate that is positioned at this first auxiliary grid and this second auxiliary grid below form a drain electrode reversal zone and an one source pole reversal zone respectively, apply the 7th voltage in this drain electrode reversal zone, apply the 6th voltage in this source electrode reversal zone, so that electronics is entered in this second electric charge storage layer by this drain electrode reversal zone by channel hot electron effect (CHE).
13, the method for operation of nonvolatile memory according to claim 11 is characterized in that wherein
Carrying out first when wiping, apply one the 8th voltage in this control grid, apply one the 9th voltage and make this substrate that is positioned at this first auxiliary grid below form a drain electrode reversal zone in this first auxiliary grid, apply 1 the tenth voltage in this drain electrode reversal zone, and setting this second auxiliary grid becomes it to float, wherein magnitude of voltage by little to being the tenth voltage, the 9th voltage and the 8th voltage greatly in regular turn, so that electronics is worn tunnel by entering this drain electrode reversal zone in this first electric charge storage layer by FN; And
Carrying out second when wiping, apply the 8th voltage in this control grid, apply the 9th voltage and make this substrate that is positioned at this second auxiliary grid below form the one source pole reversal zone in this second auxiliary grid, apply the tenth voltage in this source electrode reversal zone, and set this first auxiliary grid and it is become float, so that electronics is worn tunnel by entering this source electrode reversal zone in this second electric charge storage layer by FN.
14, the method for operation of nonvolatile memory according to claim 11 is characterized in that wherein
Carrying out first when reading, apply 1 the 11 voltage in this control grid, apply 1 the 12 voltage in this first auxiliary grid and this second auxiliary grid, and make this substrate that is positioned at this first auxiliary grid and this second auxiliary grid below form a drain electrode reversal zone and an one source pole reversal zone respectively, apply 1 the 13 voltage in this source electrode reversal zone, apply 1 the 14 voltage in this drain electrode reversal zone, wherein magnitude of voltage by little to being the 14 voltage greatly in regular turn, the 13 voltage, the 11 voltage and the 12 voltage are to read the position that is stored in this first electric charge storage layer; And
Carrying out second when reading, apply the 11 voltage in this control grid, apply the 12 voltage in this first auxiliary grid and this second auxiliary grid, and make this substrate that is positioned at this first auxiliary grid and this second auxiliary grid below form a drain electrode reversal zone and an one source pole reversal zone respectively, apply the 13 voltage in this drain electrode reversal zone, apply 1 the 14 voltage in this source electrode reversal zone, to read the position that is stored in this second electric charge storage layer.
15, a kind of method of operation of nonvolatile memory, be suitable for a nonvolatile memory, this nonvolatile memory comprises that at least being positioned at one suprabasil one controls grid, cover one first electric charge storage layer and one second electric charge storage layer of this control grid part top and sidewall respectively, lay respectively at an one source pole district and a drain region in this substrates of this second electric charge storage layer and these first electric charge storage layer both sides, it is characterized in that this method of operation comprises:
When carrying out first programming, apply 1 the 15 voltage in this control grid, apply 1 the 16 voltage in this drain region, and setting this source area becomes it to float, wherein magnitude of voltage, is entered in this first electric charge storage layer by this drain region so that electronics is worn tunnel by FN to being the 16 voltage and the 15 voltage greatly in regular turn by little; And
Carrying out second when programming, apply the 15 voltage in this control grid, apply the 16 voltage in this source area, and set this drain region and it is become float, enter in this second electric charge storage layer by this source area so that electronics is worn tunnel by FN.
16, the method for operation of nonvolatile memory according to claim 15 is characterized in that wherein
When carrying out first programming, apply 1 the 17 voltage in this control grid, apply 1 the 18 voltage in this drain region, apply 1 the 19 voltage in this source area, wherein magnitude of voltage by little to being the 19 voltage, the 18 voltage and the 17 voltage greatly in regular turn, so that electronics is entered in this first electric charge storage layer by this source area by channel hot electron effect (CHE); And
When carrying out second programming, apply the 17 voltage in this control grid, apply the 18 voltage in this source area, apply the 19 voltage, so that electronics is entered in this second electric charge storage layer by this drain region by channel hot electron effect (CHE) in this drain region.
17, the method for operation of nonvolatile memory according to claim 15 is characterized in that wherein
Carrying out first when wiping, apply one the 20 voltage in this control grid, apply one the 21 voltage in this drain region, and setting this source area becomes it to float, wherein magnitude of voltage by little to being the 21 voltage and the 20 voltage greatly in regular turn, so that electronics is worn tunnel by entering this drain region in this first electric charge storage layer by FN; And
Carrying out second when wiping, apply the 20 voltage in this control grid, apply the 21 voltage in this source area, and set this drain region and it is become float, so that electronics is worn tunnel by entering this source area in this second electric charge storage layer by FN.
18, the method for operation of nonvolatile memory according to claim 15 is characterized in that wherein
Carrying out first when reading, apply one the 22 voltage in this control grid, apply one the 23 voltage in this source area, apply one the 24 voltage in this drain region, wherein magnitude of voltage by little to be the 24 voltage, the 23 voltage and the 22 voltage greatly in regular turn, with read be stored in this first electric charge storage layer; And
Carrying out second when reading, apply the 22 voltage in this control grid, apply the 23 voltage in this drain region, apply the 24 voltage in this source area, to read the position that is stored in this second electric charge storage layer.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6255166B1 (en) * | 1999-08-05 | 2001-07-03 | Aalo Lsi Design & Device Technology, Inc. | Nonvolatile memory cell, method of programming the same and nonvolatile memory array |
| CN1433064A (en) * | 2002-01-14 | 2003-07-30 | 联华电子股份有限公司 | Operation process of non-volatile memory element |
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| US6255166B1 (en) * | 1999-08-05 | 2001-07-03 | Aalo Lsi Design & Device Technology, Inc. | Nonvolatile memory cell, method of programming the same and nonvolatile memory array |
| CN1433064A (en) * | 2002-01-14 | 2003-07-30 | 联华电子股份有限公司 | Operation process of non-volatile memory element |
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