CN100446392C - Optimized pulse over-cycle modulation switch stabilized voltage power supply controller - Google Patents

Abstract

The present invention relates to an optimized pulse over-period modulation switch stabilized voltage power supply controller which belongs to the field of electronic technology. The controller is composed of a voltage control loop, a current control loop and a main control gate, wherein the voltage control loop is composed of a voltage comparator C1, a voltage reference source 1, an AND gate G1, a state register, a zero state judgment device, a counter and a decoder so as to realize the function of common PSM modulation; the current control loop is composed of a resistor network, a voltage comparator C2 and a voltage reference source 2; different current limit values are generated by controlling the resistor network according to the signals of the voltage comparator C1 in the clock period and the former clock period so as to realize the conversion of three duty ratios; the main control gate is composed of an oscillator, an OR gate G4, an RS trigger, an NAND gate G2 and an AND gate G3, and the main control gate can generate control signals for the conduction or the close of a power switch tube. The controller of the present invention not only maintains the advantages of common PSM controllers, but also optimizes the duty ratios so as to reduce the ripples of the output voltage, and the active switch frequency of the power switch tube can not enter the audio range.

Description

A kind of pulse over-cycle phase modulation switch stabilized voltage power supply controller

Technical field

A kind of pulse over-cycle phase modulation switch stabilized voltage power supply controller belongs to electronic technology field, relates to a kind of pulse over-cycle phase modulation (PSM) switching stabilized-voltage power supply controller that can be applicable in the power integrated circuit.

Background technology

Normal pulse-width-modulated mode PWM (Pulse Width Modulation) and the pulse frequency modulated pattern PFM (Pulse Frequency Modulation) of adopting in power inverter.Fig. 1 has expressed the difference of several control mode control waveforms.Along with feedback voltage V _FbWith reference voltage V _RefError change, the PWM modulating mode adopts and changes fixed frequency pulse width power controlling switching tube, the PFM modulating mode adopts and changes fixed width pulse frequency power controlling switching tube, and pulse over-cycle phase modulating mode PSM (Pulse Skip Modulation) is a kind of new type of modulation pattern of power conversion system, regulate output voltage by skipping certain clock cycle, when being higher than set point, skips the clock cycle output voltage normally clock cycle when output voltage is lower than set point.

PWM controller and PFM controller are widely used in the Switching Power Supply.Fig. 2 has expressed the Boost switching power supply that adopts common PSM controller.Common PSM controller is made of voltage comparator, d type flip flop and oscillator etc.When the clock cycle of oscillator begins, if output voltage is higher than set point, voltage comparator output logic low level then, thus forbid d type flip flop in the set of this clock cycle, so power switch pipe in the not conducting of this clock cycle, is promptly skipped the clock cycle; If output voltage is lower than set point, voltage comparator output logic high level, then d type flip flop set under clock pulse control, the power controlling switching tube is opened a pulse identical with clock signal.The Switching Power Supply that adopts common PSM controller will be skipped the more clock cycle when load is light, otherwise load is heavy more, and it is few more to skip the clock cycle.

Under the normal operating conditions, the loss of Switching Power Supply mainly comprises conduction loss and switching loss.Under underload or the holding state, load upper reaches overcurrent is less, and conduction loss can be ignored, and switching loss becomes main system standby power consumption source.When underload, the PWM controller is because frequency is constant, and switching loss is constant in whole loading range, has influenced the raising of efficient under the light load condition; The PFM controller has caused the difficulty of subsequent filter design owing to become during frequency spectrum, and the electromagnetic compatibility characteristic of PFM controller switches power supply is adopted in influence.And common PSM controller can make power switch pipe skip the more clock cycle under light load condition, therefore can reduce switching loss, the efficient when increasing substantially underload.In addition, common PSM controller also has advantages such as control mode is simple, strong robustness, response speed is fast, antijamming capability is strong, the electromagnetic compatibility characteristic is good.But the Switching Power Supply that adopts common PSM controller can be skipped the more clock cycle when underload, and the actual switch frequency of power tube easily enters audiorange and produces noise, and output voltage ripple is bigger.Therefore need be optimized common PSM controller, avoid switching frequency to enter audiorange, reduce output ripple.

Summary of the invention

The invention provides a kind of pulse over-cycle phase modulation switch stabilized voltage power supply controller, on advantage basis such as keep efficient height, strong robustness under the common PSM controller underload, response speed is fast, antijamming capability is strong, the electromagnetic compatibility characteristic is good, duty ratio is optimized, thereby reduced output voltage ripple, and the power switch pipe effective switching frequency can not enter audiorange.

Detailed technology scheme of the present invention is:

A kind of pulse over-cycle phase modulation switch stabilized voltage power supply controller (as shown in Figure 3) is made up of voltage control loop, current controlled circuit and master control door, it is characterized in that, the described voltage control loop route first voltage comparator C ₁, voltage-reference 1, first and door G ₁, status register, nought state determining device, counter and decoder form; Described current regulator route resistor network, the second voltage comparator C ₂Form with voltage-reference 2; Described master control door is by oscillator or door G ₄, rest-set flip-flop, NAND gate G ₂With second with the door G ₃Form;

The first voltage comparator C ₁Positive input terminal link to each other with voltage-reference 1, its negative input end links to each other with the Switching Power Supply output, its output termination first and door G ₁First input end; First with the door G ₁The clock signal output terminal CLK of the second input termination oscillator, the input of its output termination status register; The input of the current state output connecting to neutral state judging of status register, the first input end and second input of its previous state and current state output termination decoder; The input and the NAND gate G of the output termination counter of nought state determining device ₂The positive logic input; The 3rd input and the NAND gate G of the output termination decoder of counter ₂The negative logic input; The output connecting resistance network control corresponding input of decoder corresponding state sign indicating number;

The second voltage comparator C ₂Positive input terminal link to each other with the tie point of resistor network with power switch pipe M, its negative input end links to each other with voltage-reference 2, its output termination or the door G ₄The positive logic input;

The clock signal output terminal CLK of oscillator connects the S end and first and a G of rest-set flip-flop ₁Second input, its maximum duty cycle signal output D _MaxConnect or door G ₄The negative logic input; Or door G ₄The R end of output termination rest-set flip-flop; The output termination second of rest-set flip-flop and door G ₃First input end; Second with the door G ₃The second input termination NAND gate G ₂Output, the grid of its output termination power switch pipe M.

In the technique scheme:

Described status register is two bit shift register, data input pin connect first with the door G ₁, input end of clock is oscillator clock signal CLK, data output end is this a clock cycle state and a last clock cycle state output end.

Described nought state determining device is an inverter.

The counter of described counter for restarting automatically, count value increases when being input as ' 1 ', and count value is reset to 0 when being input as ' 0 ', is output as ' 1 ' when count value reaches the N hour counter.

Described N is the critical periodicity of striding that is about to enter audiorange.Audiorange is 20Hz～20kHz, so when oscillator clock signal CLK frequency was fosc, N satisfied fosc/N＞20kHz, the operating frequency of guaranteeing power switch pipe M is more than audiorange.

Described decoder is input with current state and three signals of previous state output of counter output, status register, is output with resistor network control signal a, b and c, and its input/output relation is according to the logical relation operation of table 1.

Table 1 decoder input/output relation table

Described resistor network is parallel resistor network (as shown in Figure 4), is made up of first resistance R 1, second resistance R 2, the 3rd resistance R 3, the first switching tube M1, second switch pipe M2 and the 3rd switching tube M3; One end of first resistance R 1, second resistance R 2 and the 3rd resistance R 3 is connected with each other, and connects the source electrode of power switch pipe M jointly; The drain electrode of another termination first switching tube M1 of first resistance R 1, the drain electrode of another termination second switch pipe M2 of second resistance R 2, the drain electrode of another termination switching tube the 3rd M3 of the 3rd resistance R 3; The source electrode common ground of the first switching tube M1, second switch pipe M2 and the 3rd switching tube M3; The grid of the first switching tube M1 meets the state first output a of decoder, and the grid of second switch pipe M2 meets the state second output b of decoder, and the grid of the 3rd switching tube M3 meets state the 3rd output c of decoder.

Described oscillator output signal is clock signal clk and maximum duty cycle signal D _Max, both frequencies, phase place are identical, but the duty ratio difference, the clock signal clk duty ratio is less, and maximum duty cycle signal D accounts for _MaxSky is bigger.

The function of each part of the present invention is:

The voltage control loop is realized common PSM modulation function, and current controlled circuit is realized the conversion of three kinds of duty ratios, and the master control door is realized the output of the control waveform that Switching Power Supply is required.Oscillator output signal is clock signal clk and maximum duty cycle signal D _Max, both frequencies, phase place are identical, but the duty ratio difference.Voltage-reference 1 and voltage-reference 2 are used to produce fixing magnitude of voltage.Rest-set flip-flop is at clock signal clk and or door G ₄Act on set down or reset output high level during set, output low level when resetting.The first voltage comparator C ₁Detected switch power source output voltage Vout and fixed reference potential a reference source 1 are compared, when Vout is higher than the reference voltage of fixed voltage a reference source 1, be output as 0, otherwise be output as 1.First with the door G ₁Play synchronous effect.Status register receives the first voltage comparator C in each clock cycle ₁Output signal (0 or 1), store this clock cycle and a last clock cycle first voltage comparator C ₁Output signal.The nought state determining device is judged this clock cycle first voltage comparator C of status register ₁Output signal whether be zero, as the first voltage comparator C ₁Output signal be 0 o'clock, the nought state determining device is output as 1.Counters count nought state determining device is 1 number of states of output continuously, when the nought state determining device is exported 1 state continuously, and this clock cycle first voltage comparator C of corresponding states register ₁Output signal be 0, the rolling counters forward value increases, when the nought state determining device is exported 0 state, this clock cycle first voltage comparator C of corresponding states register ₁Output signal be 1, counter reset.The output useful signal is to decoder and NAND gate G when the counter meter is imported to N continuous individual 1 ₂The negative logic input.Decoder is according to the input of counter and status register, according to logical relation shown in the table 1, and required gate control signal a, b and the c of switching tube in the network that has a resistance.The effect of resistor network is to regulate the equivalent resistance R that is in series with power switch pipe M _SenseThereby the voltage signal output different proportion, reflection power switch pipe M electric current.The second voltage comparator C ₂Function be under the particular current peak condition, to turn-off power switch pipe M.When power switch pipe M gate control signal when being high, power switch pipe is opened, and flows through the electric current I of power switch pipe _DSLinear increasing.So the second voltage comparator positive input terminal voltage signal is for flowing through power switch tube current and equivalent resistance R _SenseAmassing, i.e. I _DS* R _SenseWhen the value of the second voltage comparator positive input terminal voltage signal reaches the reference value of voltage-reference 2, the second voltage comparator C ₂Be output as 1, thereby make the rest-set flip-flop switch-off power switching tube M that resets, so just realized fixing duty ratio switch power switching tube.Obtain different equivalent resistance R by decoder controlling resistance network _Sense, can make the second voltage comparator C ₂Switch-off power switching tube M when different peak currents, thereby the duty ratio D that realization is set ₁, D ₂, D ₃

Detailed operation process of the present invention is:

Sampling and outputting voltage Vout is by the first voltage comparator C ₁Compare with the reference voltage of voltage-reference 1, produce the state of output voltage, greater than set point, then output state is ' 0 ' as if output voltage; Otherwise output state is ' 1 '.The first voltage comparator C ₁Output through after the clock signal clk modulation, be input to status register.Store last clock cycle and the present clock period first voltage comparator C in the status register ₁Output state, the combination by this two states determines current conducting duty ratio.The nought state determining device judges whether the output signal of status register is zero, counters count nought state determining device is the nought state useful signal quantity of output continuously, its basic principle is a finite state machine, then is output as height when detecting input N continuous ' 1 '; Other states are output as low.The output useful signal is to decoder during to N continuous ' 1 ' when the counter meter, and its output represents whether system frequency enters audiorange.If output effectively, then expression system enters audiorange; Otherwise system does not enter audiorange.When counter meter during to nought state determining device output non-zero status, reset when perhaps counting N continuous ' 1 ', restart counting.Decoder as input, if the current output voltage state is 0, no matter why last periodic state is worth, is then skipped this cycle with counter output signal and status register state; If the present clock period output state is 1, then decoder is determined the duty ratio in this cycle with the controlling resistance network according to the output state output control signal in last cycle.If two periodic state sequences are " 01 ", then the controlling resistance network produces a medium resistance value R _MidIf two periodic state sequences are " 11 ", then the controlling resistance network produces a less resistance value R _MinFor anti-locking system enters audiorange, to export when effective at counter, decoder controlling resistance network produces a bigger resistance value R _MaxThe resistor network and the second voltage comparator C ₂Be most crucial control circuit, its output signal is directly determining gate control signal.Resistor network is made up of three resistance branch by switch control of parallel connection, respectively by a, and b and c signal controlling.When sample rate current flows through resistor network, on resistor network, produce the voltage signal that changes with electric current, will make the second voltage comparator C with the reference voltage comparison of voltage-reference 2 ₂Switch-off power switching tube when output voltage signal equates with the reference voltage of voltage-reference 2, the value by different control signal controlling resistance networks can produce the different duty pulse control signal.The clock signal of pierce circuit output is a narrow pulse signal, and in each clock cycle, clock signal clk is high, maximum duty cycle signal D _MaxBe height, the second voltage comparator C ₂Be output as lowly, promptly rest-set flip-flop S end is for high, and the R end is for low, makes rest-set flip-flop set output high level.Spend very short a period of time, clock becomes low, and this moment, S end became lowly, and the R end still be low, and high level is still exported in the maintenance of rest-set flip-flop state; When or the door G ₄Any one input signal when changing, i.e. D _MaxBy hypermutation is low, perhaps the second voltage comparator C ₂Output becomes height and (represents the power switch tube current to reach set point a reference source 2/R from low _Sense) time, rest-set flip-flop R end is for high, and the S end is for low, makes the rest-set flip-flop output low level that resets.Sample rate current I _DsBe the fixing triangular wave of a slope, when its value rises to voltage-reference 2 reference voltages/R _SenseThe time, the second voltage comparator C ₂Output becomes height, and promptly the R end becomes height, the rest-set flip-flop output low level that resets.Second with the door G ₃With NAND gate G ₂Counter output, the output of nought state determining device, rest-set flip-flop output are become the control signal of power switch pipe M by certain combinational logic.When counter is output as lowly, the nought state determining device is output as when low, illustrates that this clock cycle output voltage is lower than set point, this moment NAND gate G ₂Output high level make second with the door G ₃Identical with rest-set flip-flop output, in the beginning rest-set flip-flop set of clock cycle, promptly the power switch pipe control signal is high, opens power switch pipe, and decoder is according to this clock cycle and last clock cycle state, the R of controlling resistance network _Sense, as sample rate current I _DsValue rises to a reference source 2 reference voltages/R _SenseThe time, the second voltage comparator C ₂Output becomes height, and promptly the R end becomes height, the output low level switch-off power switching tube M thereby rest-set flip-flop resets; When counter is output as lowly, the nought state determining device is output as when high, illustrate that this clock cycle output voltage is higher than set point, but the switching frequency of power switch pipe M does not enter audiorange, this moment NAND gate G ₂Output low level make second with the door G ₃Also output low level is skipped the clock cycle thereby power switch pipe M control signal remains low realization; When counter is output as height, illustrate because the switching frequency of power switch pipe M will enter audiorange, no matter this moment, why the nought state determining device exported state, NAND gate G ₂Output high level make second with the door G ₃Output is identical with rest-set flip-flop output, and decoder controlling resistance network makes minimum duty cycle D of power switch pipe M conducting ₃Prevent that locking system enters audiorange.

The duty ratio of PSM controller pulse control signal of the present invention has three kinds: fixed duty cycle D ₁, little duty ratio D ₂With minimum duty cycle D ₃For reaching the purpose that reduces output voltage ripple, fixed duty cycle D ₁Be used for the bigger situation of load current; Little duty ratio D ₂Be used for the less situation of load current.When output voltage values was higher than set point, power switch pipe strode across the clock cycle; When the converter output voltage values was lower than set point, power switch pipe was with duty ratio D ₁Or D ₂Conducting, the PSM controller determines according to the relativeness of this clock cycle and a last clock cycle output voltage and set point power switch pipe M is with which kind of duty ratio conducting at this moment.Fixed duty cycle D ₁With little duty ratio D ₂Introducing, reduced switch periods and skipped energy span between the clock cycle, thereby reduced output voltage ripple.

PSM controller of the present invention when clock cycle of skipping during greater than N (N is the critical periodicity of striding that is about to enter audiorange), makes switching regulator with minimum duty cycle D under light load condition ₃Switch once, thereby make power switch pipe M effective switching frequency not enter audiorange, avoided the generation of audio-frequency noise.

PSM controller of the present invention has the following advantages:

1, when underload efficient than PWM controller height

Under underload or the holding state, conduction loss can be ignored because load upper reaches overcurrent is less, and switching loss becomes main system power dissipation source.During underloading, this PSM controller reduces the switch number of times of power tube, thereby reduces switching loss, to reach the purpose that improves its efficient by skipping the clock cycle.

2, during underload, the actual switch frequency of power switch pipe can not enter audiorange

PSM controller of the present invention is striden periodic phenomena and all can be occurred under different loads, the light more periodicity that strides across of load is many more, and duty ratio changes along with the load weight.When load is very light, increase the minimum duty cycle D that produces owing to counter controls though stride across clock periodicity ₃Existence, make to stride across clock periodicity, so can effectively avoid the actual switch frequency of power switch pipe to enter audiorange all the time less than N.

Description of drawings:

Fig. 1 is that PSM and PWM, PFM pulse control signal contrast schematic diagram; Wherein, V _RefBe reference voltage, V _FbBe feedback voltage.

Fig. 2 is the Boost switching power supply electrical block diagram with common PSM controller; Wherein, L is an energy storage inductor, and Vin is an input voltage, and Vout is an output voltage, and D is a diode, and C is an electric capacity, and R is a load resistance.

Fig. 3 is the Boost switching power supply electrical block diagram with PSM controller of the present invention; Wherein, L is an energy storage inductor, and Vin is an input voltage, and Vout is an output voltage, and D is a diode, and C is an electric capacity, and R is a load resistance, and M is a power switch pipe, C ₁, C ₂Be first voltage comparator and second voltage comparator, G ₁Be first with the door, G ₂Be the NAND gate of band negative logic input, G ₃Be second with the door, G ₄For band negative logic input or door, CLK is an oscillator clock signal, D _MaxBe oscillator output maximum duty cycle signal.

Fig. 4 is the resistor network structural representation in the PSM controller of the present invention; R1, R2 and R3 are respectively first, second and the 3rd resistance, and M1, M2 and M3 are respectively first, second and the 3rd switching tube, I _DsBe sample rate current, a, b and c represent the gate control signal of first, second and the 3rd switching tube.

Fig. 5 is the working waveform figure of described PSM controller under different loads:

(a) load R=50 Ω, (b) load R=150 Ω, (c) load R=500 Ω

Fig. 6 is under different loads, adopts in the Boost converter proof scheme of described PSM controller power tube drain-source voltage V _Ds, drain-source current I _DsWith the converter output voltage V _OutTest waveform:

(a) during R=36 Ω, V _DsAnd I _DsTest waveform

(b) during R=150 Ω, V _DsAnd I _DsTest waveform

(c) during R=500 Ω, V _DsAnd I _DsTest waveform

(d) during R=150 Ω, V _DsAnd V _OutTest waveform

Specific embodiments

Counter is output as input with the nought state determining device, with decoder and NAND gate G ₂The negative logic input is output.When the nought state determining device is output as zero hour counter work, when nought state determining device output non-zero hour counter resets.Counters count nought state determining device is the nought state quantity of output continuously, when the counter meter during to N continuous zero the output useful signal to decoder and NAND gate G ₂The negative logic input.Whether its output display system frequency enters audio frequency.If output effectively, then expression system enters audiorange; Otherwise system does not enter audiorange.

As input, its output bus a/b/c is connected to resistor network to decoder with counter output signal and status register quantity of state.Output bus a/b/c comprises 3 holding wires: the first output a, the second output b, the 3rd output c.If current output voltage state S0 is 0,, then skip this clock cycle no matter why last periodic state is worth; If current period output state S0 is 1, then determine the current limit value in this cycle according to the output state S1 in last cycle.If two periodic state S1/S0 sequences are " 01 ", then the controlling resistance network produces a medium resistance value R _MidIf two periodic state sequences are " 11 ", then the controlling resistance network produces a less resistance value R _MinFor anti-locking system enters audiorange, to export when effective at counter, the controlling resistance network produces a bigger resistance value R _Max

Typical resistor network as shown in Figure 4, thereby its effect is to regulate the resistance of connect with power switch pipe to export the voltage signal that different proportion reflects the power switch tube current, is made up of three switch controlling resistance branch roads of parallel connection, respectively by a, b and c signal controlling.As shown in Figure 4, after power switch pipe is opened, electric current I _DSFlow down from the upper end, when control signal c is a logical one, I _DSFlow through resistance R 3, output voltage signal is I _DSLong-pending with R3; When control signal b is a logical one, I _DSFlow through resistance R 2, output voltage signal is I _DSLong-pending with R2; When control signal a is a logical one, I _DSFlow through resistance R 1, output voltage signal is I _DSLong-pending with R1.By controlling resistance network equivalent resistance value R _Sense, can determine the ratio of respective output voltages voltage of signals value and power switch pipe M electric current.

The corresponding relation of the detected state in current limit and the status register is as follows:

Table 2: the corresponding relation of electric current limit and detected state

Counter output	The state S1 S0 that detects	Resistor network control signal a b c	I limit(0＜k3＜k2＜1)	Duty ratio
					0	1 1	0 1 0	I max	D 1
0	0 1	0 0 1	k 2I max	D 2
					0	X 0	0 0 0	Skip the clock cycle	Skip the clock cycle
1	N continuous 0 state	1 0 0	k 3I max	D 3

PSM controller of the present invention, this cycle of status register logic state S0 and last week logic state S1 represented the relation of output voltage and set point.Making duty ratio of power switch pipe conducting at output voltage during less than set point is D ₁Or D ₂Switch periods, during greater than set point, make power switch pipe stride across the clock cycle at output voltage, and when striding across the clock cycle when too much, making duty ratio of power switch pipe conducting is D ₃Switch periods.The current limitation that duty ratio is determined by resistor network and current limitation comparator is determined.When load was heavier, current limitation was higher, and the power switch pipe conducting is than big space rate or skip the clock cycle; And when load reduction, then may make the actual switch frequency near audiorange owing to skipping the clock cycle increase, so reduce current limitation this moment, power switch pipe conducting duty ratio reduces simultaneously, thereby reduce the clock cycle that power switch pipe strides across, increase the actual switch frequency.When load was enough light, current limitation was in minimum, and the clock cycle of skipping is more, and the actual switch frequency may enter audiorange, and make power switch pipe every minimum duty cycle D of N clock cycle conducting this moment ₃Wherein N is the critical periodicity of striding that is about to enter audiorange, for the clock cycle be the canonical system of 132kHz, N is 6.The above working method can guarantee to adopt the switching power supply of PSM controller of the present invention to reach high conversion rate by cycle-skipping.The actual switch frequency does not enter audiorange simultaneously.

The duty ratio of PSM controller of the present invention is realized by the current limitation that decoder controlling resistance network produces.With the Boost circuit is example, wherein minimum duty cycle D ₃Can be by formula $D_3=\sqrt{\frac{2L(1-K^{N+1})}{{\mathrm{TV}}_{\mathrm{in}}^2{K}^N(1-K)}{x}_0}$ Calculate.This formula derives from the input and output energy balance relations, wherein $K=\frac{1-T/\mathrm{<figure-callout\; id="1"\; label="RC"\; filenames="C20061002091600151.png"\; state="\{\{state\}\}">RC</figure-callout>}}{1+T/\mathrm{RC}};$ R, L, C are respectively resistance, inductance, the capacitance in the inverter main circuit (as the Boost circuit); T is the clock cycle of control signal; V _InInput voltage for circuit; x ₀Load power consumption during for energy balance).Fixed duty cycle D ₁Maximum by formula $D_{}$ ${}_1=\sqrt{\frac{8\frac{m+n}{n}\frac{L}{\mathrm{RT}}}{{(\frac{{2V}_{\mathrm{in}}}{V_{\mathrm{ref}1}}-1)}^2-1}}$ Calculate, wherein m is the periodicity of power switch pipe conducting, and n is the periodicity that power switch pipe is skipped; V _Ref1Reference value for the converter output voltage.Little duty ratio D ₂Choose comparatively flexibly, D is generally arranged ₂=(0.2～0.6) D ₁, can decide according to actual conditions.

Common PSM controller has two states: stride across the clock cycle and with maximum duty cycle D ₁Switch conduction, so the energy span is bigger, and then influence enters the speed and the output voltage ripple of stable state.And PSM controller of the present invention is compared with common PSM controller, and difference is to have 4 kinds of operating states: stride across the clock cycle, duty ratio is respectively D ₁(fixed duty cycle), D ₂(little duty ratio) and D ₃The on off state of (minimum duty cycle).Wherein, D ₁Be used for the bigger situation of load, can transmit more energy to output from input; D ₂Be used for the slightly little situation of load, relax and stride across the clock cycle and with fixed duty cycle D ₁Energy span between the switch reduces output voltage ripple; D ₃Be used to stride across that clock periodicity equals to be about to enter audiorange is critical when striding periodicity, make the duty ratio of power tube conducting, avoid the actual switch frequency of power switch pipe to enter audiorange.

The control signal oscillogram of the PSM controller that is as shown in Figure 5 under different loads.Wherein first waveform is a clock signal, and second waveform S1 is the state that detected load last one-period, and the 3rd waveform S0 is the state that current period detects load, the 4th waveform I _DSIt is the electric current of power switch pipe.As can be seen from the figure, current state is that 0 o'clock power switch pipe turn-offs; When state is 01,11, corresponding different limiting current value (promptly corresponding different duty ratios); When the full N continuous of counter meter (being 6 in the legend) 0 state, minimum duty cycle D of power switch pipe conducting ₃As can be seen from this figure: when load was heavier, system was mainly at fixed duty cycle D ₁(be that electric current is limited to I _Max) and stride across conversion between the clock cycle; When load lightened, system was mainly at duty ratio D ₂(be that electric current is limited to k ₂I _Max) and stride across conversion between the clock cycle; When load was lighter, system was mainly at minimum duty cycle D ₃(be that electric current is limited to k ₃I _Max) and stride across conversion between the clock cycle.Therefore, described PSM controller in whole loading range, conducting duty ratio and to stride across between the clock cycle energy span less, it is bigger to overcome common PSM controller output voltage ripple, easily enters the shortcoming of audiorange during underloading.Fig. 6 is the experimental waveform with the FPGA checking.Obviously, stride periodic phenomena and all can occur under different loads, the light more periodicity that strides across of load is many more, and duty ratio changes along with the load weight.When load is very light, shown in Fig. 6 (c), increase though stride periodicity, stride periodicity all the time less than N, and shown in Fig. 6 (d), reached less output voltage ripple.Therefore, PSM controller of the present invention can reach less output voltage ripple, avoids the actual switch frequency of power tube to enter audiorange simultaneously.

Claims (7)

1, a kind of pulse over-cycle phase modulation switch stabilized voltage power supply controller is made up of voltage control loop, current controlled circuit and master control door, it is characterized in that, the described voltage control loop route first voltage comparator (C ₁), voltage-reference 1, first and door (G ₁), status register, nought state determining device, counter and decoder form; Described current regulator route resistor network, the second voltage comparator (C ₂) and voltage-reference 2 compositions; Described master control door is by oscillator or door (G ₄), rest-set flip-flop, NAND gate (G ₂) and second and the door (G ₃) form;

First voltage comparator (the C ₁) positive input terminal link to each other with voltage-reference 1, its negative input end links to each other with the Switching Power Supply output, its output termination first and door (G ₁) first input end; First with the door (a G ₁) the clock signal output terminal (CLK) of the second input termination oscillator, the input of its output termination status register; The input of the current state output connecting to neutral state judging of status register, the first input end and second input of its previous state and current state output termination decoder; The input and the NAND gate (G of the output termination counter of nought state determining device ₂) the positive logic input; The 3rd input and the NAND gate (G of the output termination decoder of counter ₂) the negative logic input; The output connecting resistance network control corresponding input of decoder corresponding state sign indicating number;

Second voltage comparator (the C ₂) positive input terminal link to each other with the tie point of resistor network with power switch pipe (M), its negative input end links to each other with voltage-reference 2, its output termination or the door (G ₄) the positive logic input;

The clock signal output terminal of oscillator (CLK) connects the S end and first and (a G of rest-set flip-flop ₁) second input, its maximum duty cycle signal output (D _Max) connect or door (G ₄) the negative logic input; Or door (G ₄) the R end of output termination rest-set flip-flop; The output termination second of rest-set flip-flop and door (G ₃) first input end; Second with the door (a G ₃) the second input termination NAND gate (G ₂) output, its output the termination power switch pipe (M) grid.

2, a kind of pulse over-cycle phase modulation switch stabilized voltage power supply controller according to claim 1 is characterized in that described status register is two bit shift register, data input pin connect first with the door (a G ₁), input end of clock is oscillator clock signal (CLK), data output end is this a clock cycle state and a last clock cycle state output end.

3, a kind of pulse over-cycle phase modulation switch stabilized voltage power supply controller according to claim 1 is characterized in that, described nought state determining device is an inverter.

4, a kind of pulse over-cycle phase modulation switch stabilized voltage power supply controller according to claim 1, it is characterized in that, the counter of described counter for restarting automatically, count value increases when being input as ' 1 ', count value is reset to 0 when being input as ' 0 ', is output as ' 1 ' when count value reaches the N hour counter.

5, a kind of pulse over-cycle phase modulation switch stabilized voltage power supply controller according to claim 1, it is characterized in that, described decoder is input with current state and three signals of previous state output of counter output, status register, with resistor network control signal a, b and c is output, and its input/output relation moves according to the logical relation of following table:

6, a kind of pulse over-cycle phase modulation switch stabilized voltage power supply controller according to claim 1, it is characterized in that described resistor network is parallel resistor network by three resistance: first resistance (R1), second resistance (R2) and the 3rd resistance (R3) and three switching tubes: first switching tube (M1), second switch pipe (M2) and the 3rd switching tube (M3) are formed; One end of first resistance (R1), second resistance (R2) and the 3rd resistance (R3) is connected with each other, and the connect power switch pipe jointly source electrode of (M); The drain electrode of another termination first switching tube (M1) of first resistance (R1), the drain electrode of another termination second switch pipe (M2) of second resistance (R2), the drain electrode of another termination the 3rd switching tube (M3) of the 3rd resistance (R3); The source electrode common ground of first switching tube (M1), second switch pipe (M2) and the 3rd switching tube (M3); The grid of first switching tube (M1) meets the state first output a of decoder, and the grid of second switch pipe (M2) meets the state second output b of decoder, and the grid of the 3rd switching tube (M3) meets state the 3rd output c of decoder.

7, a kind of pulse over-cycle phase modulation switch stabilized voltage power supply controller according to claim 1 is characterized in that, described oscillator output signal is clock signal (CLK) and maximum duty cycle signal (D _Max), both frequencies, phase place are identical, but the duty ratio difference, clock signal (CLK) duty ratio is less, maximum duty cycle signal (D _Max) duty ratio is bigger.

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