CN100448028C - A MOS resistor and its manufacture method - Google Patents
A MOS resistor and its manufacture method Download PDFInfo
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- CN100448028C CN100448028C CNB2006101403912A CN200610140391A CN100448028C CN 100448028 C CN100448028 C CN 100448028C CN B2006101403912 A CNB2006101403912 A CN B2006101403912A CN 200610140391 A CN200610140391 A CN 200610140391A CN 100448028 C CN100448028 C CN 100448028C
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Abstract
The provided MOS transistor comprises asymmetric source and drain structures. Wherein, the source uses metal or metal-semiconductor compound and channel to form Schottky barrier contact, while the drain is boost high doped. Compared with traditional MOSFET device, this invention increases on-off current rate greatly, compatible to traditional manufacture technology, and has much room for high-K grid medium and metal grid material since low thermal budget.
Description
Technical field:
The invention belongs to semiconductor integrated circuit and manufacturing technology field thereof, relate in particular to MOS transistor of a kind of new construction and preparation method thereof.
Background technology:
In the information-intensive society in the present age, under maximization of chip integration density and the optimized double drive of circuit performance, the core MOSFET device of integrated circuit is constantly scaled.Along with constantly dwindling of MOSFET device size, after the characteristic size of device entered nanoscale, at material, numerous areas such as structure and technology were that the integrated circuit of core has run into increasing challenge with MOSFET.In order to deal with these challenges, many new device architectures and technology manufacture method are suggested the MOSFET design that is applied to nanoscale and make.
The Schottky barrier source drain MOSFET is exactly wherein a kind of, and this structure devices was put forward by Lepselter and Sze in nineteen sixty-eight.Schottky barrier source drain MOSFET transistor is the source of device to be leaked utilize metal (or silicide) to replace traditional source leakage doping, form Schottky barrier between metal (or silicide) and the silicon raceway groove, the conducting of device is that the charge carrier direct Tunneling potential barrier by the source end realizes.When the characteristic size of MOSFET device has arrived nanoscale, doping MOSFET is leaked in traditional source, and its short channel effect and source are leaked potential barrier to reduce effect serious day by day, the degradation of device.In order to improve the performance of device, improve the short channel effect of device, it is essential that source super shallow junction of leakage and abrupt junction become, but because the restriction of manufacturing process, traditional source is leaked doping MOSFET and is difficult to form super shallow junction and abrupt junction.The source of while doped source and drain MOSFET is omitted living resistance and also is difficult to scaled.The Schottky barrier source drain MOSFET leaks doping MOSFET than traditional source, because metal or the metal silicide that has adopted high electricity to lead leaked in the source, the relative doped source and drain of the dead resistance of Schottky source drain is much smaller; And the schottky interface that metal or metal silicide and silicon form has only several atomic layer sizes, makes that super shallow source-and-drain junction is easy to form.For the MOSFET device of nanoscale, it is more and more urgent that the application of high-K gate dielectric and metal gate has become, but traditional source leakage doping MOSFET is difficult to satisfy its low heat budget.And the Schottky barrier source drain MOSFET does not need the source to leak the high-temperature annealing process of doping and back, therefore technology is simple relatively, less heat budget is arranged, satisfy the required low temperature process process of high K and metal gate material like this, for the use of high K and metal gate material provides possible solution route.
Yet because the electric leakage of the OFF state of schottky junction is much bigger with respect to PN junction, so the Schottky barrier source drain MOSFET exists the big problem of OFF leakage current; The existence of Schottky barrier simultaneously makes that also the ON state current of device is less relatively.Generally speaking, the switch attitude current ratio of Schottky barrier source drain MOSFET is not high.In order to improve the ON state current of device, reduce the off-state current of device, thereby improve the switch attitude current ratio of Schottky-barrier MOSFET, many new device architectures are suggested and are used to address this problem.There is the researcher to propose provenance leakage and raises the Schottky barrier source drain MOSFET of grid depression just, this structure devices has bigger switch attitude current ratio, yet its source end has also reduced the ON state current of device when raising, and the technology of device is implemented in and also exists difficulty under the nanoscale simultaneously.Also having the researcher to propose the source end adopts metal or metal silicide to form Schottky barrier, drain terminal adopts to mix to inject and forms PN junction, this device architecture has good device property, but can't realize autoregistration on the technology, the injection of mixing simultaneously is after the grid structure forms, this means higher heat budget, thereby be difficult to be applied to the MOSFET manufacturing of nanoscale.
Summary of the invention:
It is big to the purpose of this invention is to provide a kind of switch attitude current ratio, and can be applicable to the MOS transistor of nanoscale devices, and this transistorized manufacture method.
Technical scheme of the present invention is as follows:
A kind of MOS transistor comprises a gate electrode, a gate dielectric layer, a gate electrode side wall medium layer, semi-conductive substrate, a source region and a drain region; Described source region is made of the compound-material that metal or metal and semiconductor form, and described drain region forms by semiconductor is highly doped, lays respectively on the Semiconductor substrate, the both sides of gate electrode, and the drain region has the structure of raising; Described gate dielectric layer is positioned under the gate electrode, on the Semiconductor substrate, both sides link to each other with the drain region with the source region respectively; Described gate electrode side wall medium layer is positioned at gate electrode near on source region one side, the gate dielectric layer.
Above-mentioned MOS transistor source end adopts metal or metal silicide etc. and raceway groove to form Schottky contacts, and drain terminal adopts the highly doped leakage of raising.The thickness of the gate dielectric layer of growing on the Semiconductor substrate is 1-20nm; The thickness of gate electrode is 80-150nm; The gate electrode side wall medium layer in the gate electrode side, the width of the part that links to each other with gate dielectric layer is 5-20nm.
The manufacture method of the above-mentioned Schottky Barrier Contact source end and the MOS transistor (Schottky barrier Sourceand Raised Drain MOSFET, SSRD MOSFET) of the doping drain terminal of raising may further comprise the steps:
(1) ion injects the formation high-doped zone on Semiconductor substrate;
(2) deposit one deck medium protective layer;
(3) chemical wet etching forms a ledge structure up to undoped layer;
(4) growth gate dielectric layer;
(5) deposit gate electrode layer, etching forms gate figure;
(6) side wall medium layer is sacrificed in deposit, and etching forms grid side wall figure;
(7) deposit layer of metal, and process annealing are then removed unreacted metal;
(8) remove medium protective layer;
(9) enter the conventional cmos later process at last, comprise deposit passivation layer, opening contact hole and metallization etc., can make described MOS transistor.
In the above-mentioned manufacture method, the semiconductor substrate materials in the described step (1) is selected from Si, Ge, SiGe, GaAs or other II-VI, the binary or the ternary semiconductor of III-V and IV-IV family.
Above-mentioned manufacture method, the media protection layer material in the described step (2) are selected from silicon dioxide, silicon nitride, aluminium nitride, TEOS (silester) and other insulating material.
Above-mentioned manufacture method, the gate dielectric material in the described step (4) is selected from silicon dioxide, hafnium oxide, hafnium nitride etc.
Above-mentioned manufacture method, the method for described step (4) growth gate dielectric layer is selected from one of following method: conventional thermal oxidation, nitrating thermal oxidation, chemical vapor deposition, physical vapor deposition.
Above-mentioned manufacture method sacrifices that the side wall medium layer material is selected from silicon nitride, TEOS or other all has high corrosion to select the thin-film material of ratio with silicon and silica in the described step (6).
Above-mentioned manufacture method, the metal material in the described step (7) are selected from Pt, Er, Co, Ni and other can form the metal of compound with the substrate semiconductor material by annealing.
Above-mentioned manufacture method, the injection energy that described ion injects is 30eV-200KeV, the thickness of the gate dielectric layer of growing on the Semiconductor substrate is 1-20nm; The thickness of gate electrode layer is 80-150nm; The gate electrode side wall medium layer in the gate electrode side, the width of the part that links to each other with gate dielectric layer is 5-20nm.
Advantage of the present invention and good effect: the MOS transistor (SSRD MOSFET) of Schottky Barrier Contact of the present invention source end and the doping drain terminal of raising, its source is leaked and is adopted dissymmetrical structure, this asymmetric source-drain structure source end adopts Schottky Barrier Contact, and drain terminal adopts the highly doped leakage of raising.Owing to adopted this dissymmetrical structure, the metal of source end or metal are more much smaller than traditional doped semiconductor with the resistivity of the compound that semiconductor forms, simultaneously drain terminal has been owing to adopted the structure of raising, and it is more much smaller than traditional MOSFET device to make the source of device omit living resistance; Because the drain terminal of device has adopted highly doped leakage, the problem of the OFF state electric leakage that causes is injected in the drain terminal hole that has solved the existence of Schottky source drain MOSFET device, make the OFF leakage current of device reduce many, ON state current at device does not have under the situation of influence like this, and the switch attitude current ratio of device is greatly improved.
It is compatible mutually with traditional Schottky barrier source drain MOSFET transistor fabrication technology that the present invention proposes its preparation process of MOS transistor (SSRD MOSFET) of Schottky Barrier Contact source end and the doping drain terminal of raising, simultaneously since the ion implantation technology step before the grid structure forms, therefore lower heat budget is arranged, make the application of high-K gate dielectric and metal gate material that bigger space be arranged.
Description of drawings:
Fig. 1 is that ion injects the also processing step schematic diagram of deposit medium protective layer on Semiconductor substrate;
Fig. 2 is the processing step schematic diagram of chemical wet etching medium protective layer and doping semiconductor layer;
Fig. 3 is the processing step schematic diagram of growth gate dielectric layer and deposit gate electrode;
Fig. 4 is that gate electrode forms and gate electrode is sacrificed the processing step schematic diagram that side wall forms;
Fig. 5 is the processing step schematic diagram that depositing metal annealing forms Schottky source;
Fig. 6 is a processing step schematic diagram of removing medium protective layer;
Among the figure:
1-silicon substrate 2-doped silicon layer
3-TEOS medium protective layer 4-gate dielectric layer
5-gate electrode layer 6-sacrifices side wall medium layer
The 7-Schottky source
Embodiment:
Following specific embodiment helps to understand the features and advantages of the present invention, but enforcement of the present invention never only is confined to described embodiment.
One specific embodiment of manufacture method of the present invention comprises extremely processing step shown in Figure 6 of Fig. 1:
1. as shown in Figure 1, the crystal orientation of used body silicon silicon chip silicon substrate (1) is (100), and the tagma is initially light dope, adopts conventional cmos shallow-trench isolation fabrication techniques active area isolation layer on substrate; Carry out ion then and inject, the energy that ion injects is 30KeV, and implanted dopant is As; Follow deposit one deck TEOS medium protective layer (2), thickness is 50-100nm.
2. as shown in Figure 2, carry out a photoetching, etching TEOS medium protective layer (3), then etching doped silicon layer (2) is up to the undoped silicon substrate.
3. as shown in Figure 3, growth gate dielectric layer (4), gate dielectric layer (4) is a silicon dioxide, its thickness is 1-5nm.The formation method of gate medium can also be one of following method: conventional thermal oxidation, nitrating thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD); Deposit gate electrode layer (5) doped polysilicon layer, the thickness of polysilicon layer is 80-150nm.The gate material of institute's deposit can also be the poly-SiGe alloy.
4. adopt as shown in Figure 4, the polysilicon layer of conventional cmos technology photoetching and the deposit of etching institute.With sacrifice side wall medium layer (6) silicon nitride of LPCVD deposit 10-30nm, then use back quarter (etch-back) technology to form the silicon nitride side wall in gate electrode one side, its partial width that links to each other with gate dielectric layer is 5-20nm.
5. as shown in Figure 5,,, form the Schottky source (7) that metal silicide is made device with silicon through the low temperature thermal annealing with MOCVD method deposit layer of metal Pt.
6. as shown in Figure 6, remove TEOS medium protective layer (3).
Enter the conventional cmos later process at last, comprise deposit passivation layer, opening contact hole and metallization etc., can make the MOS transistor (SSRD MOSFET) of described Schottky Barrier Contact source end and the doping drain terminal of raising.
Claims (10)
1. a MOS transistor comprises a gate electrode, a gate dielectric layer, a gate electrode side wall medium layer, semi-conductive substrate, a source region and a drain region; Described source region is made of the compound-material that metal or metal and semiconductor form, and described drain region forms by semiconductor is highly doped, lays respectively on the Semiconductor substrate, the both sides of gate electrode, and the drain region has the structure of raising; Described gate dielectric layer is positioned under the gate electrode, on the Semiconductor substrate, both sides link to each other with the drain region with the source region respectively; Described gate electrode side wall medium layer is positioned at gate electrode near on source region one side, the gate dielectric layer.
2. MOS transistor as claimed in claim 1, the thickness that it is characterized in that described gate dielectric layer is 1-20nm, the thickness of gate electrode is 80-150nm, the gate electrode side wall medium layer in the gate electrode side, the width of the part that links to each other with gate dielectric layer is 5-20nm.
3. the manufacture method of a MOS transistor may further comprise the steps:
(1) ion injects the formation high-doped zone on Semiconductor substrate;
(2) deposit one deck medium protective layer;
(3) chemical wet etching forms a ledge structure up to undoped layer;
(4) growth gate dielectric layer;
(5) deposit gate electrode layer, etching forms gate figure;
(6) side wall medium layer is sacrificed in deposit, and etching forms grid side wall figure;
(7) deposit layer of metal, and process annealing are then removed unreacted metal;
(8) remove medium protective layer;
(9) enter the CMOS later process at last, comprise deposit passivation layer, opening contact hole and metallization, can make described MOS transistor.
4. manufacture method as claimed in claim 3 is characterized in that, the semiconductor substrate materials in the described step (1) is selected from: Si, Ge, SiGe, GaAs or other II-VI, the binary or the ternary semiconductor of III-V or IV-IV family.
5. manufacture method as claimed in claim 3 is characterized in that, the insulating material of the medium protective layer in the described step (2) is selected from: silicon dioxide, silicon nitride, aluminium nitride, silester.
6. manufacture method as claimed in claim 3 is characterized in that, the gate dielectric material in the described step (4) is selected from: silicon dioxide, hafnium oxide, hafnium nitride.
7. manufacture method as claimed in claim 3 is characterized in that, the method for described step (4) growth gate dielectric layer is selected from one of following method: nitrating thermal oxidation, chemical vapor deposition, physical vapor deposition.
8. manufacture method as claimed in claim 3 is characterized in that, sacrifices the side wall medium layer material in the described step (6) and is selected from: silicon nitride, silester or other all have high corrosion to select the thin-film material of ratio with silicon and silica.
9. manufacture method as claimed in claim 3 is characterized in that, the metal material in the described step (7) is selected from: Pt, Er, Co, Ni and other can form the metal of compound with the substrate semiconductor material by annealing.
10. as the described manufacture method of the arbitrary claim of claim 3～9, it is characterized in that: the injection energy that described ion injects is 30eV-200KeV; The thickness of the gate dielectric layer of growing on the Semiconductor substrate is 1-20nm, and the thickness of gate electrode layer is 80-150nm, the gate electrode side wall medium layer in the gate electrode side, the width of the part that links to each other with gate dielectric layer is 5-20nm.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2006101403912A CN100448028C (en) | 2006-12-08 | 2006-12-08 | A MOS resistor and its manufacture method |
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| CNB2006101403912A CN100448028C (en) | 2006-12-08 | 2006-12-08 | A MOS resistor and its manufacture method |
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| CN100448028C true CN100448028C (en) | 2008-12-31 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101807602A (en) * | 2010-03-25 | 2010-08-18 | 复旦大学 | Asymmetrical source-drain field effect transistor and preparation method thereof |
| CN102142461B (en) * | 2011-01-07 | 2013-01-30 | 清华大学 | Grid controlled Schottky junction tunneling field effect transistor and forming method thereof |
| CN102206799B (en) * | 2011-04-20 | 2012-12-19 | 北京大学 | Surface passivation method for germanium-based MOS (Metal Oxide Semiconductor) device substrate |
| CN103606563B (en) * | 2013-10-22 | 2016-06-01 | 清华大学 | Without knot type tunneling field-effect transistor and forming method thereof |
| CN106024712B (en) * | 2016-07-29 | 2018-09-21 | 东莞华南设计创新院 | A kind of production method of autoregistration GaAs PMOS device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5834810A (en) * | 1996-10-17 | 1998-11-10 | Mitsubishi Semiconductor America, Inc. | Asymmetrical vertical lightly doped drain transistor and method of forming the same |
| US6194768B1 (en) * | 1998-10-23 | 2001-02-27 | Advanced Micro Devices, Inc. | High dielectric constant gate dielectric with an overlying tantalum gate conductor formed on a sidewall surface of a sacrificial structure |
| US6429077B1 (en) * | 1999-12-02 | 2002-08-06 | United Microelectronics Corp. | Method of forming a lateral diffused metal-oxide semiconductor transistor |
| US6503833B1 (en) * | 2000-11-15 | 2003-01-07 | International Business Machines Corporation | Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby |
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2006
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5834810A (en) * | 1996-10-17 | 1998-11-10 | Mitsubishi Semiconductor America, Inc. | Asymmetrical vertical lightly doped drain transistor and method of forming the same |
| US6194768B1 (en) * | 1998-10-23 | 2001-02-27 | Advanced Micro Devices, Inc. | High dielectric constant gate dielectric with an overlying tantalum gate conductor formed on a sidewall surface of a sacrificial structure |
| US6429077B1 (en) * | 1999-12-02 | 2002-08-06 | United Microelectronics Corp. | Method of forming a lateral diffused metal-oxide semiconductor transistor |
| US6503833B1 (en) * | 2000-11-15 | 2003-01-07 | International Business Machines Corporation | Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby |
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