CN100451886C

CN100451886C - Feedback signal counting circuit of grating encoder

Info

Publication number: CN100451886C
Application number: CNB2006100165156A
Authority: CN
Inventors: 刘廷霞; 王伟国; 姜润强
Original assignee: Changchun Institute of Optics Fine Mechanics and Physics of CAS
Current assignee: Changchun Institute of Optics Fine Mechanics and Physics of CAS
Priority date: 2006-01-12
Filing date: 2006-01-12
Publication date: 2009-01-14
Anticipated expiration: 2026-01-12
Also published as: CN101000494A

Abstract

A feedback signal counting circuit of grating coder is prepared as using counter in digital signal processor to count pulse outputted by grating coder and transmitting counted value to microcontroller by digital signal processor through control of internal circuit on programmable logic component.

Description

Feedback signal counting circuit of grating encoder

Technical field

The invention belongs to the servo control technique field, relate to the counting of a kind of position and velocity feedback element and read circuit.

Background technology

In the high-precision servo control system, usually will adopt resolution is that nano level grating encoder is as position and velocity feedback element, and be nano level grating encoder for resolution, utilize debating of d type flip flop sum counter composition to be difficult to the accurate counting of realization to grating to counting circuit, even best debates to counting circuit, the error of more than 100 code value is arranged also when static.

Summary of the invention

The object of the invention provides a kind of feedback signal counting circuit of grating encoder, utilizes the accurate counting of digital signal processor realization to high-resolution gration encoder feedback signal.

The present invention includes digital signal processor 1, programmable logic device (PLD) 2, microcontroller 3.Described programmable logic device (PLD) 2 inner structures comprise DSP decoding scheme 4, the first NOR-logic doors 5, latch 6, triple gate 7, the second NOR-logic doors 8, microcontroller decoding scheme 9; The capturing unit of digital signal processor 1 links to each other with the positive and negative pulse output end mutually of grating encoder, and the pulse of grating encoder output is counted; The address wire of digital signal processor 1, reading writing signal line, data bus link to each other with DSP decoding scheme 4, the first NOR-logic door 5, latch 6 respectively; DSP decoding scheme 4 links to each other with the first NOR-logic door 5, and the first NOR-logic door, 5 output terminals link to each other with latch 6; DSP decoding scheme 4 carries out address decoding, according to decoding address and read-write, and the first NOR-logic door, 5 output logic control signals, control figure signal processor 1 is delivered to count value on the data bus, deposits simultaneously in the latch 6.Microcontroller 3 data buss, reading writing signal line, address bus link to each other with triple gate 7, the second NOR-logic door 8, microcontroller decoding scheme 9 respectively, latch 6 links to each other with triple gate 7, microcontroller decoding scheme 9 links to each other with the second NOR-logic door 8, and the second NOR-logic door, 8 output terminals link to each other with triple gate 7; Microcontroller decoding scheme 9 carries out address decoding, and according to decoding address and read-write, the second NOR-logic door, 8 output logic control signals are opened triple gate 7, and the count value that latch is 6 li is read in microcontroller 3.

Beneficial effect: the present invention utilizes 1 pair of grating encoder of digital signal processor to count, and the counting precision height is nano level grating encoder for resolution, has only the error of 1～2 code value.The present invention is mainly used in the High Accuracy Control of servo-drive system.

Description of drawings

Fig. 1 is a structural representation of the present invention, also is Figure of abstract.1 is digital signal processor among the figure, 2 programmable logic device (PLD), and 3 microcontrollers, 4 is the DSP decoding scheme, 5 first NOR-logic doors, 6 latchs, 7 triple gates, 8 second NOR-logic doors, 9 microcontroller decoding schemes.

Embodiment

It is TMS320F240 that digital signal processor 1 of the present invention adopts model, and programmable logic device (PLD) 2 is selected the EPM7128 of ALTERA company for use, and microcontroller 3 is selected the PC104 computing machine for use.

The positive and negative phase pulse output end of grating encoder links to each other with QEP2 with the QEP1 of TMS320F240 digital signal processor 1,16 bit data bus of TMS320F240 digital signal processor 1 are assigned on the latch 6, high 2 bit address bus A14, A15 is assigned on the DSP decoding scheme 4, read-write/the IS of TMS320F240 digital signal processor 1 links to each other with the first NOR-logic door, 5 input ends with DSP decoding scheme 4 output terminals, and the first NOR-logic door, 5 output terminals link to each other with latch 6; 16 position datawires of PC104 computing machine are assigned on the

triple gate

7, and 8 bit address lines are assigned on the PC104 decoding scheme, the PC104 computing machine read signal/SIOR, PC104 decoding scheme output terminal links to each other with the second NOR-logic door, 8 input ends.

The course of work of the present invention: the positive and negative phase pulse signal of grating encoder is input to the QEP1 and the QEP2 of TMS320F240 digital signal processor, debate to the circuit sum counter digital signal processor inside, just changeing the count value of hour counter when scrambler and progressively increasing, when the count value of scrambler counter-rotating hour counter is successively decreased.Carry out address decoding by DSP decoding scheme 4, and by I/O read-write/IS, digital signal processor was delivered to the count value of counter on the DSP data bus by the cycle of 800Hz, deposited in the latch simultaneously; Carry out address decoding by the PC104 decoding scheme, and the signal/SIOR that reads by PC104, by the cycle of 800Hz the count value in the latch is read in PC104.

Claims

1, a kind of feedback signal counting circuit of grating encoder is characterized in that comprising digital signal processor (1), programmable logic device (PLD) (2), microcontroller (3); Described programmable logic device (PLD) (2) inner structure comprises DSP decoding scheme (4), the first NOR-logic door (5), latch (6), triple gate (7), the second NOR-logic door (8), microcontroller decoding scheme (9); The capturing unit of digital signal processor (1) links to each other with the positive and negative pulse output end mutually of grating encoder; The address wire of digital signal processor (1), reading writing signal line, data bus link to each other with DSP decoding scheme (4), the first NOR-logic door (5), latch (6) respectively; DSP decoding scheme (4) links to each other with the first NOR-logic door (5), and first NOR-logic door (5) output terminal links to each other with latch (6); Microcontroller (3) data bus, reading writing signal line, address bus link to each other with triple gate (7), the second NOR-logic door (8), microcontroller decoding scheme (9) respectively, latch (6) links to each other with triple gate (7), microcontroller decoding scheme (9) links to each other with the second NOR-logic door (8), and second NOR-logic door (8) output terminal links to each other with triple gate (7).

2, feedback signal counting circuit of grating encoder according to claim 1, it is characterized in that it is TMS320F240 that digital signal processor (1) adopts model, programmable logic device (PLD) (2) is selected the EPM7128 of ALTERA company for use, and microcontroller (3) is selected the PC104 computing machine for use.

3, feedback signal counting circuit of grating encoder according to claim 2 is characterized in that the positive and negative phase pulse output end of grating encoder links to each other with QEP2 with the QEP1 of TMS320F240 digital signal processor; 16 bit data bus of TMS320F240 digital signal processor are assigned on the latch, high 2 bit address bus A14, and A15 is assigned on the DSP decoding scheme, and the read-write/IS of TMS320F240 digital signal processor links to each other with the first NOR-logic door input end; 16 position datawires of PC104 computing machine are assigned on the triple gate, and 8 bit address lines are assigned on the PC104 decoding scheme, the PC104 computing machine read signal/SIOR, PC104 decoding scheme output terminal links to each other with the second NOR-logic door input end.