CN100451914C - 锁相环迅速加电方法和装置 - Google Patents

锁相环迅速加电方法和装置 Download PDF

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CN100451914C
CN100451914C CNB028169697A CN02816969A CN100451914C CN 100451914 C CN100451914 C CN 100451914C CN B028169697 A CNB028169697 A CN B028169697A CN 02816969 A CN02816969 A CN 02816969A CN 100451914 C CN100451914 C CN 100451914C
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帕勒·比尔克
约恩·瑟伦森
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Abstract

提供了一种PLL倍频器，其等待时间几乎与PLL的唤醒时间相等。当PLL正在获取锁相时，通过保证时钟信号不包含高于PLL目标频率及低于预定阈值频率的频率而向处理器提供一操作时钟信号。特别地，提供分频器和频率检测器，以防止时钟信号的频率在阈值和目标频率定义的范围之外操作。

Description

锁相环迅速加电方法和装置
相关申请
本申请要求2001年8月29日在35U.S.C.§119(e)基础上由Allen等提交的申请号为60/315,655，标题为“DIGITAL BASEBANDPROCESSOR”的临时申请的权益。以上临时申请的全部合并在本申请中以作参考。
技术领域
本发明涉及锁相环(PLL)倍频器，特别是用于通过在PLL的锁定时间间隔期间提供操作时钟信号而减少与激活PLL相关的消耗的方法和装置。
背景技术
在许多计算系统、数字设备等之中，经常将处理器需要的各种时钟信号同步到单一的基准时钟信号，然后分配到处理器适当的逻辑电路、子系统、和元件。术语“处理器”通常指任何执行逻辑运算、计算任务、和/或控制功能的设备。处理器可以包括一个或多个子系统、元件、和/或其他处理器。处理器一般包括各种逻辑和/或数字元件，它们利用时钟信号来操作，用来锁存数据、前进和/或排序逻辑状态、同步计算和逻辑操作、和/或提供其他定时功能。
例如，便携式电话包括具有多个子系统或元件的处理器，比如数字信号处理器(DSP)，它以高时钟频率动作，用来执行实时、计算密集并且经常是时间严格的任务；微控制器(MCU)，以较低时钟频率动作，例如执行各种控制功能、协调事件、执行系统软件等等。此外，DSP和MCU可以各自操作或者具有以多个时钟频率动作的支持元件。在任何指定时间时钟频率的需求取决于处理器的计算需求。
由模拟或数字锁相环(PLL)或延迟锁定环(DLL)实现的倍频器经常用来生成高频时钟信号，并将其锁定为与基准时钟同相。然后该高频时钟信号可以提供用来驱动逻辑电路或元件、提供给数字设备的时钟分配树、和/或另外分配给处理器来满足系统的计时需求。这样，处理器各种元件的时钟频率需求可以由单一的基准信号支持和同步到单一的基准信号。
提供时钟信号中的术语“提供”描述了信号没有被禁用、被旁路、被禁止(gated off)、或被阻止应用于所指的逻辑门、数字元件和/或电路等，或由其接收并用于操作。通常，术语时钟元件将用在这里描述任何以上提到的元件。例如，时钟信号可以提供给旁路选择、禁止逻辑、时钟分配树等等，但最终提供给一个或多个诸如逻辑门、触发器等需要如逻辑电平、定时信号、锁存器等的低电平元件。这些低电平元件或这种低电平元件的集合通常被称为时钟元件。
图1为从输入时钟信号生成输出时钟信号的现有的倍频器10的框图。倍频器10包括PLL 12，该PLL 12生成高频输出时钟信号32并锁定该信号与输入时钟信号30同相。
术语时钟信号或简单时钟通常是指任何模拟或数字周期性信号，尤其是用来为逻辑元件、数字电路或其他(即，时钟元件)生成至少一个定时信号或逻辑电平的周期性信号。时钟信号可以是各种波形中的任何一种，这些波形包括但不限定于正弦波、方波、脉冲串等。例如，时钟信号可以是最终用作前进处理器的状态、锁定数据、执行逻辑操作等的信号。诸如摆动(swing)正弦波的信号，和来自例如从中形成和/或导出一个或多个时钟信号的晶体振荡器的信号也可以考虑为时钟信号。
PLL 12包括相位比较器22、环路滤波器24、压控振荡器26、和分频器28。相位比较器22接收输入时钟信号30和反馈时钟信号34，并比较两信号的相位。输入时钟信号30可以例如是系统时钟，该系统时钟为处理器提供基准时钟，利用该基准时钟来同步分配给处理器的较高频率的时钟信号。反馈信号34与输出时钟信号32相关，具有与输出时钟信号32相同的相位和与输入时钟信号30相同的频率。相位比较器22提供相位误差信号40，该信号与输入时钟信号30和反馈时钟信号34之间的差异成比例。
环路滤波器24用来滤除噪声并使相位误差信号40平滑。例如，环路滤波器24可以包括低通滤波器。此外，环路滤波器24将相位误差信号转换为一信号，该信号表示用来减少相位误差信号40大小所需要的电压的变化。由环路滤波器24产生的电压校正信号42提供给VCO，用来校正输入时钟信号30和反馈信号34之间的相位差异。
压控振荡器(VCO)一般为振荡器提供电压，该振荡器产生具有与所提供电压成比例的频率的信号。这样，VCO 26接收来自环路滤波器24的电压校正信号42，并相应地调整提供给振荡器的电压。从而调整输出时钟信号32的频率，以校正由相位比较器22检测到的相位误差(即输出时钟信号32被改进为与输入时钟信号30同相)。
输出时钟信号32通过分频器28反馈到相位比较器。分频器28可以是例如n分计数器，对输出时钟信号的频率进行分频，来提供用来与输入时钟信号30进行比较的反馈时钟信号34。这样，选择分频器比率n来匹配由VCO得到的倍频器比率，从而提供反馈时钟信号，它具有与输入时钟信号相同的频率并且与输出时钟信号相同的相位。
一般伴随生成被锁相到输入时钟信号的输出时钟信号会有各种延迟。特别是锁相环收敛需要一定时间间隔(即，锁定输出时钟信号与输入时钟信号同相)。当获得相位锁定时发生的延迟经常称为锁定时间。
图2为图解利用如图1所示的倍频器产生锁相到输入时钟信号的输出时钟信号时，经常伴随其发生的延迟的时序图。座标图5表示输出时钟信号(例如，输出时钟信号32)的频率作为时间的函数。在图2中，将假定PLL在时间t0是未激活的。例如，没有输入信号提供给PLL，没有启动VCO，没有产生输出信号。
换言之，时间t0表示何时想要给倍频器提供输入时钟并给VCO加电的时间，即何时想要激活PLL。
在稳定的输入信号能够提供给PLL的相位比较器之前需要一定数量的时间。该时间是间隔的一部分，称为唤醒时间，表示为间隔60。不同的PLL或DLL实现会具有其他与唤醒时间相关的延迟。例如，在图1的PLL中，具有与启动VCO开始给振荡器提供电压相关的延迟。通常，唤醒时间是指与启用各种信号和/或PLL的元件相关的时间间隔。特别是，唤醒时间是指想要产生输出信号与信号发生器第一次输出信号之间的时间间隔。
此外，会有与PLL获得输入和输出时钟信号之间的相位锁定所需要的时间相关的延迟。这些延迟表示为时间间隔64和66，分别称作PLL锁定时间和PLL锁定定时器。时间间隔64表示获得输入和输出时钟信号之间的相位锁定所实际需要的时间。然而，经常很难精确检测出何时PLL已经被有效地锁定。更为复杂的是，实际锁定时间会变化，作为所期望的倍频器的频率增长、输入时钟信号中的噪声量等的函数。这样的话，在预计PLL的锁定时间时会有一定程度的不确定性。
为了防止检测和/或预计实际锁定时间中的不确定性，锁定定时器可以用来记录等于或超过PLL锁定时间最坏情况的时间间隔。当PLL第一次激活时，锁定定时器开始递减计数。一般，直到锁定定时器期满，才认为PLL被锁定和稳定。因此，倍频器的等待时间经常由锁定定时器中记录的延迟来约束(例如，间隔66)。术语等待一般是指从倍频器输出有效的时钟信号之前所经过的时间间隔。
有效的时钟信号是指可以提供给时钟元件用来执行预期功能的时钟信号。一般，有效的时钟信号提供可用的定时参考和/或逻辑信号，从而可以执行有用的计算和/或处理，而不会丢失数据或产生其他有害的影响。例如，有效的时钟信号可以是足以向前推进处理器、锁存数据、同步逻辑时间、和/或执行其他需要时钟信号的逻辑操作的时钟信号，操作不会超出时钟元件的容许偏差并且不会导致时钟元件操作错误。
已经提出各种方法来减少倍频器的等待时间。然而，这些方法经常集中在降低锁相环的锁定时间上，从而减少由锁定定时器需要的延迟来调节最坏情况的锁定时间。
发明内容
申请者已经发现通过减少倍频器锁定时间这种方法来获得等待时间，当系统等待倍频器获得相位锁定期间，仍然有显著的处理时间的损失和功率消耗。此外，一些处理情况会需要具有比通过减少倍频器锁定时间这种方法获得的等待时间短的倍频器。
因此，根据本发明的一个实施例包括一种用于减少激活倍频器的消耗的方法，该倍频器提供与输入时钟信号同步的第一输出时钟信号。该方法包括操作：将具有第一频率的输入时钟信号提供给倍频器，用来同步第一输出时钟信号；产生第一输出时钟信号，该第一时钟信号具有充分收敛到目标频率的第二频率，该目标频率大于第一频率，第一输出时钟信号的产生决定锁定时间间隔的开始；从第一输出时钟信号产生第二输出时钟信号，该第二输出时钟信号具有第三频率，该第三频率小于第二频率并且不超过目标频率；确定第一输出时钟信号何时与输入时钟信号同步，同步的确定结束锁定时间间隔；和在锁定时间间隔期间，将第二输出时钟信号提供给至少一个时钟元件，在锁定时间间隔之后，将第一输出时钟信号提供给至少一个时钟元件。
根据本发明的又一个实施例，包括一种用于在倍频器的锁定时间间隔期间提供操作时钟信号的方法，该倍频器适于提供与输入时钟信号同步的输出时钟信号。该方法包括操作：通过将输入时钟信号与输出时钟信号连接在反馈控制环路中，将输入时钟信号与输出时钟信号之间的相位差异基本减少至零。在减少输入时钟信号与输出时钟信号之间的相位差异的操作期间，该方法还包括：利用将输出时钟信号的频率N分频，来提供频率降低后的时钟信号；和仅在确定频率降低后的输出时钟信号具有超过规定阈值频率的频率之后，将频率降低后的输出时钟信号提供给至少一个时钟元件。
根据本发明的又一个实施例，包括比较器，用于接收具有第一频率的输入时钟信号和反馈信号，该比较器适于提供误差信号，该误差信号表示在输入时钟信号与反馈信号之间的第一特性的差异；信号发生器，连接至该比较器，用来提供具有第二频率的输出时钟信号，发生器基于误差信号调整输出时钟信号的第二特性，来降低在输入时钟信号与反馈信号之间的第一特性的差异；反馈环路，基于输出时钟信号来将反馈信号提供给比较器，反馈环路与所需第一时间间隔相关联，来将在输入时钟信号与输出时钟信号之间的第一特性的差异基本上减少至零；和用于在第一时间间隔期间基于输出时钟信号来提供操作信号的装置。
根据本发明的又一个实施例，包括一种倍频器，适于在输出时钟信号已经与输入时钟信号同步之前提供操作时钟信号，该倍频器包括：比较器，用于接收具有第一频率的输入时钟信号和反馈信号，该比较器适于提供误差信号，该误差信号表示在输入时钟信号与反馈信号之间的第一特性的差异；信号发生器，连接至比较器，用来提供具有第二频率的输出时钟信号，发生器基于误差信号调整输出时钟信号的第二特性，来降低在输入时钟信号与反馈信号之间的第一特性的差异；第一分频器，用于降低第二频率，产生提供给相位比较器的反馈时钟信号；第二分频器，通过将第二频率N分频，来提供具有第三频率的第二输出时钟信号；和检测器，适于监控第一输出时钟信号和第二输出时钟信号中的至少一个，该检测器配置为将第二输出时钟信号提供给至少一个时钟元件，该操作仅在检测器确定第三频率已经超过规定的阈值频率之后进行，该规定的阈值频率大于第一频率。
附图说明
图1为锁相环(PLL)倍频器的框图；
图2为图1的PLL倍频器中与激活和获得相位锁定相关的延迟的时序图；
图3图解用于包括PLL倍频器的处理器的定时方案和控制；
图4图解根据本发明的实施例，降低了等待时间的PLL倍频器；
图5为图4所示的PLL倍频器中与激活和获得相位锁定相关的延迟、及PLL倍频器的减少了的等待时间的时序图；
图6图解根据本发明另一个实施例的减少了等待时间的PLL倍频器；
具体实施方式
在许多设备，尤其是由电池提供能量的设备中，比如移动电话、便携式电脑、个人数字助理(PDA)、以及其他手提式设备，功率消耗会消极影响在需要再次充电或替换电源之前这些设备的操作时间。
申请者已经发现设备的功率消耗与提供给设备处理器的电压的平方相关，并与处理器操作的频率成比例。设备的功率消耗可以表示为：
PD＝cV2F(方程1)
这里：
V＝供给设备的电压(即Vdd与GND之间的电压差)
F＝频率(例如处理器的时钟频率)
c＝一个由在电压V和频率F工作的电路所决定的常量
此外，申请者也认识到，操作处理器所需要的电压可能是提供给处理器的时钟频率的函数。
因此，一种减小设备功率消耗的方法就是将提供给处理器的频率动态调整至满足处理器的计算和/或处理需求所需的最小频率。
图3所示的系统定时方案将用来说明在典型处理器中会发生的各种处理情况。例如，处理器可能具有与图3所示的系统定时方案近似的系统定时方案。PLL多路复用器10接收作为输入的系统时钟信号80并输出高频时钟信号82。然后，高频时钟信号82提供给各种处理器元件，这些元件在三种所示的时钟域中操作：时钟域90a、时钟域90b、和时钟域90c。
时钟域90a，例如将时钟信号84提供给数字信号处理器(DSP)100a和专用DSP协处理器100b。时钟信号84的频率(即，提供给时钟域90a中元件的时钟的频率)由多路复用器70a和与门72a决定。多路复用器70a选择高频时钟信号82或者系统时钟信号80分配给在时钟域90a中操作的各种时钟元件。与门72a或者提供由多路复用器70a选择的时钟信号，或者禁止时钟信号，从而禁止用来将时钟信号84分配给DSP和协处理器的时钟元件的时钟树(未图示)。
相似的，时钟域90b将时钟信号86提供给，例如，由DSP子系统用来交换数据、传送控制信号等的专用总线(DSP总线100c)，和诸如高速缓存或暂时存储器这样的专用存储器(DSP SRAM 100D)。多路复用器70b选择高频时钟信号或者系统时钟，与门或者允许或者禁止由多路复用器提供的时钟信号。此外，当高频时钟被选择时，分频器74b允许高频时钟信号82降低频率(例如，降低2倍)。
时钟域90c将时钟信号88提供给处理器100的各种其他典型的子系统和元件。尤其是在域90c中操作的微控制器(MCU)100e、系统存储器100f、外围设备总线100g、和外部总线100h。分频器74c允许高频时钟信号82在提供给多路复用器74c，用来象上述时钟域90a和90b那样选择或旁路之前，通过因数2、4、6、8、10、12、14降低频率。
处理器100可以具有许多工作状态，其中一个或多个元件处于空闲状态，和/或一个或多个时钟域不需要操作。例如，考虑包括处理器100的便携式电话。当便携式电话电源开通，但没工作(即，待机状态)的时候，便携式电话与其当前位于的小区的基站保持连接。基站周期性地(例如，每2秒钟)向所有小区电话广播关于是否已经接收到呼叫和电话是否应该转变为呼叫操作状态的小区信息。已知广播寻呼信道，便携式电话必须监控寻呼信道，以确定是否已经接收到呼叫。
然而，为了从寻呼信道获得信息需要很少的处理功率。如此这样，在寻呼信道获得期间，处理器仅需要系统时钟运行。相反，一旦信息进入便携式电话(例如，存储到存储缓冲器)，为了确定是否有呼叫，需要DSP来处理该信息。然而，这种工作状态中大部分时间不需要DSP。
如此这样，当处理器的计算性需求不需要PLL时，期望将其禁止，例如，当DSP在空闲状态时。通过DSP进入空闲状态，可以禁用高频时钟信号(即，倍频器可以休眠或者禁用)。然而，当再次需要DSP的处理功率时，例如，用来处理从寻呼信道接收的信息时，为了提供处理器上增长的需求所需的必要的时钟频率，必须激活PLL。
然而，会有与激活倍频器相关的消耗，它与PLL的等待时间有关。尤其是，在PLL的锁定时间间隔期间，消耗功率但没有做计算性的工作。伴随激活倍频器带来的有效处理时间的损失，使得在某些情况下，优选地需要倍频器保持激活，而不管额外的功率消耗。
术语激活倍频器用于说明增加倍频器输出时钟信号的频率所涉及的操作。将倍频器从休眠或禁用状态启用和增加PLL的倍频器比率都认为是激活倍频器。伴随激活PLL的消耗可以认为具有时间成分和功率成分。
申请者已经认识到在输出时钟信号被认为是有效的之前，没有必要获得输入时钟信号与输出时钟信号之间的相位锁定。尤其是，申请者已经确定，输出时钟足以达到规定的最小频率并不超出规定的最大频率，从而使输出时钟被认为是操作时钟。最小和最大频率由将输出时钟信号提供给的时钟元件的特性来决定。
例如，如果输出时钟信号是用于驱动处理器的时钟，则该时钟信号需要达到能够向前推进处理器而不会导致时序破坏的最小频率。此外，输出时钟信号需要保持在处理器支持的最大频率之下，以保证正确操作。
在根据本发明的一个实施例中，通过在倍频器的锁定时间间隔期间提供操作时钟信号来减少激活倍频器的消耗。尤其是，倍频器的等待时间减少为与倍频器的唤醒时间基本相等。如此这样，在锁定时间期间可以完成计算性的工作，并且增加了激活倍频器期间的有效的处理时间。
下面更详细的阐述与根据本发明的方法与装置相关的概念和它们的实施例。应该理解以上讨论的本发明的各种方面以及以下的概要，可以用多种形式实现，本发明不限定于任何特定的实现方式。特定实现的例子仅用于说明的目的。
例如，下面阐述的PLL倍频器将用于说明本发明的各种方面。然而，倍频器的领域包括多种变形和实现，此处无法都涉及。应该理解本发明不限定于任何特定的倍频器实现，如此这样，任何具有一定时间间隔，用来将输出时钟信号与输入时钟信号同步的倍频器都认为在本发明的范围之内。
术语“倍频器”应用于提供与输入时钟信号同步的输出时钟信号的任何元件，该输出时钟信号具有大于输入时钟信号的频率。通常，倍频器包括信号发生器，用来产生具有期望频率的信号；用来将所产生的信号与输入时钟信号进行比较的方法；根据该比较用来将所产生的信号与输入时钟信号同步的方法。
当该比较是基于相位的，术语锁相环(PLL)将用于说明这样的倍频器。
可以通过各种方式实现相位比较，比如边沿跟踪(即，比较时钟信号的上升和/或轨迹边沿)、信号过零、信号导数中的零等等。此外，可以通过各种方法中的任何一种来获得相位锁定，比如，根据相位比较来改变输出时钟信号的频率、根据相位误差来延迟输出时钟信号等等。
图4表示根据本发明的倍频器的一个实施例。倍频器10‘包括锁相环12’。该锁相环的操作方式与图1所表示的PLL 12相似。特别地，PLL 12’包括相位比较器22’，提供相位误差信号40’，该信号表示输入时钟信号30’与反馈时钟信号34’之间的相位差异。环路滤波器24’接收相位误差信号40’并提供电压校正信号42’。VCO 26’接收校正信号42’并调整提供给振荡器的电压，来提供趋向减少相位误差信号40’幅度的输出时钟信号。分频器28’对输出时钟信号进行分频，提供反馈时钟信号34’，该信号具有与输入时钟信号30’基本相同的频率，和与输出时钟信号32’基本相同的相位。
此外，倍频器12’包括频率检测器50和分频器52。由VCO 26’产生的输出时钟信号32’被提供给检测器50和分频器52。检测器50和分频器52确保提供给处理器的时钟信号中不包含可能导致处理器操作错误或者导致数据丢失的频率，即，检测器50和分频器52提供操作时钟信号36。
在唤醒间隔(例如，图2中的间隔60)之后和锁定输出时钟信号与输入时钟信号同相之前，输出时钟信号容易频率超出接收时钟信号的时钟元件所预期的频率。例如，输出时钟信号会经历目标频率之上的频率，该目标频率是指由倍频器达到的预期频率。尤其是，目标频率是PLL已经锁定后由VCO产生的信号的频率。
此外，就在VCO启动之后(即，唤醒时间间隔结束的时候)，输出时钟信号会经历低于接收时钟信号的时钟元件所需要的阈值频率的频率。如此这样，为了提供操作时钟信号，应该抑制由阈值频率和目标频率所定义的频率范围之外的频率。
图5表示PLL的激活间隔的频率与时间的特性曲线图，该PLL不是临界阻尼的。当考虑PLL的等待时间，PLL经常不是临界阻尼的，即，PLL不是阻尼的以防止目标频率的超调。典型的，阻尼PLL将具有延长的锁定时间，并且不适合许多考虑PLL激活消耗的应用。
PLL的输出时钟信号的目标频率(即，由倍频器得到的频率)由频率轴上的虚线表示为频率110。例如，目标频率可以是如图3说明的提供给DSP的高频时钟。
在启动VCO之后(即，在时间tw)，输出时钟信号几乎瞬时达到频率100，由时间tw处的垂直线示意性表示。如图所示，在锁定时间间隔期间，输出时钟信号的频率跳跃，并且PLL趋向超调目标频率。如此这样，输出时钟信号将经历一直到频率120的频率。然后时钟信号在目标频率附近振荡，直到收敛到目标频率作为PLL锁定。
那些超过目标频率110的频率，如果提供给例如处理器，可能引起处理器操作错误。这可能导致破坏或丢失数据、错误定时或同步、或者可能对处理器的操作产生其他坏影响。如此这样，如果认为锁定时间间隔期间提供给处理器的时钟信号是操作性的，则应该抑制超过目标频率的那些频率。
为了阻止目标频率之上的频率应用到处理器的时钟元件，在图3说明的实施例中，输出时钟信号32’提供给分频器52。分频器52将输出时钟信号N分频，以确保不会由于超过时钟元件处理器操作所需最大频率的频率，而使时钟元件易丢失数据或者错误操作。
分频器52可以是例如二分计数器。然而本发明不限定于任何特定的分频器比率。设计考虑和PLL的特征会引导对每个特定实现的N的选择。
然而，N的选择应该阻止提供给处理器的时钟信号经历那些可能导致处理器操作错误的频率，即，应给提供操作时钟信号。
此外，接收时钟信号的时钟元件会具有使它能够操作的最小频率。例如，处理器的定时会依赖提供高于最小频率的时钟信号。为了确保当时钟信号第一次提供给时钟元件或元件时是操作性的，频率检测器50用来监控输出时钟信号。
仅仅当输出时钟信号超过阈值频率时，才允许将分频器的输出作为操作时钟信号36而提供。阈值频率取决于接收时钟信号的时钟元件的类型和需求。
图4表示由频率检测器控制的开关72，用来在锁定时间间隔期间，当已经超过了阈值频率后提供操作时钟信号36。然而，任何一种方法都可以用来当已经确定信号为操作性的之后，将时钟信号提供给时钟元件和元件。典型的，在PLL已经锁定之后，分频器52被旁路(例如，通过关闭开关72和打开开关70，或者通过某些相当的机构)，并且将输出时钟信号作为操作时钟信号提供给处理器的各种时钟元件。
如此这样，在PLL锁定时间间隔之间，倍频器10‘将操作时钟信号提供给处理器。然后在PLL锁定时间间隔之间，可以进行计算性的工作、逻辑操作、定时、和其他各种处理任务。倍频器的等待时间几乎等于PLL的唤醒时间，如此这样，减少了激活PLL的消耗。
此外，伴随激活PLL的时间消耗会适应处理环境，其中依赖于锁定时间的等待时间已经阻止倍频器被禁用。这样，提供给处理器的时钟频率能够动态调整，以符合处理器的计算性的需求，而不必在不需要计算等级时还保持高能量状态。
应该理解以上实施例中说明的元件的排列、数量、和类型仅是示范性的。对于本领域的技术人员而言，可以在设计上做许多变形。然而，这些变形不应该背离本发明的范围。
例如，提供用来抑制目标频率之上的频率的分频器(例如，分频器52)不需要是附加的和/或单独的分频器。例如，PLL的控制环路中的全部或部分分频器(例如，分频器28‘)可以用来实现对超调频率的抑制。
图6中，分频器28“被图解为一列串联连接的二分计数器。在第一个二分计数器之后分流出时钟信号，并提供作为操作时钟信号36’，即分频器52‘是分频器28“的第一个分频级。如此这样，分频器52‘提供频率减少因数2来抑制超过倍频器目标频率的那些频率。然而，取决于期望的频率减少，可以从分频器28“的任何级引出信号。此外，分频器28“不需要包括二分计数器，而可以是具有任何适当分频比率的任何适当的分频元件。
此外，用来确定何时已经超过阈值频率的频率检测器(例如，频率检测器50)可以检测时钟信号的频率，而不是检测如图7所示直接由VCO提供的信号的频率。例如，频率检测器可以监控已经提供到分频器或者从分频器分流出的信号的频率，该分频器用于抑制超过目标频率的频率(例如，分频器52、52‘)。
此外，频率检测器可以编程为检测何时时钟信号已经超过可变的阈值频率。例如，参照图3表示的处理器100，在给定时间从任何一个时钟域中选择的最大的分频因数可以决定阈值频率应该是什么，以确保将具有符合或超过时钟元件的最小频率需求的频率的时钟信号，提供给每个接收时钟信号的元件。作为例子，当时钟域90c选择了通过14因数分频，则需要增加阈值频率，当选择更小因数或没有减少因数时，则降低阈值频率。
在一些实施例中，不需要用于检测何时已经超过阈值频率的频率检测器。例如，信号发生器(例如，VCO)的特征和接收由倍频器输出的时钟信号的时钟元件的需求可能是这样的，即当启动信号发生器后由它提供的初始输出时钟信号已经在阈值频率之上。在这种情况下，可以用简单地检测信号发生器何时第一次开始输出信号，而不管频率的逻辑来替换频率检测器(例如，频率检测器50)。由于已知信号发生器立即达到超出阈值频率的频率，所以信号发生器一启动，输出时钟信号就是操作性的。
为了得到仅具有特定范围中的频率的输出时钟信号，对于本领域的技术人员而言，对于元件的数量、类型、和配置可以做许多其他的变更、变形、和替换。这些变形应该认为是在本发明的范围之内。
已经详细阐述了本发明的许多实施例，对于本领域的技术人员而言，将很容易对其做出各种变更和改进。这些变更和改进规定为在本发明的范围之内。
因此，以上的说明仅作为例子，并不限定。本发明仅由权利要求以及等价部分来限定。

Claims (33)

1.在提供与输入时钟信号同步的第一输出时钟信号的倍频器中，一种用于减少激活倍频器的消耗的方法，该方法包括操作：
将具有第一频率的输入时钟信号提供给该倍频器；
产生该第一输出时钟信号，其具有充分收敛到目标频率的第二频率，该目标频率大于该第一频率；
检测当该第二频率已经超过最小频率并且在该第二频率到达该目标频率之前的时间，该时间确定第一间隔的开始；
从该第一输出时钟信号产生第二输出时钟信号，该第二输出时钟信号具有第三频率，该第三频率小于该第二频率并且不超过该目标频率，该第三频率基本上收敛到该目标频率的一个因数；
确定该第一输出时钟信号何时与该输入时钟信号同步，该同步的确定结束该第一间隔；和
在该第一间隔期间，提供该第二输出时钟信号来操作至少一个时钟元件，并且在该第一间隔之后，将该第一输出时钟信号提供给该至少一个时钟元件。
2.如权利要求1的方法，其中产生该第二输出时钟信号的操作包括N分该第二频率的操作，其中N决定该目标频率的因数。
3.如权利要求2的方法，其中N分该第二频率的操作包括将该第二频率至少二分。
4.一种倍频器，包括：
比较器，用于接收具有第一频率的输入时钟信号和反馈信号，该比较器提供误差信号，该误差信号表示在该输入时钟信号与该反馈信号之间的第一特性的差异；
信号发生器，连接至该比较器，用来提供具有第二频率的输出时钟信号，该信号发生器基于该误差信号调整该输出时钟信号的第二特性，来降低在该输入时钟信号与该反馈信号之间的该第一特性的差异；
具有分频器的反馈环路，基于该输出时钟信号来将该反馈信号提供给比较器，该反馈环路与第一时间间隔相关联，用来减少该第一特性的差异，从而该输入时钟信号的第一特性与该反馈信号的第一特性基本相同；和
用于在该第一时间间隔期间基于该输出时钟信号来提供操作信号的装置，该装置包括至少一部分分频器，该分频器连接至该输出时钟信号，以将该第二频率降低到低于该输出时钟信号的目标频率。
5.如权利要求4的倍频器，其中用于提供操作信号的装置包括检测器，该检测器用来确定该第二频率何时已经超过大于该第一频率的阈值频率，从而在该第二频率已经超过该阈值频率之后且在该第二频率已经到达由该分频器确定的目标频率的因数之前，提供该操作信号。
6.如权利要求5的倍频器，其中依赖该第一频率与该目标频率之间的增长来确定该阈值频率。
7.如权利要求4的倍频器，其中该第一特性是相位。
8.如权利要求7的倍频器，其中该比较器确定该输入时钟信号与该反馈信号的至少一个上升沿和下降沿之间的差异。
9.如权利要求7的倍频器，其中该比较器确定该输入时钟信号与该反馈信号的过零点之间的差异。
10.如权利要求7的倍频器，其中该第二特性是频率。
11.如权利要求7的倍频器，其中该第二特性是该输出时钟信号的延迟。
12.如权利要求4的倍频器与至少一个处理器结合。
13.如权利要求12的结合，其中该输入时钟信号是该处理器系统时钟信号。
14.如权利要求12的结合，其中该输出时钟信号分配到该至少一个处理器的时钟元件。
15.如权利要求12的结合，其中该至少一个处理器包括多个子系统，多个子系统能够以多个频率操作。
16.如权利要求15的结合，其中倍频器将时钟信号提供给该至少一个处理器的多个子系统。
17.在适于提供与输入时钟信号以目标频率同步的输出时钟信号的倍频器中，一种用于在倍频器的锁定时间间隔期间提供操作时钟信号的方法，该方法包括操作：
减少反馈控制环路中该输入时钟信号与该输出时钟信号之间的相位差异，该反馈控制环路比较该输入时钟信号与该输出时钟信号之间的相位差异，并且调整该输出时钟信号来减少该相位差异，
在减少该输入时钟信号与该输出时钟信号之间的相位差异的操作期间：
将该输出时钟信号的频率N分频，来提供频率降低后的该输出时钟信号；和
将频率降低后的该输出时钟信号提供给至少一个时钟元件，该操作在确定频率降低后的该输出时钟信号具有超过规定阈值频率的频率之后，并且频率降低后的该输出时钟信号具有已经达到N频分的该目标频率之前开始。
18.如权利要求17的方法，其中调整该输出时钟信号的频率来减少该输入时钟信号与反馈信号之间的相位差异。
19.如权利要求17的方法，其中调整该输出时钟信号的延迟来减少该输入时钟信号与反馈信号之间的相位差异。
20.如权利要求17的方法，其中确定频率降低后的该输出时钟信号具有超过规定该阈值频率的频率的操作包括：检测频率降低后的该输出时钟信号的频率，并将该频率与规定的该阈值频率比较。
21.如权利要求17的方法，还包括从压控振荡器产生该输出时钟信号，压控振荡器调整该输出时钟信号的频率来减少相位差异。
22.如权利要求21的方法，其中确定频率降低后的该输出时钟信号具有超过规定该阈值频率的频率的操作包括：检测该压控振荡器何时第一次产生该输出时钟信号。
23.一种倍频器，适于在输出时钟信号已经与输入时钟信号同步之前提供操作时钟信号，该倍频器包括：
比较器，用于接收具有第一频率的该输入时钟信号和反馈信号，该比较器适于提供误差信号，该误差信号表示在该输入时钟信号与该反馈信号之间的第一特性的差异；
信号发生器，连接至该比较器，来提供第一输出时钟信号，该第一输出时钟信号具有基本收敛于目标频率的第二频率，该信号发生器基于该误差信号调整该第一输出时钟信号的第二特性，来降低在该第一输入时钟信号与该反馈信号之间的第一特性的差异；
分频器，连接至该信号发生器，具有至少第一部分，该第一部分配置为将该第二频率N分频，以提供具有第三频率的第二输出时钟信号；
检测器，适于监控该第一输出时钟信号和该第二输出时钟信号中的至少一个，该检测器配置为将该第二输出时钟信号提供给至少一个时钟元件，该操作在该检测器确定该第二频率已经超过大于该第一频率的规定的阈值频率之后且该第二频率已经达到该目标频率之前开始。
24.如权利要求23的倍频器，其中该分频器具有至少第二部分，该第二部分配置为降低该第二频率来产生提供给该比较器的该反馈时钟信号。
25.如权利要求24的倍频器，其中该分频器包括多个级，每个级具有第一分频器因数，并且该分频器的第一部分包括多个级中的至少一个。
26.如权利要求25的倍频器，其中该第一分频器因数等于2。
27.如权利要求23的倍频器，其中该检测器监控该第一输出时钟信号，来检测该信号发生器何时第一次产生该第一输出时钟信号，以确定该第三频率何时超过规定的该阈值频率。
28.如权利要求23的倍频器与至少一个处理器结合。
29.如权利要求28的结合，其中该输入时钟信号是该至少一个处理器系统时钟信号。
30.如权利要求28的结合，其中该第一和第二输出时钟信号分配到该至少一个处理器的时钟元件。
31.如权利要求28的结合，其中该至少一个处理器包括多个子系统，多个子系统能够以多个频率操作。
32.如权利要求31的结合，其中该倍频器将该输出时钟信号提供给该至少一个处理器的多个子系统。
33.如权利要求1的方法，其中该倍频器将该第一输出时钟信号提供给至少一个处理器，并且提供该第二输出时钟信号的操作包括在该第一间隔期间将该第二输出时钟信号提供给该至少一个处理器。
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