CN100452655C - Self correcting multipath A/D converter - Google Patents
Self correcting multipath A/D converter Download PDFInfo
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- CN100452655C CN100452655C CNB2005100947430A CN200510094743A CN100452655C CN 100452655 C CN100452655 C CN 100452655C CN B2005100947430 A CNB2005100947430 A CN B2005100947430A CN 200510094743 A CN200510094743 A CN 200510094743A CN 100452655 C CN100452655 C CN 100452655C
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Abstract
The present invention discloses a self correcting multi-path A/D converter which comprises a signal generation circuit, a first path A/D converter, a second path A/D converter, a third path A/D converter, a fourth path A/D converter and a data selector, wherein the output ends of the four four-path A/D converters are connected with a multi-path selector and are respectively connected with four data input ends of the multi-path selector; the four paths of the output ends of the multi-path selector are connected with a correcting circuit and are respectively connected with the input end of the correcting circuit; the four paths of the output ends of the correcting circuit are respectively connected with the four paths of the input end of the data selector. The present invention has the advantage that the signal-noise ratio is adjusted by a calculated maladjustment error, a gain error and the correcting circuit, etc. The maladjustment error and the gain error of a multi-path A/D converter are reduced to a great extend, and the signal-noise ratio is greatly enhanced by the correcting proposal.
Description
Technical field
The present invention relates to a kind of various multipath A/D converter circuit that can be applied to carry out offset error and gain error calibration, relate in particular to a kind of self correcting multipath A/D converter that can use at chip circuit.
Background technology
Many channel modulus converter concurrent workings become the common scheme of current high-speed AD converter design.But under existing process conditions, between passage, produce offset error and gain error owing to there are various inevitable fabrication errors.These errors affect the signal to noise ratio of analog to digital converter to a great extent.For reducing the deterioration of performance, must calibrate interchannel offset error and gain error.
Summary of the invention
The invention provides a kind of self correcting multipath A/D converter that can reduce each interchannel offset error and gain error in the multipath A/D converter.
The present invention adopts following technical scheme:
A kind of self correcting multipath A/D converter, comprise signal generating circuit, the first passage analog to digital converter, the second channel analog to digital converter, the third channel analog to digital converter, four-way analog to digital converter and data selector, the clock termination low-speed clock Clk_t of signal generating circuit, the control input end connects signal Eff_ena, two outputs respectively with first passage, second channel, third channel, the positive input of four-way and reverse input end connect, on the output of four No. four analog to digital converters, be connected with MUX and be connected with four data inputs of MUX respectively, the control end connection control signal Eff_ena of MUX, on other four road outputs of MUX, be connected with the calibration computing circuit and be connected with four road inputs of calibrating computing circuit respectively, the clock termination low-speed clock Clk_t of calibration computing circuit, its six outputs are connected with other six inputs of calibration circuit respectively, on four road outputs of MUX, be connected with calibration circuit and be connected with the input of calibration circuit respectively, four road outputs of calibration circuit are connected with four road inputs of data selector respectively, the control end connection control signal Cal_ena of data selector, input end of clock connects clock Clk, output output final data data.
Compared with prior art, the present invention has following advantage:
The present invention at first produces some signals by signal generating circuit, respectively same signal is sampled and conversion of signals by the analog to digital converter of each bar passage.Calculate each bar passage by the digital quantity of changing out by least square method and approach with respect to the offset error of article one passage and the best square of gain error, and by these error parameters of register-stored.When carrying out data transaction, according to the error parameter that records the digital quantity of conversion is lacked of proper care and gain calibration, again by the synthetic output of data selector by calibration circuit.By calibration program of the present invention, the offset error and the gain error of multipath A/D converter are reduced significantly, and signal to noise ratio is greatly improved.
Description of drawings
Fig. 1 is circuit theory diagrams of the present invention.
Fig. 2 is that this calibrating signal produces circuit diagram.
Fig. 3 is the output waveform figure of signal generating circuit.
Fig. 4 is a calibration computing circuit block diagram of the present invention.
Fig. 5 is the first calibration computing circuit circuit diagram of the present invention.
Fig. 6 is an error parameter pre-computation circuit diagram of the present invention.
Fig. 7 is offset error parameter generation circuit figure of the present invention.
Fig. 8 is gain error parameter generation circuit figure of the present invention.
Fig. 9 is a calibration circuit circuit diagram of the present invention.
Embodiment
A kind of self correcting multipath A/D converter, comprise signal generating circuit 5, first passage analog to digital converter 1, second channel analog to digital converter 2, third channel analog to digital converter 3, four-way analog to digital converter 4 and data selector 8, the clock termination low-speed clock Clk_t of signal generating circuit 5, the control input end connects signal Eff_ena, two outputs respectively with first passage 1, second channel 2, third channel 3, the positive input of four-way 4 and reverse input end connect, at four No. four analog to digital converters 1,2,3, be connected with MUX 6 on 4 the output and be connected with four data inputs of MUX 6 respectively, the control end connection control signal Eff_ena of MUX 6, on other four road outputs of MUX 6, be connected with calibration computing circuit 9 and be connected with four road inputs of calibrating computing circuit 9 respectively, the clock termination low-speed clock Clk_t of calibration computing circuit 9, its six outputs are connected with other six inputs of calibration circuit 7 respectively, on four road outputs of MUX 6, be connected with calibration circuit 7 and be connected with the input of calibration circuit 7 respectively, four road outputs of calibration circuit 7 are connected with four road inputs of data selector 8 respectively, the control end connection control signal Cal_ena of data selector, input end of clock connects clock Clk, output output final data data
Calibration computing circuit 9 is by the first calibration computing circuit 11, the second calibration computing circuit 12 and the 3rd calibration computing circuit 13 are formed, the first calibration computing circuit 11, second the calibration computing circuit 12 and the 3rd the calibration computing circuit 13 an input be connected and as the calibration computing circuit 9 an input, the first calibration computing circuit 11, another input of the second calibration computing circuit 12 and the 3rd calibration computing circuit 13 is respectively as other three inputs of calibrating computing circuit 9, the first calibration computing circuit 11, two outputs of the second calibration computing circuit 12 and the 3rd calibration computing circuit 13 are respectively as six outputs calibrating computing circuit 9
The first calibration computing circuit 11, the second calibration computing circuit 12 or the 3rd calibration computing circuit 13 are by error parameter pre-computation circuit 14, offset error parameter generation circuit 15 and gain error parameter generation circuit 16 are formed, four output S1 of error parameter pre-computation circuit 14, S2, T0, T1 is connected with four inputs of offset error parameter generation circuit 15 and four inputs of gain error parameter generation circuit 16 respectively, two inputs of above-mentioned error parameter pre-computation circuit 14 are respectively as the first calibration computing circuit 11, two inputs of the second calibration computing circuit 12 or the 3rd calibration computing circuit 13, offset error parameter generation circuit 15 and gain error parameter output are respectively as the first calibration computing circuit 11, two outputs of the second calibration computing circuit 12 or the 3rd calibration computing circuit 13
Error parameter pre-computation circuit 14 is by accumulator 17,19,20,22, squaring circuit 18 and multiplier 21 are formed, the input of accumulator 17, an input of the input of squaring circuit 18 and multiplier 21 is connected and as an input of error parameter pre-computation circuit 14, the output of squaring circuit 18 is connected with the input of accumulator 19, multiplier 21 outputs are connected with the input of accumulator 22, the input of accumulator 20 is connected with another input of multiplier 21 and as another input of error parameter pre-computation circuit 14, accumulator 17,19,20,22 outputs are respectively as four output S1 of error parameter pre-computation circuit 14, S2, T0, T1; Offset error parameter generation circuit 15 is by subtracter 25,28, multiplier 23,24,26,30, squaring circuit 27, reciprocal circuit 29, register 47 is formed, an input of multiplier 24 is connected with the input of squaring circuit 27 and as the first input end of offset error parameter generation circuit 15, another input of multiplier 24 is as the four-input terminal of offset error parameter generation circuit 15, multiplier 24 and squaring circuit 27 outputs respectively with subtracter 25,28 subtrahend end connects, the output of subtracter 28 is connected with the input of reciprocal circuit 29, the output of reciprocal circuit 29 is connected with another input of multiplier 30, an input of multiplier 23 is connected with an input of another multiplier 26 and as second input of offset error parameter generation circuit 15, another input of multiplier 23 is as the 3rd input of offset error parameter generation circuit 15, multiplier 23 and another multiplier 26 outputs respectively with subtracter 25,28 minuend end connects, an input of the output of subtracter 25 and multiplier 30 is connected, the output of multiplier 30 connects the input of register 47, the output of register 47 is as the output of offset error parameter generation circuit 15, and another input of above-mentioned multiplier 26 produces the signal input part of number N as data; Gain error parameter generation circuit 16 is by subtracter 33,36, multiplier 31,32,34,38, squaring circuit 35, reciprocal circuit 37, register 48 is formed, an input of multiplier 32 is connected with the input of squaring circuit 35 and as an input of gain error parameter generation circuit 16, an input of multiplier 34, another input of multiplier 32 and another input of multiplier 31 are respectively as other three inputs of gain error parameter generation circuit 16, the input data of another input of above-mentioned multiplier 34 are the number of the voltage output signal of signal generating circuit 5 generations, the output of multiplier 31 and multiplier 32 is connected with the subtrahend end with the minuend end of subtracter 33 respectively, the output of subtracter 33 is connected with an input of multiplier 38, the output of multiplier 34 and squaring circuit 35 is connected with the subtrahend end with the minuend end of subtracter 36 respectively, the output of subtracter 36 is connected with input with reciprocal circuit 37, another input of the output of reciprocal circuit 37 and multiplier 38 is connected, the output of multiplier 38 connects the input of register 48, the output of register 48 is as the output of gain error parameter generation circuit 16, the input data of an input of multiplier 31 are the number of the voltage output signal of signal generating circuit 5 generations
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is made more detailed explanation:
Fig. 1 is the circuit diagram of multipath A/D converter.Comprise signal generating circuit 5, first passage analog to digital converter 1, second channel analog to digital converter 2, third channel analog to digital converter 3, four-way analog to digital converter 4, MUX 6, calibration computing circuit 9, calibration circuit 7 and data selector 8.The clock termination low-speed clock Clk_t of signal generating circuit 5, the control input end connects signal Eff_ena, two outputs are connected with two inputs of first passage 1, second channel 2, third channel 3, four-way 4 respectively, and wherein an end is a positive input, and the other end is a reverse input end.The output of No. four analog to digital converters 1～4 is connected with four data inputs of MUX 6 respectively.The control end connection control signal Eff_ena of MUX 6, four road outputs connect the input of calibration circuit 7, and four road outputs connect four road inputs of calibration computing circuit 9 in addition.The clock termination low-speed clock Clk_t of calibration computing circuit 9, other six inputs of six outputs and calibration circuit 7 are connected.Four road outputs of calibration circuit 7 are connected with four road inputs of data selector 8.The control end connection control signal Cal_ena of data selector, input end of clock connects clock Clk, output output final data data.
This circuit adopts calibration mode and two kinds of mode of operations of data transfer module, respectively by Eff_ena signal and Cal_ena signal controlling, is calibration mode when Eff_ena is effective, is data transfer module when the Cal_ena signal is effective.Clock is divided into two groups: Clk_t and Clk, be respectively applied for calibration mode and translative mode, and wherein Clk_t is clock signal at a slow speed, Clk is a high-speed clock signal.Signal adopts the difference input mode.
At first allow circuit working at calibration mode.Produce signal V1 and reverse signal VCM by signal generating circuit 5, four-way analog to digital converter 1～4 is sampled successively by the clock order and is changed V1 signal, output digital quantity D0＜1 〉, D1＜1, D2＜1, D3＜1.Because signal Eff_ena is effective, MUX 6 makes this four road signal enter calibration computing circuit 9.Then signal generating circuit 5 produces signal V2, and No. four analog to digital converters 1～4 produce digital quantity D0＜2 〉, D1＜2, D2＜2, D3＜2, and finally enter computing calibration circuit 9.Conversion successively by this way, last the signal Vn conversion that produces up to signal generating circuit finishes.Go out offset error parameter c 1, c2, c3 and gain error parameter d 1, d2, the d3 of passage 2～4 by the calibration computing circuit according to these data computation with respect to passage 1.
Error parameter is arranged on transformation working pattern with circuit after calculating and finishing.Input signal VIN and VINR.Produce D0～D3 chronologically by four paths, this moment, control signal Eff_ena was invalid, and MUX 6 makes D0～D3 enter calibration circuit 7, was output as data the D0 '～D3 ' after the calibration, by data selector 8 with the synthetic back output of four circuit-switched data.
Data generating circuit among Fig. 2 is made up of resistance pressure-dividing network and frequency divider 10.The two ends of resistor network meet maximum, minimum levels vrefh and the vrefl of input signal respectively.The voltage node of resistor network is V1～Vn.N is recommended as 20 herein, and 20 voltage node are promptly arranged, and produces 20 data.The source end of metal-oxide-semiconductor M1～Mn connects these voltage node respectively, and drain terminal all is connected on the output port VIN.The control termination signal Eff_ena of frequency divider 10, input end of clock input Clk_t, output links to each other with the grid of metal-oxide-semiconductor M1～Mn successively, output switch control signal r1～rn.The waveform of r1～rn is seen shown in Figure 3.The reverse incoming level VCM of the source termination of metal-oxide-semiconductor Mn+1, drain terminal meets output VINR, and grid meet signal Eff_ena.Calibration mode eff_ena of following time signal is effective when being in, output reverse signal VCM, and the Clk_t clock is effective, output node voltage V1～Vn.
Fig. 3 is the output waveform of frequency divider 5.When Eff_ena was high level, output signal r1～rn is output high level when clock Clk_t high level successively.Output signal r1～rn is a low level when Eff_ena is low level.
The calibration computing circuit is made up of three paths 11～13 among Fig. 4.The input termination D0＜k of the first calibration computing circuit 11 〉, D1＜k signal, output termination c1, d1 signal; The input termination D0＜k of the 2nd calibration computing circuit 12 〉, D2＜k signal, output termination c2, d2 signal; The input termination D0＜k of the 3rd calibration computing circuit 13 〉, D3＜k signal, output termination c3, d3 signal.Wherein passage 111 as shown in Figure 5.The circuit of two other passage is identical with article one.
Fig. 5 is the circuit diagram of the first calibration computing circuit, is made up of error parameter pre-computation circuit 14, offset error parameter generation circuit 15 and gain error parameter generation circuit 16.Two inputs of error parameter pre-computation circuit 14 meet signal D0＜k respectively〉and D1＜k, four outputs are connected with four inputs of offset error parameter generation circuit 15, four inputs of gain error parameter generation circuit 16 respectively.Four output signals of error parameter pre-computation circuit 14 are respectively S1, S2, T0, T1.The output of offset error parameter generation circuit 15 is an offset error parameter c 1.The output of gain error parameter generation circuit 16 is a gain error parameter d 1.
Fig. 6 is the error parameter pre-computation circuit in the first calibration computing circuit, and by accumulator 17,19,20,22, squaring circuit 18 and multiplier 21 are formed.The input of accumulator 17 connects signal D0＜k 〉, output connects signal S1.The input of squaring circuit 18 connects signal D0＜k 〉, output is connected with the input of accumulator 19.The output output signal S2 of accumulator.The input of accumulator 20 connects signal D1＜k 〉, output connects signal T0.Two inputs of multiplier 21 connect signal D0＜k respectively〉and D1＜k, output is connected with the input of accumulator 22.The output output signal T1 of accumulator 22.
Fig. 7 is the offset error parameter generation circuit in the first calibration computing circuit, by subtracter 25,28, and multiplier 23,24,26,30, squaring circuit 27, reciprocal circuit 29 is formed.An input of multiplier 23 connects signal S2, and another input connects signal T0, and output connects the minuend end of subtracter 25.An input of multiplier 24 connects signal S1, and another input connects signal T1, and output connects the subtrahend end of subtracter 25.An input of the output of subtracter 25 and multiplier 30 is connected.
An input of multiplier 26 connects signal S2, and another input connects data producer and produces data number N, and the minuend end of output and subtracter 28 is connected.The input of squaring circuit 27 connects signal S1, and the subtrahend end of output and subtracter 28 is connected.Be connected with reciprocal circuit 29 on the output of subtracter 28, and be connected with the input of reciprocal circuit 29.Another input of the output of reciprocal circuit 29 and multiplier 30 is connected.The output output signal c1 of multiplier 30.
Fig. 8 is a gain error parameter generation circuit in the first calibration computing circuit, by subtracter 33,36, and multiplier 31,32,34,38, squaring circuit 35, reciprocal circuit 37 is formed.An input of multiplier 31 connects signal S0, and another input connects signal T1, and output connects the minuend end of subtracter 33.An input of multiplier 32 connects signal S1, and another input connects signal T0, and output connects the subtrahend end of subtracter 33.An input of the output of subtracter 33 and multiplier 38 is connected.
An input of multiplier 34 connects signal S2, and another input connects data producer and produces data number N, and the minuend end of output and subtracter 36 is connected.The input of squaring circuit 35 connects signal S1, and the subtrahend end of output and subtracter 36 is connected.Be connected with reciprocal circuit 37 on the output of subtracter 36, and be connected with the input of reciprocal circuit 37.Another input of the output of reciprocal circuit 37 and multiplier 38 is connected.The output output signal d1 of multiplier 38.
Offset error parameter of the present invention and gain error parameter are approached by the best square that least square method calculates error parameter, and computing formula is
Wherein
Calibration circuit among Fig. 9 is made up of subtracter 39,41,43,45 and divider 40,42,44,46.The minuend termination data D0 of subtracter 39, subtrahend termination data 0, output is connected with the dividend end of divider 40.The divisor termination data 1 of divider 40, dateout D0 '.The minuend termination data D1 of subtracter 41, subtrahend termination calibration parameter c1, output connects the dividend end of divider 42.The divisor termination calibration parameter d1 of divider 42, dateout D1 '.The minuend end of subtracter 43 connects data D2, and the subtrahend end connects calibration parameter c2, and output connects the dividend end of divider 44.The divisor end of divider 44 connects calibration parameter d2, output signal D2 '.The minuend end of subtracter 45 connects data D3, and the subtrahend end connects calibration parameter c3, the dividend end of output termination divider 46.The divisor end of divider 46 connects calibration parameter d3, output signal D3 '.
Claims (3)
1, a kind of self correcting multipath A/D converter, comprise signal generating circuit (5), first passage analog to digital converter (1), second channel analog to digital converter (2), third channel analog to digital converter (3), four-way analog to digital converter (4) and data selector (8), the clock termination low-speed clock Clk_t of signal generating circuit (5), the control input end connects signal Eft_ena, two outputs of signal generating circuit (5) respectively with first passage analog to digital converter (1), second channel analog to digital converter (2), third channel analog to digital converter (3), the positive input of four-way analog to digital converter (4) is connected with reverse input end, it is characterized in that first passage analog to digital converter (1), second channel analog to digital converter (2), third channel analog to digital converter (3), the output of four-way analog to digital converter (4) is connected with four data inputs of MUX (6) respectively, the control end connection control signal Eft_ena of MUX (6), four outputs of MUX (6) are connected with four inputs of calibration computing circuit (9) respectively, other four road outputs of MUX (6) are connected with four inputs of calibration circuit (7) respectively, the clock termination low-speed clock Clk_t of calibration computing circuit (9), six outputs of calibration computing circuit (9) are connected with other six inputs of calibration circuit (7) respectively, four road outputs of calibration circuit (7) are connected with four road inputs of data selector (8) respectively, the control end connection control signal Cal_ena of data selector (8), the input end of clock of data selector (8) connects clock Clk, the output output final data data of data selector (8); Calibration computing circuit (9) is by the first calibration computing circuit (11), the second calibration computing circuit (12) and the 3rd calibration computing circuit (13) are formed, an input of the first calibration computing circuit (11), an input of input of the second calibration computing circuit (12) and the 3rd calibration computing circuit (13) is connected and as an input of calibration computing circuit (9), first another input of calibration computing circuit (11), as other three inputs of calibration computing circuit (9), first calibrates two outputs of computing circuit (11) to another input of second calibration another input of computing circuit (12) and the 3rd calibration computing circuit (13) respectively, two outputs of two outputs of the second calibration computing circuit (12) and the 3rd calibration computing circuit (13) are respectively as six outputs of calibration computing circuit (9); The first calibration computing circuit (11), the second calibration computing circuit (12) or the 3rd calibration computing circuit (13) are by error parameter pre-computation circuit (14), offset error parameter generation circuit (15) and gain error parameter generation circuit (16) are formed, four output (S1 of error parameter pre-computation circuit (14), S2, TO, T1) be connected with four inputs of offset error parameter generation circuit (15) and four inputs of gain error parameter generation circuit (16) respectively, two inputs of above-mentioned error parameter pre-computation circuit (14) are respectively as the first calibration computing circuit (11), two inputs of the second calibration computing circuit (12) or the 3rd calibration computing circuit (13), the output of offset error parameter generation circuit (15) and gain error parameter generation circuit (16) are respectively as the first calibration computing circuit (11), two outputs of the second calibration computing circuit (12) or the 3rd calibration computing circuit (13).
2, self correcting multipath A/D converter according to claim 1, it is characterized in that error parameter pre-computation circuit (14) is by first accumulator (17), second accumulator (19), the 3rd accumulator (20), the 4th accumulator (22), first squaring circuit (18) and first multiplier (21) are formed, the input of first accumulator (17), the input of first squaring circuit (18) and be connected with an input of first multiplier (21) and as an input of error parameter pre-computation circuit (14), the output of first squaring circuit (18) is connected with the input of second accumulator (19), first multiplier (21) output is connected with the input of the 4th accumulator (22), the input of the 3rd accumulator (20) is connected with another input of first multiplier (21) and as another input of error parameter pre-computation circuit (14), the output of first accumulator (17), the output of second accumulator (19), the output of the output of the 3rd accumulator (20) and the 4th accumulator (22) is respectively as four output (S1 of error parameter pre-computation circuit (14), S2, T0, T1): offset error parameter generation circuit (15) is by first subtracter (25), second subtracter (28), second multiplier (23), the 3rd multiplier (24), the 4th multiplier (26), the 5th multiplier (30), second squaring circuit (27), first reciprocal circuit (29), first register (47) is formed, an input of the 3rd multiplier (24) is connected with the input of second squaring circuit (27) and as the first input end of offset error parameter generation circuit (15), another input of the 3rd multiplier (24) is as the four-input terminal of offset error parameter generation circuit (15), the 3rd multiplier (24) output is connected with the subtrahend end of first subtracter (25), second squaring circuit (27) output is connected with the subtrahend end of second subtracter (28), the output of second subtracter (28) is connected with the input of first reciprocal circuit (29), the output of first reciprocal circuit (29) is connected with another input of the 5th multiplier (30), an input of second multiplier (23) is connected with an input of the 4th multiplier (26) and as second input of offset error parameter generation circuit (15), another input of multiplier (23) is as the 3rd input of offset error parameter generation circuit (15), second multiplier (23) output is connected with subtracter (25) minuend end, the 4th multiplier (26) output is connected with the minuend end of second subtracter (28), an input of the output of first subtracter (25) and the 5th multiplier (30) is connected, the output of the 5th multiplier (30) connects the input of first register (47), the output of first register (47) is as the output of offset error parameter generation circuit (15), and another input of the 4th multiplier (26) produces the signal input part of number N as data; Gain error parameter generation circuit (16) is by the 3rd subtracter (33), the 4th subtracter (36), the 5th multiplier (31), the 6th multiplier (32), the 7th multiplier (34), the 8th multiplier (38), the 3rd squaring circuit (35), second reciprocal circuit (37), second register (48) is formed, an input of the 6th multiplier (32) is connected with the input of the 3rd squaring circuit (35) and as an input of gain error parameter generation circuit (16), an input of the 7th multiplier (34), another input of another input of the 6th multiplier (32) and the 5th multiplier (31) is respectively as other three inputs of gain error parameter generation circuit (16), the input data of another input of the 7th multiplier (34) are the number of the voltage output signal of signal generating circuit (5) generation, the output of the 5th multiplier (31) and the 6th multiplier (32) is connected with the subtrahend end with the minuend end of the 3rd subtracter (33) respectively, the output of the 3rd subtracter (33) is connected with an input of the 8th multiplier (38), the output of the 7th multiplier (34) and the 3rd squaring circuit (35) is connected with the subtrahend end with the minuend end of the 4th subtracter (36) respectively, the output of the 4th subtracter (36) is connected with the input of second reciprocal circuit (37), the output of second reciprocal circuit (37) is connected with another input of the 8th multiplier (38), the output of the 8th multiplier (38) connects the input of second register (48), the output of second register (48) is as the output of gain error parameter generation circuit (16), and the input data of an input of the 5th multiplier (31) are the number of the voltage output signal of signal generating circuit (5) generation.
3, self correcting multipath A/D converter according to claim 1, it is characterized in that calibration circuit (7) is by the 5th subtracter (39), the 6th subtracter (41), the 7th subtracter (43), the 8th subtracter (45), first divider (40), second divider (42), the 3rd divider (44) and the 4th divider (46) are formed, the minuend end of the 5th subtracter (39), the minuend end of the 6th subtracter (41), the minuend of the minuend of the 7th subtracter (43) end and the 8th subtracter (45) is held respectively four inputs as described calibration circuit (7), the subtrahend termination data 0 of the 5th subtracter (39), the output of the 5th subtracter (39) is connected with the dividend end of first divider (40), the divisor termination data 1 of first divider (40), the output of the 6th subtracter (41), the output of the output of the 7th subtracter (43) and the 8th subtracter (45) respectively with the dividend end of second divider (42), the dividend end of the 3rd divider (44) is connected with the 4th divider (46) dividend end, the subtrahend end of the 6th subtracter (41), the divisor end of the subtrahend end of the subtrahend end of the 7th subtracter (43) and the 8th subtracter (45) and second divider (42), the divisor end of the 3rd divider (44), the divisor end of the 4th divider (46) is respectively as described other six inputs of described calibration circuit (7), above-mentioned second divider (42), the output of the 3rd divider (44) and the 4th divider (46) is respectively as four outputs of calibration circuit (7).
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| CN106647226A (en) * | 2016-12-09 | 2017-05-10 | 深圳市锐能微科技股份有限公司 | Time digital converter, error correcting device and error correcting method |
| CN108897264B (en) * | 2018-09-27 | 2020-06-16 | 浙江大学 | Analog-digital converter control device for general system chip |
| CN109462401B (en) * | 2018-11-21 | 2022-07-05 | 上海航天计算机技术研究所 | Multichannel AD collection equipment that mutual noninterference between multimachine |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6563446B1 (en) * | 2000-06-06 | 2003-05-13 | Marvell International, Ltd. | Method and apparatus for direct RAM analog-to-digital converter calibration |
| CN2605703Y (en) * | 2003-04-10 | 2004-03-03 | 上海复旦微电子股份有限公司 | Analogue-digital conversion circuit |
| US6882371B2 (en) * | 2001-04-12 | 2005-04-19 | Mitsubishi Denki Kabushiki Kaisha | Method and apparatus for selective video signal sampling |
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2005
- 2005-10-10 CN CNB2005100947430A patent/CN100452655C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6563446B1 (en) * | 2000-06-06 | 2003-05-13 | Marvell International, Ltd. | Method and apparatus for direct RAM analog-to-digital converter calibration |
| US6882371B2 (en) * | 2001-04-12 | 2005-04-19 | Mitsubishi Denki Kabushiki Kaisha | Method and apparatus for selective video signal sampling |
| CN2605703Y (en) * | 2003-04-10 | 2004-03-03 | 上海复旦微电子股份有限公司 | Analogue-digital conversion circuit |
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