CN100452800C

CN100452800C - FPGA based rapid Ethernet port bandwidth control system

Info

Publication number: CN100452800C
Application number: CNB2005100188897A
Authority: CN
Inventors: 杨旭; 周箴
Original assignee: Fiberhome Telecommunication Technologies Co Ltd
Current assignee: Wuhan Fiberhome Technical Services Co Ltd
Priority date: 2005-06-09
Filing date: 2005-06-09
Publication date: 2009-01-14
Anticipated expiration: 2025-06-09
Also published as: CN1703049A

Abstract

The present invention discloses a bandwidth control system of a rapid ethernet port, which is based on parts of a field programmable gate array. The present invention relates to a bandwidth control system of a rapid ethernet port. The present invention is composed of parts 1 of a field programmable gate array, a first MII bus 2, a second MII bus 3, an address and data bus 4, a data link layer chip 5, a physical layer chip 6 and a CPU 7, wherein the parts 1 of a field programmable gate array are respectively connected with the data link layer chip 5 through the second MII bus 3, are connected with the physical layer chip 6 through the first MII bus 2, and are connected with the CPU 7 through the address and data bus 4; the parts 1 of a field programmable gate array comprise an uplink flow control module 1.1, a downlink flow control module 1.3 and an administrative interface module 1.2. Because the present invention uses a hardware mode, bandwidth control is effective, reliable and simple, and is easy to achieve; a network bandwidth can be planned flexibly via the bandwidth control, and the efficiency of a network is improved; because the cost performance ratio is high, the present invention has a wide application prospect.

Description

Fast ethernet port bandwidth control system based on Field Programmable Gate Array

Technical field

The present invention relates to a kind of fast ethernet port bandwidth control system, specifically, being to pass through hardware mode---Field Programmable Gate Array (FPGA) is controlled the media-independent bus (MII) of the IEEE802.3 standard between fast ethernet data link layer chip and the physical chip, realization is to the flexible control of fast ethernet port bandwidth, thereby realize the reasonable distribution of ethernet device networking Time Bandwidth easily, improve the efficient and the stability of the network operation.

Background technology

Ethernet technology is current most widely used a kind of local area network technology, has also obtained increasing application at Access Network.But the port of the IEEE802.3 Fast Ethernet of standard can only provide two kinds of interface rates of 10M, 100M optional, and the speed of each port cannot be set as required flexibly.Simultaneously, the actual bandwidth of the network interface in the real network is unpredictable, thereby is easy to produce bottleneck effect in network uses, and causes network blockage, has reduced the efficient and the stability of the network operation.In addition, the ethernet port Bandwidth Control can also satisfy the management of network operation and the requirement of charging.

The solution of Ethernet bandwidth control at present all is to be realized by the bandwidth controlled function that Ethernet switching chip (ASIC) provides.The realization bandwidth controlled function of various exchange chips all is not quite similar, the bandwidth controlled function lacks flexibility, several bandwidth mode designs only are provided, and in some special Ethernets are used, also can not realize Ethernet bandwidth controlled function by existing Ethernet switching chip (ASIC).

Summary of the invention

The objective of the invention is to overcome the shortcoming and defect of above-mentioned Ethernet bandwidth control system, propose a kind of fast ethernet port bandwidth control system based on Field Programmable Gate Array.

The object of the present invention is achieved like this:

Use hardware plan---Field Programmable Gate Array (FPGA) 1, make Ethernet bandwidth control efficiency and precision all very high.This hardware is a cover external circuit that is increased in the media-independent bus (MII) of 6 of fast ethernet data link layer chip 5 and physical chips, can be increased to flexibly in the various Ethernet access devices.Along with the price reduction of large-scale fpga chip, cost of the present invention is also lower.Control flexibly by practical communication bandwidth Ethernet interface, thereby when networking can by the network management means make rational planning for and distribution network in the bandwidth of each interface, eliminate network bottleneck, avoid the networking to stop up, thereby improve network operating efficiency and stability, make things convenient for the Fast Ethernet access technology in nonbusiness's net environmental applications.

Adopt Field Programmable Gate Array (FPGA) 1, meet the MII of the Ethernet interface of IEEE 802.3 standards between the data link layer chip 5 of transformation Ethernet and the MII of physical chip 6.The major function of physical chip 6 is finished actual signal transmission for the network physical interface is provided.And the function of data link layer chip 5 is to set up data link to connect on two main frames, and to physical chip 6 transmission of data signals.So by control MII bus, also with regard to the actual transmitting-receiving bandwidth of control data link layer chip 5, and the output flow of the network port depends on the data traffic that physical chip 6 is received from data link layer chip 5, the input flow rate of the network port depends on the data traffic that data link layer chip 5 is received from physical chip 6, finally finishes the control to the high bandwidth of network port input and output.

As shown in Figure 1, the present invention is made up of Field Programmable Gate Array (FPGA) 1, a MII bus 2, the 2nd MII bus 3, address and data/address bus 4, data link layer chip 5, physical chip 6, CPU7; Field Programmable Gate Array (FPGA) 1 is connected with data link layer chip 5 by the 2nd MII bus 3 respectively, is connected with physical chip 6 by a MII bus 2, is connected with CPU7 with data/address bus 4 by the address.

Described Field Programmable Gate Array (FPGA) 1 has three modules: uplink traffic control module 1.1, downlink traffic control module 1.3 and management interface module 1.2.

As shown in Figure 2, uplink traffic control module 1.1 is made up of a MII interface module 8, the first doubleclocking pushup storage 9, the second doubleclocking pushup storage 10, the 2nd MII interface module 11, frequency dividing circuit 12; The one MII interface module 8, the first doubleclocking pushup storage 9, the second doubleclocking pushup storage 10, the 2nd MII interface module 11 connect successively; The first doubleclocking pushup storage 9, the second doubleclocking pushup storage 10 are connected with frequency dividing circuit 12 respectively.

The data of uplink traffic control module 1.1 flow to a MII interface module 8, the first doubleclocking pushup storage 9, the second doubleclocking pushup storage 10, the 2nd MII interface module 11 successively;

The principle of downlink traffic control module 1.3 and uplink traffic control module 1.1 are identical, and just data flow is opposite, no longer superfluous chatting.

Management interface module 1.2 provides interface to be connected with data/address bus 4 with the address, and CPU7 can communicate by letter with management interface module 1.2 with data/address bus 4 by the address.

Operation principle of the present invention is:

In three modules of FPGA1, uplink and downlink flow-control module the 1.1, the 1.3rd directly is connected with first,

second MII bus

2,3, since first, second MII bus the 2, the 3rd, full duplex work, adopt uplink and downlink flow-control module 1.1,1.3, control respectively first,

second MII bus

2,3 from physical chip 6 to data link layer chip 5 with from data link layer chip 5 to physical chip 6 flow; The principle of these two modules is identical, all is the two-stage transmission in FPGA1 inside, promptly strides two data in time domain in the inside of FPGA1 and handles; Management interface module 1.2 is connected with data/address bus 4 with the address of CPU7, CPU7 by data and address bus 4 can Access Management Access interface module 1.2 inside control register, uplink and downlink flow-control module 1.1,1.3 is correspondingly adjusted interface bandwidth according to the content of control register, the management interface of CPU7 just can be finished network port bandwidth control configuration.Three module co-ordinations can realize detecting in real time the flow bandwidth by this port, and forbid surpassing the data traffic of setting bandwidth and pass through, and just the communication bandwidth with the network port is controlled within the scope of setting.

Uplink traffic control module 1.1: interface circuit is provided, the Power Generation Road of the receipts circuit of the MII interface of connection data link layer chip 5 and the MII interface of physical chip 6, the bandwidth of these two interface circuits all is 100M, but the bandwidth between two interface circuits is subjected to the control of internal bandwidth control register, the flow that receives from the MII interface Power Generation Road of physical chip 6 is higher than the bag of bandwidth setting all to be lost, thereby realizes the control of upstream data bandwidth;

Downlink traffic control module 1.3: interface circuit is provided, the receipts circuit of the Power Generation Road of the MII interface of connection data link layer chip 5 and the MII interface of physical chip 6, the bandwidth of these two interface circuits all is 100M, but the bandwidth between two interface circuits is subjected to the control of internal bandwidth control register, the flow that receives from the MII interface Power Generation Road of data link layer chip 5 is higher than the bag of bandwidth setting all to be lost, thereby realizes the control of downlink data bandwidth.

Management interface module 1.2: can constitute by the general pin of FPGA1 with the address bus of 8Bit and the data/address bus of 8Bit, and chip selection signal.Data and address bus 4 with CPU7 joins again, the address bus maximum of 8Bit can with 256 registers of addressing FPGA1 inside, CPU7 is by address bus and the chip selection signal of 8Bit, just can be to these 256 registers addressing read-write respectively of FPGA1 inside, these 256 registers can partly be used as control register, part is used for status register, and part can be used as reservation register.We are the bandwidth control register with one of them register definitions, and by the readwrite bandwidth control register, control frequency dividing circuit 12 just can be provided with the bandwidth that fast ethernet data flows uplink and downlink flow-control module 1.1,1.3 respectively.In the specific implementation of management interface module 1.2, CPU7 can adopt the MPC860 series of Motorola.The design of cpu system is not discussed scope in the present invention.

The present invention has following advantage and good effect:

1. use hardware mode, bandwidth control is effectively reliable, is simple and easy to realize;

2. control planning network bandwidth neatly by bandwidth, improve networks efficiency.

Because therefore ratio of performance to price height has wide application prospect.

Description of drawings

Fig. 1-native system composition frame chart;

Fig. 2-uplink and downlink flow-control module composition frame chart;

Fig. 3-the one MII interface module 8, the 2nd MII interface module 11 composition frame charts;

Wherein:

1-Field Programmable Gate Array (FPGA),

1.1-the uplink traffic control module, 1.2-management interface module, 1.3-downlink traffic control module;

2-the one MII bus;

3-the 2nd MII bus;

4-address and data/address bus;

5-data link layer chip;

The 6-physical chip;

7-CPU；

8-the one MII interface module;

The 9-first doubleclocking pushup storage (dcfifol);

The 10-second doubleclocking pushup storage (dcfifo2);

11-the 2nd MII interface module;

The 12-frequency dividing circuit.

Embodiment

Further specify below in conjunction with embodiment:

Field Programmable Gate Array (FPGA) 1 can be selected the EP2S15 of altera corp etc. for use;

Data link layer chip 5 can be selected the GT48510A of MARVELL company etc. for use;

Physical chip 6 can be selected the LXT971 of Intel Company etc. for use;

CPU7 can select the PC850 of Freescale company or MPC850 etc. for use;

The one MII interface module 8, the 2nd MII interface module 11 can be selected the PE-MACMII-10/100Ethernet Media Access Controller of Mentor Graphics-Inventra company for use, as Fig. 3;

The first doubleclocking pushup storage 9, the second doubleclocking pushup storage 10 use the integrated M512RAM blocks of Field Programmable Gate Array 1 chip internal;

Frequency dividing circuit 12 uses the integrated Enhanced PLLs of Field Programmable Gate Array 1 chip internal.

Claims

1, a kind of fast ethernet port bandwidth control system based on Field Programmable Gate Array is characterized in that:

Form by Field Programmable Gate Array (1), a MII bus (2), the 2nd MII bus (3), address and data/address bus (4), data link layer chip (5), physical chip (6), CPU (7); Field Programmable Gate Array (1) is connected with data link layer chip (5) by the 2nd MII bus (3) respectively, is connected with physical chip (6) by a MII bus (2), is connected with CPU (7) with data/address bus (4) by the address;

Described Field Programmable Gate Array (1) has three modules: uplink traffic control module (1.1), downlink traffic control module (1.3) and management interface module (1.2);

Described uplink traffic control module (1.1), downlink traffic control module (1.3) are made up of a MII interface module (8), the first doubleclocking pushup storage (9), the second doubleclocking pushup storage (10), the 2nd MII interface module (11), frequency dividing circuit (12); The one MII interface module (8), the first doubleclocking pushup storage (9), the second doubleclocking pushup storage (10), the 2nd MII interface module (11) connect successively; The first doubleclocking pushup storage (9), the second doubleclocking pushup storage (10) are connected with frequency dividing circuit (12) respectively;

Described management interface module (1.2) provides the module that interface and address are connected with data/address bus (4);

CPU (7) is by the inner control register of data and address bus (4) Access Management Access interface module (1.2), uplink and downlink flow-control module (1.1,1.3) is correspondingly adjusted interface bandwidth according to the content of control register, and the bag that will be higher than the bandwidth setting is all lost, realize the data bandwidth control of uplink traffic and downlink traffic respectively, three module co-ordinations are controlled at the communication bandwidth of the network port within the scope of setting.

2, by the described a kind of fast ethernet port bandwidth control system of claim 1, it is characterized in that based on Field Programmable Gate Array:

Field Programmable Gate Array (1) is selected the EP2S15 of altera corp for use;

Data link layer chip (5) is selected the GT48510A of MARVELL company for use;

Physical chip (6) is selected the LXT971 of Intel Company for use;

CPU (7) selects the PC850 or the MPC850 of Freescale company for use;

The one MII interface module (8), the 2nd MII interface module (11) are selected the PE-MACMII-10/100Ethernet Media Access Controller of Mentor Graphics-Inventra company for use;

The first doubleclocking pushup storage (9), the second doubleclocking pushup storage (10) use the integrated M512 RAM blocks of Field Programmable Gate Array (1) chip internal;

Frequency dividing circuit (12) uses the integrated EnhancedPLLs of Field Programmable Gate Array (1) chip internal.