CN100461090C - Stack high-speed memory using code sharing - Google Patents
Stack high-speed memory using code sharing Download PDFInfo
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- CN100461090C CN100461090C CNB2004800425684A CN200480042568A CN100461090C CN 100461090 C CN100461090 C CN 100461090C CN B2004800425684 A CNB2004800425684 A CN B2004800425684A CN 200480042568 A CN200480042568 A CN 200480042568A CN 100461090 C CN100461090 C CN 100461090C
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- stack
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- described instruction
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
- G06F9/4482—Procedural
- G06F9/4484—Executing subprograms
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/45—Caching of specific data in cache memory
- G06F2212/451—Stack data
Abstract
Executing an instruction on an operand stack, including performing a stack-state aware translation of the instruction to threaded code to determine an operand stack state for the instruction, dispatching the instruction according to the operand stack state for the instruction, and executing the instruction.
Description
Technical field
The present invention relates to storehouse high-speed cache field, more specifically, relate to and utilize code sharing to carry out the system of storehouse high-speed cache, method and apparatus.
Background technology
Explanation is a kind of widely used technology, is used to realize virtual machine (VM) and operational system, and advantage is portable and maintainable.VM, operational system and other high level language processors such as the Java processor, comprise the storehouse caching scheme and come virtually syllabified code to be mapped on the operand stack.One type storehouse caching scheme, mixed stack can use physical register and continuous storage area as operand stack.Interpreter plays an important role in many operational systems.Many modern programming language when they are for example programmed and move, still use the execution engine of different interpreters as them such as Java, Forth, Perl and Python on the memory/computation restraint device.
Linguistic interpretation based on storehouse may rely on the secondary data structure of the execution of operating instruction thereon, for example, and operand stack.Accessing operation is counted storehouse may relate to memory access.In order to improve the performance of explanation, people have adopted diverse ways.In the middle of those methods, the storehouse high-speed cache can approach to eliminate most of visit to operand stack effectively and also can quicken to explain.The storehouse high-speed cache may promote the transfer of top operand to register, and this can reduce the number of times of memory access and cause each higher round-robin instruction number.
Handle the different state of mixed stack, for example, storehouse high-speed cache interpreter can be kept many copies of run time version for each bar VM instruction.A kind of design like this can cause code explosion, and it may consume excessive storer and introduce maintenance complexity.
Description of drawings
From following description more specifically to one exemplary embodiment of the present invention, as illustrational in the accompanying drawings, the different example features and the advantage of embodiments of the invention will become apparent, in the accompanying drawing similarly the general indication of label identical, in similar unit similarly and/or on the structure on the function.
Fig. 1 describes the one exemplary embodiment according to the mixed stack of the embodiment of the invention;
Fig. 2 describes the one exemplary embodiment according to the system of the embodiment of the invention;
Fig. 3 A describes the one exemplary embodiment according to the method for the embodiment of the invention;
Fig. 3 B describes the one exemplary embodiment according to the method for the embodiment of the invention;
Fig. 4 describes the one exemplary embodiment according to the method for the embodiment of the invention;
Fig. 5 describes the one exemplary embodiment according to the code layout of the embodiment of the invention;
Fig. 6 A describes the one exemplary embodiment according to the code layout of the embodiment of the invention;
Fig. 6 B describes the one exemplary embodiment according to the code layout of the embodiment of the invention;
Fig. 6 C describes the one exemplary embodiment according to the code layout of the embodiment of the invention;
Fig. 6 D describes the one exemplary embodiment according to the code layout of the embodiment of the invention;
Fig. 6 E describes the one exemplary embodiment according to the code layout of the embodiment of the invention;
Fig. 6 F describes the one exemplary embodiment according to the code layout of the embodiment of the invention;
Fig. 6 G describes the one exemplary embodiment according to the code layout of the embodiment of the invention; And
Fig. 7 describes can be used for the computing machine of the some parts of the embodiment of the invention and/or the one exemplary embodiment of communication system.
Embodiment
Go through one exemplary embodiment of the present invention below.Although concrete one exemplary embodiment is discussed, should understand, do just illustrative purposes for example like this.Person skilled in the relevant art will recognize that under the situation that does not break away from the spirit and scope of the present invention, other parts and configuration also can be used.
Embodiments of the invention can be provided for the code sharing mechanism of storehouse high-speed cache, repeat to avoid code.The storehouse caching scheme can use the register-stack model of mixing, that is, be mapped to the mixed stack of syllabified code (for example, Java or CLI) operand stack virtually.Mixed stack can be made of two parts: register stack and memory stack.Register stack can comprise physical register, and they can preserve several top unit of operand stack.Memory stack can be territory, a connected storage, and it can preserve the unit of the remainder of described operand stack.
Fig. 1 describes the one exemplary embodiment of mixed stack 100.As shown in Figure 1, mixed stack 100 can comprise register stack 101 and memory stack 102.
Fig. 2 describes the one exemplary embodiment of virtual-machine architecture 200.Virtual-machine architecture 200 can comprise interpreter 201, loader 202, garbage collector 203, thread 204 and this machine module 205.In one exemplary embodiment of the present invention, interpreter 201 can comprise ALU (ALU) (not shown), storehouse (not shown) and storer (not shown).Interpreter 201 can use above-mentioned parts to come that the appropriate functional unit is deciphered and called in instruction and execute instruction.Loader 202 can be responsible for a class file load memory, class file is carried out grammatical analysis and is interpreter 201 preparation syllabified code instructions.Interpreter 201 can be the execution engine of VM, and for example, once explains an instruction.Garbage collector 203 can distribute new object and reclaim useless object.In one exemplary embodiment of the present invention, thread 204 can support application program DLL (dynamic link library) (API), and this machine module 205 can support for example to be used for the API of this hangar function.
In one exemplary embodiment of the present invention, machine instruction can be from the operand stack fetch operand, operates on it and the result is sent back to storehouse.Storehouse can be 32 storehouses, and for example it can be used for passing a parameter and the result of method of reseptance to method, and parameter is provided and preserves operating result for operation.In one exemplary embodiment of the present invention, as mentioned above, storehouse can be a mixed stack.
In one exemplary embodiment of the present invention, interpreter, the syllabified code that can keep most of (if not whole) to move on register stack rather than memory stack such as interpreter 201 instructs.Do the execution time that can reduce memory access and instruction like this.
In one exemplary embodiment of the present invention, interpreter may need to carry out shifting function, so that keep the stack top location of operand stack in the register stack.For example, if register of an instruction consumes as shown in Figure 3A then can be removed stack top register R1 from register stack, the end value of R2 may need to move on to the top, and R3 moves to R2.Because memory stack is not empty (register stack underflow), the numerical value in the position 1 also may be moved to R3, so that keep register stack to fill numerical value.After position 1 was taken away, memory stack pointer (sp) also was updated to sp ' possibly.On the other hand, shown in Fig. 3 B, if an instruction produces the numerical value that needs are pushed to register stack, then may need by the numerical value displacement downwards R1 that soars, that is R3 moves to position 0 (register file stack overflow), R2 moves to R3, and R1 moves to R2 then.
Although embodiments of the invention are described with regard to following example, described description for convenient, is not the application of wanting to limit it just.In fact, after the following description of reading, the technician of relevant industries obviously knows how to invent below (for example, under the common statement runtime environment) realization in the embodiment that substitutes.
In addition, explaining on the JAVA syllabified code although following description concentrates on focus, is not to want to limit purposes of the present invention.How realizing following invention, is conspicuous to the technician of relevant industries.When needing, in the embodiment that substitutes.For example, embodiments of the invention can use separately, or with the architecture of different virtual machine, such as, but be not limited to common statement infrastructure and other virtual execution systems are used in combination.
Fig. 4 illustrates in one exemplary embodiment of the present invention interpreter and how can work with mixed stack.In one exemplary embodiment of the present invention, instruction is experienced the translation of knowing stack states that becomes thread code possibly such as the syllabified code instruction, and it may enter the entrance of sharing run time version for carrying out described instruction indication.
Fig. 4 describes for example one exemplary embodiment from syllabified code to the transformation 400 of sharing run time version of instruction.As shown in Figure 4, before first time interpretation procedure, can instruct syllabified code 401 to be sent to the translater 402 of knowing stack states, or make an explanation by translater 402.The translater 402 of knowing stack states can produce thread code 403.According to described thread code 403, instruction 401 can be dispatched according to the operand stack state of described instruction.In one exemplary embodiment of the present invention, when dispatching described instruction, just can determine to enter the entrance 404 of sharing run time version, and can carry out described instruction from described entrance according to the operand stack state of instruction.
In one exemplary embodiment of the present invention, can embody stack states by the shifting function number of times that needs after the execution command.As using the shifting function number of times that needs after η (i) the expression execution command i here.For example, referring to Fig. 3 B, 3 shifting functions are arranged in Fig. 3 B.
The described method with reference to Fig. 4 is described for example, can instructs iadd to make example, come the one exemplary embodiment of interpretive code shared mechanism with addition of integer.In one exemplary embodiment of the present invention, register stack can be made of 2 registers, for example comprises stack top (tos) register and next stack top (no) register.For instruction iadd, may be useful on two possible stack states carrying out iadd, depend on η (iadd).IADD_S1 among Fig. 4 on the row 1 of run time version 404 can represent the situation of explaining IADD when η (iadd)=1, and the IADD_S0 on run time version 404 row 3 can be corresponding to the situation of η (iadd)=0.
The situation of consideration situation η (iadd)=1 when operand stack has two above unit, η (iadd)=1 may occur.In other words, when the memory stack non-NULL and η (iadd)=1 may appear in register stack when having expired.Because two operands of instruction iadd consumption (that is, be respectively tos and no), and produce an operand (new tos), for the top items on the memory stack is moved to register stack as new no, may only need a shifting function.The iadd instruction just can be dispatched to the row 1 of IADD_S1 situation (as shown in Figure 4) then.For example, the row 2 of IADD_S1 situation can eject the register to temp to the top unit of memory stack.Described then implementation can drop to the situation of IADD_S0 always, wherein uses the add operation (row 4) of register can explain the addition of integer operation.For example, by temp is moved on to no, so that two unit, the top of operand stack are remained in the register, row 5 can refill no.As described herein, row 2 and 5 combination can constitute described shifting function.
When considering the situation of η (iadd)=0, when operand stack has only two unit (two all are in register stack), η (iadd)=0 may appear.Under such a case, may need no shifting function, because only surplus next unit is as the result of add operation.Iadd can be dispatched to IADD_S0 (tos will be unique stack item after carrying out).As described above, row 4 can be explained the addition of integer operation.Execution refills statement (row 5) may become useless and redundant at that time, but may not influence program correctness, may be legal project because have only tos after the execution IADD.Under such a case, for the attribute of register-register assignment, performance penalty may be unessential.
As shown and desc, IADD_S0 and IADD_S1 can share same run time version, repeat to avoid excessive code.In one exemplary embodiment of the present invention, the run time version of different stack states and instruction scheduling can be reused with the comprehensive Design layout.In such an embodiment, for example, during the code threads stage, the stack states of each instruction can calculate out, and described then instruction can directly be dispatched to suitable execution inlet, and tables look-up when need not to move.In addition, the translating phase can be carried out some optimizing process, so that improve sequence of interpretation.
Fig. 5 describes the exemplary code layout 500 according to one exemplary embodiment of the present invention.As shown in Figure 5, OP_S
kExpression has operational code OP, and needs k (the explanation entrance that operand stack is kept in the inferior shifting function of η (i)=k) after carrying out i.For example, can illustrate the general code layout of all VM instructions as shown in Figure 5.
In Fig. 5, SO
kBe corresponding to OP_S
kThe code of shifting function.Carry out after the described operation, at SO
kIn the unit that is shifted can move to register stack (RO).In one exemplary embodiment of the present invention, OP_S
kCan also carry out its subsequent project OP_S
oTo OP_S
K-1All codes.In other words, in such an embodiment, can share code OP_S
oTo OP_S
K-1ID is the code that calls next instruction.
As example, consider the situation of register stack size M=2 (that is, as described above, 2 registers are arranged) in register stack.The characteristic of instruction I can be defined as [X (i), Y (i)], and wherein X (i) represents the number of the operand that i consumes, the number of the stack item that Y (i) expression i produces.Fig. 6 A-6G enumerates all possible code layout for 0≤X (i)≤M and 0≤Y (i)≤M.As example, former iadd example drops on the class of Fig. 6 D.
For its X (i)〉M or Y (i)〉instruction of M, the still code layout of type like the application class.In one exemplary embodiment of the present invention, as X (i)〉M or Y (i)〉during M, before run time version, may need to carry out more multiregister-memory shift operations.
As shown in Fig. 6 A-6G, each code layout is all represented specific class [X (i), Y (i)], and wherein X (i) represents the number of the operand that i consumes, and the number of the stack item that Y (i) expression i produces.In one exemplary embodiment of the present invention, know that the translating phase of stack states can be replenished code layout design.In such an embodiment, know that the translation of stack states can take place before execution command.Translater can be with the false code executive mode, for example, and the syllabified code of processing instruction, and be that each instruction produces suitable thread syllabified code inlet.Carry out on the point at each, translater can be recognized [X (i), Y (i)] characteristic of operand stack state and present instruction i.Translater can be calculated n (i) such as the result of calculation of f (Depth (opstack), M, X (i), Y (i)) correspondingly according to static table searching or comprehensive formula.
In described embodiment, the correctness of the described translation of knowing stack states can be based on the following fact: (constant during operation) determined before each syllabified code instruction and stack depth afterwards statically.Such translation may only need be carried out one time for most of syllabified code instructions.Such embodiment can allow to expose the more chance of optimizing in translation process.
Fig. 7 describes the one exemplary embodiment of computing machine and/or communication system, can be used for some parts of described system are included in the one exemplary embodiment of the present invention.Fig. 7 is described in the one exemplary embodiment of the computing machine 700 that can be used for some calculation elements in the one exemplary embodiment of the present invention.Computing machine 700 can include, but is not limited to: for example, any calculation element or communicator, for example, comprise personal computer (PC), workstation, mobile device, phone, hand-held PC, PDA(Personal Digital Assistant), thin client, fertile client, the network equipment, Internet-browser, call or warning device, TV, interactive television, receiver, tuner, high resolving power (HD) TV, HD receiver, video request program (VOD) system, server or other device.
In an exemplary embodiment, computing machine 700 can comprise the CPU (central processing unit) (CPU) or the processor 704 that can be coupled to bus 702.Processor 704 can be for example by bus 702 visit primary memorys 706.Computing machine 700 can be to be coupled to I/O (I/O) subsystem, such as network interface unit (NIC) 722 or the modem 724 of for example accesses network 726 usefulness.Computing machine 700 can also directly be coupled to supplementary storage 708 by bus 702 or by for example primary memory 706.Supplementary storage 708 can comprise for example disk memory device 710 or out of Memory storage medium.Exemplary disk memory device 710 can include, but is not limited to magnetic memory apparatus, such as for example hard disk, optical storage, such as for example only writing mutiread (WORM) driver or little CD (CD) or magneto-optical device.The supplementary storage 708 of another kind of type can comprise detachable sabot memory storage 712, it can with the information storage medium 714 of can removing stage makeup and costume, be used in combination such as for example CD-ROM or flexible plastic disc.Generally, the application program that disk memory device 710 can the storage operation computer system be used generally is called operating system.The document of disk memory device 710 all right stored data base (not shown).Computing machine 700 can interact by bus 702 and subsystem and disk memory device 710.Bus 702 can also be coupled to display 720, as output and input media, such as, but be not limited to keyboard 718 and mouse or other sensing/selecting arrangement 716.
The embodiment that illustrates in this manual and discuss just hopes and will teach the known diverse ways of the inventor to the professional and technical personnel, so that make and use the present invention.In this manual, anything all should not be regarded as and to limit the scope of the invention.The whole examples that provided all are representational and nonrestrictive.Without departing from the invention, can be appreciated that according to above-mentioned teaching that as the professional and technical personnel above-described embodiments of the invention can be revised or change.Therefore to understand, also can implement the present invention not according to specifically described method.
Claims (19)
1. method that on operand stack, executes instruction, described method comprises:
Finish described the instruction and know stack states translation so that determine the operand stack state of described instruction usefulness to thread code, comprise according to described stack states and determine to enter the entrance of sharing run time version, the described operand stack state of wherein said instruction usefulness is indicated by required shifting function number of times after carrying out described instruction, described shifting function is used for keeping stack top location, wherein finishes described translation and comprises:
Determine to carry out the described instruction number of operand on described operand stack in the past;
According to the operand number of described instruction consumes and the operand number of described instruction generation, the number of operand on the described operand stack after the described instruction of definite execution; And
Keep the required shifting function number of times of stack top location after extrapolating the described instruction of execution;
Dispatch described instruction according to the operand stack state of described instruction usefulness; And
Carry out described instruction.
2. the method for claim 1 is wherein carried out shifting function number of times required after the described instruction based on carrying out before the described instruction number of operand on the described operand stack and carrying out the number of the operand on the described operand stack after the described instruction.
3. the method for claim 1 is wherein carried out shifting function number of times required after the described instruction and is looked into showing according to static state and calculate out.
4. the method for claim 1, wherein said operand stack are the register stacks that mixes that comprises register stack and memory stack.
5. the method for claim 1, wherein said operand stack state comprise carries out the shifting function number of times of keeping the stack top location of described operand stack after the described instruction.
6. method as claimed in claim 5, wherein said stack top location comprises register stack.
7. method as claimed in claim 1 is characterized in that, also comprises: refill described operand stack.
8. a system comprises:
The operand stack that is used to execute instruction; And
Interpreter comprises
The assembly that is used for the state of definite described operand stack;
Be used for described instruction translation is the assembly of thread code; And
Be used for assembly according to the described instruction of node state scheduling of described operand stack;
The assembly that wherein is used for determining the state of described operand stack comprises: the sub-component that is used for determining to enter according to described stack states the entrance of sharing run time version, the described operand stack state of wherein said instruction usefulness is indicated by required shifting function number of times after carrying out described instruction, described shifting function is used for keeping stack top location, and
Wherein said being used for described instruction translation is that the assembly of thread code comprises:
Be used for determining to carry out the described instruction sub-component of the number of operand on described operand stack in the past;
Be used for the operand number that produces according to the operand number of described instruction consumes and described instruction to determine to carry out after the described instruction sub-component of the number of operand on the described operand stack; And
Be used to keep after extrapolating the described instruction of execution the sub-component of the required shifting function number of times of stack top location.
9. system as claimed in claim 8, wherein said operand stack are the mixed stack that comprises register stack and memory stack.
10. system as claimed in claim 9, wherein said register stack comprises at least one register of at least one the corresponding top unit that is used to keep described storehouse, and described memory stack comprises the contiguous storage zone that is used to keep the remaining unit of described operand stack.
11. an equipment that is used to carry out the instruction on the operation storehouse, described equipment comprises:
Be used for described virtual machine instructions being translated into the assembly of thread code according to the operand stack state of virtual machine instructions, comprise according to described stack states and determine to enter the entrance of sharing run time version, the described operand stack state of wherein said instruction usefulness is indicated by required shifting function number of times after carrying out described instruction, described shifting function is used for keeping stack top location, wherein is used for comprising according to the assembly that the operand stack state of virtual machine instructions is translated into thread code to described virtual machine instructions:
Be used for determining to carry out the described instruction assembly of the number of operand on described operand stack in the past;
Be used for the operand number that produces according to the operand number of described instruction consumes and described instruction to determine to carry out after the described instruction assembly of the number of operand on the described operand stack; And
Be used to keep after extrapolating the described instruction of execution the assembly of the required shifting function number of times of stack top location;
Be used for dispatching the assembly of described virtual machine instructions according to described operand stack state; And
Be used to carry out the assembly of described instruction.
12. want 11 described equipment as right, wherein said thread code is based on entering the entrance of sharing run time version.
13. equipment as claimed in claim 11 wherein also comprises:
Be used at the assembly of carrying out the operand number that exists on definite described operand stack before the described virtual machine instructions at every turn;
Be used for assembly at each operand number that exists on definite described operand stack after carrying out described virtual machine instructions; And
Be used to extrapolate the assembly that after carrying out described virtual machine instructions, keeps the required shifting function number of times of stack top location.
14. equipment as claimed in claim 12 is wherein carried out shifting function number of times required after the described instruction based on the number of the operand that exists on the described operand stack before the described instruction of each execution and each number of carrying out the operand that exists on the described operand stack after the described instruction.
15. equipment as claimed in claim 12 is wherein carried out shifting function number of times required after the described instruction and is looked into showing according to static state and calculate out.
16. comprising, equipment as claimed in claim 11, wherein said operand stack state carries out the shifting function number of times that described virtual machine instructions is kept the stack top location of operand stack afterwards.
17. equipment as claimed in claim 16, wherein said stack top location comprises register stack.
18. equipment as claimed in claim 11 wherein also comprises:
Be used to carry out the several times shifting function so that stack top location is substituted into the assembly of operand stack.
19. the number of the unit that equipment as claimed in claim 18, the number of times of wherein said shifting function produce based on the number of the unit on the operand stack that described virtual machine instructions consumed and described virtual machine instructions.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2004/000290 WO2005096136A1 (en) | 2004-03-31 | 2004-03-31 | Stack caching using code sharing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1926509A CN1926509A (en) | 2007-03-07 |
| CN100461090C true CN100461090C (en) | 2009-02-11 |
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| CNB2004800425684A Expired - Fee Related CN100461090C (en) | 2004-03-31 | 2004-03-31 | Stack high-speed memory using code sharing |
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| Country | Link |
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| CN (1) | CN100461090C (en) |
| WO (1) | WO2005096136A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US10265311B2 (en) | 2009-07-22 | 2019-04-23 | PureTech Health LLC | Methods and compositions for treatment of disorders ameliorated by muscarinic receptor activation |
| US9436475B2 (en) * | 2012-11-05 | 2016-09-06 | Nvidia Corporation | System and method for executing sequential code using a group of threads and single-instruction, multiple-thread processor incorporating the same |
| CN115237475B (en) * | 2022-06-23 | 2023-04-07 | 云南大学 | Forth multi-core stack processor and instruction set |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6273335A (en) * | 1985-09-27 | 1987-04-04 | Toshiba Corp | Stack control system |
| US5070451A (en) * | 1984-11-21 | 1991-12-03 | Harris Corporation | Forth specific language microprocessor |
| US6131144A (en) * | 1997-04-01 | 2000-10-10 | Sun Microsystems, Inc. | Stack caching method with overflow/underflow control using pointers |
| CN1295279A (en) * | 1999-11-09 | 2001-05-16 | 摩托罗拉公司 | Device and method for execution of stack pull and push-down operation in processing system |
| CN1440528A (en) * | 2000-10-05 | 2003-09-03 | Arm有限公司 | Storing stack operands in registers |
-
2004
- 2004-03-31 WO PCT/CN2004/000290 patent/WO2005096136A1/en active Application Filing
- 2004-03-31 CN CNB2004800425684A patent/CN100461090C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5070451A (en) * | 1984-11-21 | 1991-12-03 | Harris Corporation | Forth specific language microprocessor |
| JPS6273335A (en) * | 1985-09-27 | 1987-04-04 | Toshiba Corp | Stack control system |
| US6131144A (en) * | 1997-04-01 | 2000-10-10 | Sun Microsystems, Inc. | Stack caching method with overflow/underflow control using pointers |
| CN1295279A (en) * | 1999-11-09 | 2001-05-16 | 摩托罗拉公司 | Device and method for execution of stack pull and push-down operation in processing system |
| CN1440528A (en) * | 2000-10-05 | 2003-09-03 | Arm有限公司 | Storing stack operands in registers |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2005096136A1 (en) | 2005-10-13 |
| CN1926509A (en) | 2007-03-07 |
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