CN100472788C - Quickflashing memory device and its forming method - Google Patents

Abstract

The invention relates to a quick-flashing memory and relative deforming method. Wherein, said quick-flashing memory comprises the first group of float gates with selective micro image process at minimum line width, which comprises several first float gates above the bottom gate oxide layer; the second group of float gates with several float gates; the first and second float gates are continuously deposited, while each second float gate is deposited between each couple of first float gates; it has several space walls, while each one is deposited between nearby first and second float gates; and it has several control gates connected to the float gates, while the width of space wall and/or second float gate is lower than minimum line width.

Description

Flash memory device and forming method thereof

Technical field

The invention relates to a kind of flash memory device and forming method thereof.

Background technology

The anti-electrical removable programmable read-only memory of type (the electrically erasableprogrammable read only memory that reaches; EEPROM) or flash memory (FLASH memory) gradually become the substitute of hard disk, therefore having high power capacity, low cost, attenuating memory cell size is that people are pursued with the device that reaches miniaturization and speed up processing.

United States Patent (USP) the 5th, 050, disclose a kind of non-volatile semiconductor memory No. 125, its each bit line has a serial connection flash memory cell array (being shown in this patent profile shown in Figure 4), and the size of memory cell and zone are defined with the product of corresponding control gate and adjacent insulation layer (the Y direction of Fig. 4) by the width of floating grid and adjacent insulation layer (directions X of Fig. 4).In other words, the zone of overlapping is floating grid and control gate.The upper limit that memory cell size in each this patent is dwindled is about 4F ²To 5F ²F representative in this patent processing procedure by minimum pattern size or live width that lithography technique obtained, minimum pattern size is about 90 rice how at this moment, and when the minimum widith of control gate and adjacent control gate minimum spacing are all 1F, suppose that the minimum spacing of adjacent floating grid in the minimum widith of floating grid and the floating grid array all is about 1F.Therefore, each memory cell occupies the width of 2F at least at directions X, and then arrives 2.5F for 2F in the Y direction.

Therefore the global density that increases the flash memory cell array provides a kind of flash memory to by being asked, and its memory cell size is not subject to the minimum feature by the lithography technique gained.

Summary of the invention

A kind of flash memory device and forming method thereof, this flash memory device have comprised the first group of floating grid that uses the selectivity photoetching of minimum feature, wherein more comprise a plurality of first floating grids on the grid oxic horizon that is formed at substrate; Second group of floating grid with a plurality of second floating grids, wherein these first and second floating grid successive sedimentations, promptly each second floating grid is deposited on each between first floating grid; A plurality of clearance walls, each clearance wall are deposited on each between first and second adjacent floating grid; And the control gate of a plurality of these floating grids of binding, wherein the width of these clearance walls and/or second floating grid is less than minimum feature.

Above-mentioned and other feature of the present invention can by following preferred embodiment and corresponding graphic detailed description provide more speak more bright with understand.

Description of drawings

Fig. 1 to Figure 16 is front elevational schematic and the generalized section that flash memory cell array of the present invention forms.

3-3,8-8: hatching

10: semiconductor combinations

12: substrate

14: the pass gates oxide layer

16: the first polysilicon layers

16a: second polysilicon layer

16b: polysilicon layer

16c: the 3rd polysilicon layer

18,18a, 18a ': polysilicon gate

19,24,28,35,42: passage

20: the first clearance walls

21: wall embeded formula passage

22: layer of spacer material

26: oxide skin(coating)

30: ion is implanted

31: shallow trench isolation regions

32: dielectric layer

34: the character line

36: cover curtain zone

38: cross-section place

40: electrical contact point

44: source electrode or drain electrode N+ ion are implanted

Embodiment

Fig. 1 discloses semiconductor combination 10, and this semiconductor combinations with multilayer comprises a substrate 12 forming transistor and Connection Element, and can be silicon, SiGe, three or five compounds of group substrates and other can reach the alternative material of identical effect; One pass gates oxide layer 14 as dielectric layer be formed at substrate 12 and form between the device, and can be by chemical vapour deposition (CVD) (chemical vapordeposition; CVD) or heat become long-range order to form, for example thickness is between the silicon oxide layer of 50 to 100 dusts (A); And one first polysilicon layer 16 be formed on the pass gates oxide layer 14, for example by chemical vapour deposition (CVD) or the spin-coating mode of coating to form.

As shown in Figure 2, first polysilicon layer 16 that is deposited is carved the first group of polysilicon gate 18 that can be used as first group of floating grid with formation by figure, and its method can be known photoetching.In one embodiment, each polysilicon gate 18 can be carved the step utilization at figure and has the selectivity photoetching of a minimum feature (1F) and form.

Fig. 2 further discloses a layer of spacer material 22, it comprises the silicon oxide layer or the silicon nitride layer of deposition, with first polysilicon layer 16 and the polysilicon gate 18 of coverage diagram after quarter, and part is inserted its passage 19 (figure carves the zone between the polysilicon gate 18 in the step), to produce wall embeded formula passage 21 in passage 19.

As shown in Figure 3, layer of spacer material in passage 19 22 is etched forming first clearance wall 20, and first clearance wall 20 is contiguous to each polysilicon gate 18, and first clearance wall 20 of adjacency is separated by passage 24.The isotropic dry etch processing procedure can be used for layer of spacer material 22 and forms passage 24 to produce first clearance wall 20, each passage 24, particularly etched channels 21 under pass gates oxide layer 14.When selected dry etch process in spacer material 22 but not during the polycrystalline silicon material sound response, passage 24 forming processes do not need the cover curtain.Passage 24 can be narrower than minimum feature (1F), and in one embodiment, the passage 19 between the polysilicon gate 18 can be wider than 1F, and the width of passage 24 is similar to the width 1F of polysilicon gate 18.

In one embodiment, spacer material 22 comprises that a Si oxide and comprises CHF ₃, CHF ₄And the dry ecthing agent of He etch chemistries.In another embodiment, spacer material 22 can comprise silicon nitride, and uses Ar and CF in dry etch process ₄Etch chemistries.

When first polysilicon layer 16 is schemed to have the polysilicon gate 18 of minimum feature with formation quarter, each has the passage 19 that is large enough to hold a passage 24 and the width of a pair of clearance wall and promptly is formed, and each passage 19 is formed and can produces width greater than minimum feature by photoetching.As described later, each passage 24 is in order to form the second group of polysilicon gate 18a (Fig. 6) between the polysilicon gate 18.In order to dwindle the spacing of polysilicon gate, passage 19 can be less than three times of minimum feature, and lithographic printing can accurately form passage 19.In one embodiment, the width of each passage 24 is less than or equal to minimum feature, is preferable selection and wherein equal the feasible width coupling with polysilicon gate 18 of minimum feature.In one embodiment, use the selectivity dry etch procedure but not imprint lithography can make the width of clearance wall 20 and passage 24 all less than minimum feature.

For instance, for one 0.11 micron imprint lithography was used, the width of polysilicon gate 18 was 0.11 micron, and the width of passage 19 is 0.17 micron, and the width of passage 24 is 0.11 micron, and the width of clearance wall 20 is 0.03 micron.

Utilizing after dry ecthing forms each passage 24, because can impairment in the etching process that forms passage 24 or remove the pass gates oxide layer 14 of a part of passage 24, so its reconstruction be necessary.In one embodiment, a thin oxide (for example 40 dusts) is used to heat treatment one wafer, and oxide skin(coating) 26 also is formed and covers first polysilicon layer 16 of having schemed to carve in this process part.In another embodiment, the wet etching program is used to remove the thin oxide of this kind that is formed at substrate surface, to eliminate the damage that forms 24 pairs of substrates 12 of passage in etching process.Therefore, pass gates oxide layer 14 rebuilt (for example by growing up again) is on passage 24.

Fig. 4 is the front elevational schematic of structure shown in Figure 3, that is Fig. 3 is 3-3 line segment formed generalized section on same straight line of Fig. 4.First polysilicon layer 16 is carved to form a sinuous pattern by figure, passage 24 defines sinuous pattern with clearance wall 20 with first floating grid that is extended this sinuous pattern pin position by polysilicon gate 18 forms, the periphery that is adjacent to first polysilicon layer 16 of this sinuous pattern can be used for forming the polysilicon gate of peripheral transistor, for example one selects transistor promptly to be used for other transistors of integrated circuit (IC) logic.

As shown in Figure 5, one second polysilicon layer 16a is deposited on first polysilicon layer 16 of figure after quarter, and inserts the passage 24 that is formed between first clearance wall 20 has a plurality of polysilicon gate 18a that separate with generation second group of floating grid.As previously mentioned, in one embodiment, each passage 24 wishes it is that the utilization photoetching makes it equal minimum feature and in order to form polysilicon gate 18, therefore each extra polysilicon gate 18a that inserts corresponding passage 24 can use photoetching to make it equal minimum feature, but because clearance wall 20 can be narrower than minimum feature, so each zone will have more polysilicon gate to form, make memory cell size dwindle and the increase of storage arrangement density.

As shown in Figure 6, the second polysilicon layer 16a selectivity is etched back to first polysilicon layer 16, oxide skin(coating) 26 also is hoped and can removes at this etching program, therefore, produce the polysilicon layer that a complete graph is carved, it has a plurality of by polysilicon gate 18 and the formed floating grid of 18a, and oxide skin(coating) 26 can remove in the program as an etching end point in this.In one embodiment, can select a gaseous etchant chemicals Cl for use ₂And HBr acts on silicon dioxide (SiO ₂) on polysilicon; In addition, can use a cmp (chemical mechanical polishing; CMP) handle.

Fig. 7 is a front elevational schematic, and the complete graph that has first clearance wall 20 that can isolate polysilicon gate 18 and 18a in order to demonstration is carved polysilicon layer.

Fig. 8 is 8-8 line segment formed generalized section on same straight line of Fig. 7.As shown in Figure 8, first clearance wall 20 is removed in modes such as selectivity dry ecthings, and providing between polysilicon gate 18 passage 28 with 18a, and passage 28 extends to pass gates oxide layer 14.When first clearance wall 20 has identical oxide with Fig. 5 embodiment with as oxide skin(coating) 26 time, an oxide etch program is in order to remove this oxide skin(coating) 26 and first clearance wall 20.When first clearance wall 20 is to be made by silicon nitride (SiN), carry out a nitride selectivity silicon dry ecthing between polysilicon gate 18 and 18a, to remove first clearance wall 20.In one embodiment, the etchant chemistry product can comprise the Ar and the CF of gaseous state ₄

Remove after first clearance wall 20, shallow ion is implanted 30 and is formed under substrate 12 and the passage 28.Carrying out the ion implantation is according to a known industrial procedure, for example planting N+ ion is in a p type substrate 12, and this N+ ion is implanted and formed a corresponding metal oxide semiconductcor field effect transistor (metal-oxide semiconductor field effect transistor; MOSFET) source electrode of memory cell and drain region.In addition, manyly ion is implanted 30 bunchiness cross by polysilicon gate 18 and the formed floating grid of 18a, so that the metal oxide semiconductcor field effect transistor memory cell of serial connection to be provided, for example be applied in a string column array or 16 to 32 serial connection strings of transistors of the flash memory chip of 256 megabit tuples to tens, hundred million bit groups.

In another embodiment, because not carrying out the ion of each metal oxide semiconductcor field effect transistor memory cell implants, therefore do not need passage 28, and by charging imports a fringe field in substrate 12 to open the substrate surface under first clearance wall for charged character line 34 (Figure 14), this fringe field effect can be connected in series transistor.

As shown in Figure 9, passage 28 then is filled by oxide deposition or silicon nitride deposition, implants on 30 in ion to restore first clearance wall 20, and wherein first clearance wall 20 of this extension is in order to electrically isolated polysilicon gate 18 and 18a.In addition, the ion of 16 to 32 serial connections implant 30 and corresponding memory transistor strings of transistors is provided, and the every pair of ion implant 30 and corresponding transistor be adjacent to one and be positioned at substrate 12 and in order to isolate each transistorized transistor shallow trench isolation (shallowtrench isolation; STI) zone 31 (see also Figure 10, they are the formed generalized sections of 10-10 line segment of Fig. 7).Known this skill person should understand: shallow trench isolation regions 31 is formed at before 16 formation of first polysilicon layer, though Fig. 7 only shows two shallow trench isolation regions 31 as representative, integrated circuit generally includes thousands of shallow trench isolation regions 31.

As shown in figure 11, floating grid polycrystalline silicon grid layer (first polysilicon layer 16 and polysilicon gate 18 and 18a that comprises periphery) is etched back to a target thickness, has polysilicon gate 18 ' with the polysilicon layer 16b of 18a ' with formation.In one embodiment, etching program can be to use gaseous state Cl ₂And the temporal mode selectivity dry etch procedure of HBr control remaining polysilicon grid thickness, and restore first clearance wall 20 and protrude on the floating grid polycrystalline silicon grid layer.

Then, as shown in figure 12, dielectric layer 32 (a for example ONO (oxide/Nitride/oxide) layer) forms so that the electrical isolation of each floating grid that covers polysilicon gate 18 ' and 18a ' to be provided.Dielectric layer 32 wishes can make after being deposited passage 35 still to be retained on each first clearance wall 20 and the floating grid usually.In one embodiment, the ONO clearance wall can be by low-pressure chemical vapor deposition (low pressurechemical vapor deposition; LPCVD) deposit, the oxide skin(coating) at bottom and top can be by the SiH of gaseous state ₂Cl ₂And O ₂And form, and the nitride layer of sandwich-like can be by the SiH of gaseous state ₂Cl ₂And N ₂And form, wherein cap oxide layer, nitride layer and bottom oxide layer thickness are respectively 20,80 and 40 dusts, and these thickness are controlled by known deposition program parameter.

One control grid layer then by deposition one the 3rd polysilicon layer 16c on dielectric layer 32 and form, as shown in figure 13.The 3rd polysilicon layer 16c inserts passage 35, and ' separate with 18a ', it repeats aforesaid polysilicon deposition step to be made itself and polysilicon gate 18 by dielectric layer 32.

As shown in figure 14, the 3rd polysilicon layer 16c of dielectric layer 32 is then eat-back by selectivity, so that the formed character line 34 of the control gate that is formed at passage 35 (as shown in figure 13) to be provided.Adopt a utilization gaseous state HBr or a Cl at this ₂The selectivity dry ecthing, and use the ONO layer as the etching end point layer.

One fringe field effect (fringe field effect) is imported into by the fringe field electric capacity of the substrate 12 under first clearance wall 20, when control gate is applied in a bias voltage or the lasting charging of one of them floating grid quilt, substrate surface may produce an inversion layer (inversion layer) or passage (channel), implant 30 with the serial connection adjacent memory unit as same ion, and the fringe field effect can be used as another selection that source electrode and drain ion implantation 30 are provided.Therefore, can remove the step that removes first clearance wall 20, implanting ions implantation 30 and restore first clearance wall 20 from by the fringe field effect.

In addition, character line 34 is positioned at the ONO layer and covers with other in order to first clearance wall 20 that separates character line 34, it is to be narrower than the minimum feature that photoetching produces that the width of each first clearance wall 20 and ONO layer is hoped, the floating grid spacing is the width of first clearance wall 20, just about 300 dusts, and the width of control gate is narrower than the width of floating grid, approximately differs the twice of ONO layer thickness.For instance, if the floating grid width is about 0.014 micron of 0.11 micron and an ONO layer width, then control gate approximately is 0.11 to deduct 0.014 of twice, or 0.082 micron.

This front elevational schematic of Figure 15 shows that cover curtain zone 36 is to indicate cross-section place 38, provide the character line in this sinuous pattern to form independently character line 34 by this, and more having disclosed representative electrical contact point 40 each hole by formed each control gate of character line, the setting of these electrical contact points 40 is for the line of the gate control lines of setting up electrical removable programmable read-only memory (not being shown among the figure) with corresponding character line 34.

Figure 16 shows by the passage 42 of ONO layer 32 with bottom polysilicon layer 16b institute shape.For instance, passage 42, carries out selective etch to passage 42 positions of ONO layer 32 then, and then floating grid polycrystalline silicon grid layer 16b is carried out selective etch to make by the total beyond the shade passage 42.A single gate mos field-effect transistor selects transistorized source electrode or drain electrode N+ ion implantation 44 to be planted the substrate 12 of portion under passage 42, every character line 34 is connected to the gate control lines (not being shown among the figure) of electrical removable programmable read-only memory by the selection transistor of correspondence, United States Patent (USP) the 5th as described above, 050, No. 125 revealer of institute.

Known this skill person should understand a complete flash memory device can comprise that still selection, control, read-write, sensing and other are not shown in this and are bordering on known circuit, as aforesaid U.S. Patent the 5th, 050, and No. 125 disclosed circuit.

If technology evolution makes that minimum feature (F) is 0.11 micron, and the live width of polysilicon gate 18 and 18a approximates minimum feature respectively, and then the width of each illustrative memory cell directions X is about 0.11 and adds 0.03 micron (i.e. width of first clearance wall 20).If memory cell size is about 2.5F in the Y direction, then the memory cell area of 0.11 micron flash memory is approximately less than 3.2F ², making memory span dwindle because of memory cell size has remarkable lifting, and cost also descends thereupon.

Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.

Claims (23)

1, a kind of flash memory device is characterized in that it comprises:

First group of floating grid comprises a plurality of first floating grids on the grid oxic horizon that is formed on the substrate, and this first group of floating grid uses the selectivity photoetching with minimum feature;

Second group of floating grid comprises a plurality of second floating grids, wherein these a plurality of first floating grids and these a plurality of second floating grid successive sedimentations, and each these a plurality of second floating grid is deposited between each these a plurality of first floating grid;

A plurality of clearance walls, each these a plurality of clearance wall are deposited between each adjacent these a plurality of first floating grid and this a plurality of second floating grids; And

A plurality of control gates are arranged on these a plurality of first and second floating grids, and wherein these a plurality of clearance walls and/or this a plurality of second floating grids have the width littler than this minimum feature.

2, flash memory device according to claim 1, the width that it is characterized in that these a plurality of control gates wherein is less than this minimum feature.

3, flash memory device according to claim 2, the height that it is characterized in that these a plurality of clearance walls wherein is greater than these a plurality of first floating grids and these a plurality of second floating grids, and these a plurality of control gates are deposited on these a plurality of first floating grids and this a plurality of second floating grids and between these a plurality of clearance walls.

4, flash memory device according to claim 3 is characterized in that it more comprises:

Dielectric layer is deposited between these a plurality of control gates and this a plurality of first and second floating grids.

5, flash memory device according to claim 1 is characterized in that it more comprises:

This substrate under these a plurality of clearance walls is implanted in doped source/drain region.

6, flash memory device according to claim 1 is characterized in that these a plurality of first floating grids wherein are to each other at interval less than the distance of three times of these minimum feature.

7, flash memory device according to claim 1 it is characterized in that wherein the width of these a plurality of second floating grids is this minimum feature, and the width of these a plurality of clearance walls is less than this minimum feature.

8, a kind of flash memory device formation method is characterized in that it comprises:

On substrate, form grid oxic horizon;

The selective light that utilization has minimum feature is engraved on formation first polysilicon layer on the grid oxic horizon;

The deposition spacer material is between a plurality of first floating grids;

Etched channels forms a plurality of clearance walls in this spacer material, with in abutting connection with these a plurality of first floating grids, comprises the floating grid of first group of gapped wall of these a plurality of first floating grids with formation; And

On this substrate and this passage, deposit second polysilicon layer, comprise the floating grid of second group of gapped wall of a plurality of second floating grids with formation.

9, flash memory device formation method according to claim 8, the width that it is characterized in that these a plurality of clearance walls wherein and/or these a plurality of second floating grids is less than this minimum feature.

10, flash memory device formation method according to claim 9 is characterized in that it more comprises:

The height of these a plurality of first floating grids of etching and these a plurality of second floating grids is to the height less than these a plurality of clearance walls;

Form dielectric layer on these a plurality of clearance walls and leave passage between these a plurality of clearance walls with these a plurality of first and second floating grids on;

Deposit the 3rd polysilicon layer on this substrate, to fill up this passage between these a plurality of clearance walls; And

Etching the 3rd polysilicon layer is to form polysilicon control grid between these a plurality of clearance walls and on these a plurality of first and second floating grids.

11, flash memory device formation method according to claim 10, the width that it is characterized in that this polysilicon control grid wherein is less than this minimum feature.

12, flash memory device formation method according to claim 8 is characterized in that these a plurality of first floating grids wherein are to each other at interval less than the distance of three times of these minimum feature.

13, flash memory device formation method according to claim 12 it is characterized in that wherein the width of these a plurality of second floating grids is this minimum feature, and the width of these a plurality of clearance walls is less than this minimum feature.

14, flash memory device formation method according to claim 8 is characterized in that this spacer material of wherein etching comprises the isotropic dry etch processing procedure.

15, flash memory device formation method according to claim 8 is characterized in that it more comprises:

Remove this a plurality of clearance walls;

Form doped source/drain region in this substrate in abutting connection with these a plurality of first floating grids and these a plurality of second floating grids; And

Rebuild this a plurality of clearance walls.

16, flash memory device formation method according to claim 8 is characterized in that it more comprises:

Behind this etching step, before depositing this second polysilicon, rebuild this grid oxic horizon in this passage.

17, a kind of flash memory device formation method is characterized in that it comprises:

Form the pass gates oxide layer on substrate;

Deposition ground floor polysilicon;

The selectivity photoetching that utilization has a minimum feature removes this ground floor polysilicon of part, comprises the floating grid of first group of gapped wall of a plurality of first floating grids with formation, wherein this a plurality of first floating grids to each other the interval less than the distance of three times of these minimum feature;

Deposition spacer material layer is on this substrate and between these a plurality of first floating grids;

This spacer material layer of dry ecthing is to form in abutting connection with a plurality of clearance walls of these a plurality of first floating grids and in abutting connection with the respective channel between these a plurality of clearance walls, wherein the width of this respective channel equals this minimum feature, and the width of these a plurality of clearance walls is less than this minimum feature;

Deposit second layer polysilicon this respective channel between these a plurality of clearance walls, comprise second group of floating grid of a plurality of second floating grids with formation;

The height of these a plurality of first floating grids of etching and the height of these a plurality of second floating grids are extremely less than these a plurality of clearance walls;

Dielectric layer and leaves a plurality of corresponding control gate passages between these a plurality of clearance walls on these a plurality of clearance walls and this a plurality of first and second floating grids;

Deposit the 3rd layer of polysilicon to fill up this a plurality of corresponding control gate passages; And

Eat-back the 3rd layer of polysilicon.

18, flash memory device formation method according to claim 17, wherein eat-backing the 3rd layer of polysilicon is to form with the pattern that wriggles, and it is characterized in that wherein said method more comprises:

The 3rd layer of polysilicon of selective etch is to form these a plurality of corresponding control gate passages corresponding to these a plurality of first and second floating grids.

19, flash memory device formation method according to claim 17 is characterized in that wherein these a plurality of corresponding control gate width of channel are less than this minimum feature.

20, flash memory device formation method according to claim 17 is characterized in that it more comprises:

After dry etching steps, rebuild this grid oxic horizon in this respective channel.

21, a kind of flash memory device is characterized in that it comprises:

The floating grid of a plurality of serial connections is formed on the grid oxic horizon on the substrate, and the live width of these a plurality of floating grids is smaller or equal to the minimum feature of selectivity photoetching;

A plurality of clearance walls, each these a plurality of clearance wall are deposited between each adjacent first floating grid and second floating grid; And

A plurality of control gates are arranged on these a plurality of floating grids.

22, flash memory device according to claim 21 is characterized in that it more comprises:

Dielectric layer, be deposited between these a plurality of control gates and this a plurality of floating grids, wherein the height of these a plurality of clearance walls is greater than the height of these a plurality of floating grids, and these a plurality of control gates are deposited on these a plurality of floating grids and between these a plurality of clearance walls, therefore the width of these a plurality of control gates is less than this minimum feature.

23, flash memory device according to claim 22 is characterized in that it more comprises:

This substrate under these a plurality of clearance walls is implanted in doped source/drain region.

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