CN100481555C - 工字型相变存储单元、制造方法及包含该单元的阵列 - Google Patents

工字型相变存储单元、制造方法及包含该单元的阵列 Download PDF

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CN100481555C
CN100481555C CNB2006101360349A CN200610136034A CN100481555C CN 100481555 C CN100481555 C CN 100481555C CN B2006101360349 A CNB2006101360349 A CN B2006101360349A CN 200610136034 A CN200610136034 A CN 200610136034A CN 100481555 C CN100481555 C CN 100481555C
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陈士弘
龙翔澜
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Macronix International Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
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    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
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    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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    • H10N70/801—Constructional details of multistable switching devices
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    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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    • H10N70/801—Constructional details of multistable switching devices
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    • H10N70/828—Current flow limiting means within the switching material region, e.g. constrictions
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    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
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    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/884—Other compounds of groups 13-15, e.g. elemental or compound semiconductors
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    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells

Abstract

一种存储元件包括：第一电极及第二电极，其垂直地分离并具有相向的接触表面，其间则有相变单元。此相变单元包括上相变构件，其具有与此第一电极形成电接触的接触表面；下相变构件，其具有与此第二电极形成电接触的接触表面；以及核心构件，其夹置于此上与下相变构件之间并与此两者形成电接触。此相变单元由具有至少二固相的材料所构成，且此上与下相变构件的横向面积实质上大于此核心构件的横向面积。中间绝缘层夹置于此上与下相变构件之间并邻接至此核心构件。

Description

工字型相变存储单元、制造方法及包含该单元的阵列
技术领域
本发明涉及以相变存储材料为基础的高密度存储元件，包括以硫族化物为基础的材料与其它材料。本发明还涉及此类组件的制造方法。
背景技术
以相变为基础的存储材料被广泛地运用于读写光盘片中。这些材料包括有至少两种固相，包括如大部分为非晶态的固相，以及大体上为晶态的固相。激光脉冲用于读写光盘片中，以在两种相中切换，并读取此种材料在相变之后的光学特性。
如硫族化物及类似材料的此类相变存储材料，可通过施加其幅度使该幅度适于集成电路中的电流，而致使晶相变。一般而言非晶态的特征是其电阻高于晶态，此电阻值可轻易测量得到而用以作为指示。这种特性则引发使用可编程电阻材料来形成非易失性内存电路等的兴趣，此电路可用于随机存取读写。
从非晶态转变至晶态一般为低电流步骤。从晶态转变至非晶态(以下指称为重置(reset))一般为高电流步骤，其包括短暂的高电流密度脉冲以熔化或破坏结晶结构，其后此相变材料会快速冷却，抑制相变的过程，使得至少部份相变结构得以维持在非晶态。理想状态下，致使相变材料从晶态转变至非晶态的重置电流幅度应该越低越好。欲降低重置所需的重置电流幅度，可通过减低在内存中的相变材料组件的尺寸、以及减少电极与此相变材料的接触面积而达成，因此可针对此相变材料组件施加较小的绝对电流值而达成较高的电流密度。
此领域发展的一种方法致力于在集成电路结构上形成微小孔洞，并使用微量可编程的电阻材料填充这些微小孔洞。致力于此等微小孔洞的专利包括：1997年11月11日发布的美国专利第5,687,112号”Multibit Single Cell Memory Element Having Tapered Contact”、发明人为Ovshinky；于1998年8月4日发布的美国专利第5,789,277号”Method of Making Chalogenide[sic]Memory Device”、发明人为Zahorik等；于2000年11月21日发布的美国专利第6,150,253号”Controllable Ovonic Phase-Change Semiconductor Memory Device andMethods of Fabricating the Same”、发明人为Doan等；以及于1999年7月6日发布的美国专利第5,920,788号”Chalcogenide Memory Cellwith a Plurality of Chalcogenide Electrodes”、发明人为Reinbergs。
已知相变存储器与结构的一个特定问题，是现有技术中的热库效应(heat sink effect)。一般而言，现有技术教导了在相变存储单元的双面使用金属电极的方式，且此电极的尺寸大约与相变单元相同。此种电极作为热沉，此金属的高导热性快速地将热量抽离此相变材料。由于相变现象为加热作用的结果，此热沉效应则导致其需要较高的电流方能产生理想的相变。
而且，在以非常小的尺度制造这些装置、以及欲满足大规模生产存储装置所需求的严格工艺变型时，则会遭遇到问题。优选地提供一种存储单元(memory cell)结构，其包括有小尺寸和低重置电流、以及一种用以解决上述热传导问题的结构和用以制造此类结构的方法，此类结构可满足大规模生产存储装置时的严格工艺变型规范。因此优选地提供一种制造过程以及一种结构，其可在同一集成电路上搭配制造周边电路。
发明内容
本发明的一个实施例提供了存储元件其包括两彼此垂直分离且具有相向的接触表面的电极，此两电极间夹置了相变单元。此相变单元包括上相变构件，其具有与第一电极形成电接触的接触表面；下相变构件其具有与第二电极形成电接触的接触表面；以及核心构件其置于此上与下相变构件之间，并与此两者形成电接触。此相变单由一具有至少两固相的材料所构成，且此上与下相变构件的横向面积实质上大于此核心构件的横向面积。在此上与下相变构件之间夹置了与核心构件紧邻的中间绝缘层。
本发明的另一观点中，提供用以构建相变存储单元的方法，其包括：设置具有电极单元延伸于其中的基板；沉积第一层相变材料于此基板上至理想厚度；沉积核心层相变材料于此第一相变层之上，此核心层具有理想厚度、且其宽度实质上小于第一层的宽度；以及沉积一第二相变层于此核心层上，此第二层具有理想厚度，且其宽度实质上与第一层相同。
本发明的另一观点提供计算机内存阵列，包括用于传输字与位使能信号至此阵列的数据传输线、以及多个存储单元。每一存储单元包括至少存取晶体管以及相变单元，且每相变单元包括上相变构件；下相变构件；以及夹置于上与下相变构件间且与此两者电接触的核心相变构件。在此相变单元中，此相变单元以具有至少两固相的材料所构成，且此上与下相变构件的横向面积实质上大于核心构件的横向面积。
以下详细说明本发明的结构与方法。本发明内容说明章节目的并非在于限制本发明。本发明由权利要求所限定。所有本发明的实施例、特征、观点及优点等将可透过下列说明权利要求及所附图示获得充分了解。
附图说明
图1示出本发明的相变存储单元的一个实施例；
图2示出在本发明的一个实施例中估计的电场与电流分布；
图3A与图3B示出根据本发明的计算机存储单元，其包括相变单元；
图4示出根据本发明的计算机存储电路的示意图，所述计算机存储电路包括相变单元；
图5示出根据本发明的计算机存储电路的方块图，所述计算机存储电路包括相变单元；
图6示出制造本发明的相变存储单元时的一个步骤；
图7示出制造本发明的相变存储单元时的一个步骤；
图8示出制造本发明的相变存储单元时的一个步骤；
图8A示出制造本发明的相变存储单元时的一个替代步骤；
图9示出制造本发明的相变存储单元时的一个步骤；
图10示出制造本发明的相变存储单元时的一个步骤。
具体实施方式
下面的详细说明将参考各图示。优选实施例仅用以具体描述本发明，而非用以限制本发明的范围，本发明的范围以权利要求界定。本领域技术人员依据下列叙述将能了解许多等效的变化形式。
图1示出本发明的相变存储单元的基本布局。众所周知的，相变随机存取存储(phase change random access memory，PCRAM)单元10包括相变单元17，其由具有两种固相的材料所构成。优选地，施加适当的电流脉冲至此材料时，其从非晶态(amorphous)切换至晶态(crystalline)，并再切换回非晶态。此种存储单元的大致细节公开于上述参考文献中，而相变材料本身的细节则如下所述。
本文将先讨论此存储单元的结构与功能等方面，再接着讨论用其制造方法的过程。此单元优选形成于介电层或基板12之上，此基板优选由二氧化硅或如聚亚酰胺、氮化硅、或其它介电填充材料等的已知的替代物所构成。在各实施例中，此介电层包括相对良好的热与电绝缘层，提供良好的绝热与绝电效果。电接点或栓塞14优选由耐热金属如钨等，而形成于氧化层中。其它耐热金属包括钛(Ti)、钼(Mo)、铝(Al)、钽(Ta)、铜(Cu)、铂(Pt)、铱(Ir)、镧(La)、镍(Ni)、以及钌(Ru)。阻挡材料16形成于氧化层之上，一般用以防止扩散并对在单元中的电场有良好影响，如下所述。此阻挡层优选由氮化钛或类似材料所构成，例如选自下列组群中的一个以上：硅、钛、铝、钽、氮、氧与碳。需要注意的是，仅做为参考，在图示中由下往上的方向称为「垂直」，而侧向方向则称为「横向」或「水平」。此种指代方式无论是在制造或使用上，对于组件的实际物理设置方向并无影响。
相变单元17主要由下相变构件18、核心构件26、以及上相变构件28所组成。一般而言，此上与下相变构件的体积远大于核心构件的体积，且此单元优选以垂直堆叠方式形成，亦即下相变构件位于介电层12之上，核心构件位于下相变构件之上，且上相变构件位于核心构件之上，形成夹层结构。此上与下相变构件的横向面积远大于核心构件的横向面积。本领域技术人员将可在给定特定设计需求时，针对这些参数选择特定数值。
优选由二氧化硅所形成的介电层22分隔此相变构件从核心构件往外延伸的部分。本发明的一个实施例包括在下相变构件上的阻挡金属层20，其夹置于此构件与氧化层之间。另一阻挡金属层24则可能夹置于介电层22以及上相变构件28之间。在一个使用了阻挡层24的实施例中，此阻挡层并未延伸至核心构件26与上相变构件28之间。阻挡金属层的上层则形成了电极层30，其也作为扩散阻挡层。
此存储单元的尺寸如下所述。上与下相变组件的厚度(垂直方向)介于约10nm至约100nm之间，优选为40nm。核心构件26的厚度介于约10nm至约100nm之间，优选为40nm。绝缘层22的厚度与核心层相同。阻挡层16，20，24的厚度介于约5nm至约30nm之间，优选为10nm。电极层30的厚度介于约10nm至约300nm之间，优选为150nm。核心构件26还具有宽度(图1的水平方向)介于约50nm至约300nm之间，优选为150nm。
存储单元的实例包括以相变为基础的存储材料，包括以硫族化物为基础的材料以及其它材料。硫族元素包括下列四元素中的任一个：氧(O)、硫(S)、硒(Se)、以及碲(Te)，形成元素周期表上第VI族的部分。硫族化物包括硫族元素与更为正电性的元素或自由基结合的化合物。硫族化物合金包括将硫族化物与其它物质如过渡金属等结合。硫族化物合金通常包括一个以上选自元素周期表第六栏的元素，例如锗(Ge)以及锡(Sn)。通常，硫族化物合金包括具有下列元素中一个以上的组合：锑(Sb)、镓(Ga)、铟(In)、以及银(Ag)。许多以相变为基础的存储材料已经被描述于技术文件中，包括下列合金：镓/锑、铟/锑、铟/硒、锑/碲、锗/碲、锗/锑/碲、铟/锑/碲、镓/硒/碲、锡/锑/碲、铟/锑/锗、银/铟/锑/碲、锗/锡/锑/碲、锗/锑/硒/碲、以及碲/锗/锑/硫。在锗/锑/碲合金家族中，可以尝试大范围的合金成分。此成分可以下列特征式表示：TeaGebSb100-(a+b)。一位研究员描述了最有用的合金为，在沉积材料中所包含的平均碲浓度远低于70％，典型地低于60％，并在一般型态合金中的碲含量范围从最低23％至最高58％，且优选介于48％至58％的碲含量。锗的浓度约高于5％，且其在材料中的平均范围从最低8％至最高30％，一般低于50％。优选地，锗的浓度范围介于8％至40％。在此成分中所剩下的主要成分则为锑。上述百分比为原子百分比，其所有组成元素总和为100％。(Ovshinky‘112专利，栏10～11)由另一研究者所评估的特殊合金包括Ge2Sb2Te5、GeSb2Te4、以及GeSb4Te7。(Noboru Yamada，”Potential of Ge-Sb-TePhase-change Optical Disks for High-Data-Rate Recording”，SPIEv.3109，pp.28-37(1997))更一般地，过渡金属如铬(Cr)、铁(Fe)、镍(Ni)、铌(Nb)、钯(Pd)、铂(Pt)、以及上述的混合物或合金，可与锗/锑/碲结合以形成相变合金，其包括有可编程的电阻特性。可使用的存储材料的特殊范例，如Ovshinsky‘112专利中栏11-13所述，其范例在此列入参考。
在此存储单元的活性信道区域中，相变合金可在第一结构状态与第二结构状态之间以其局部次序切换，其中第一结构状态一般为非晶固相，而第二结构状态一般为结晶固相。这些合金至少为双稳定态。此词汇「非晶」用以指代相对较无次序的结构，其较单晶更无次序性，而带有可侦测的特征，如较晶态更高的电阻值。此词汇「晶态」用以指代相对较有次序的结构，其较非晶态更有次序，因此包括有可侦测的特征，例如比非晶态更低的电阻值。典型地，相变材料可电切换至完全晶态与完全非晶态之间所有可侦测的不同状态。其它受到非晶态与结晶态的改变而影响的材料特中包括，原子次序、自由电子密度、以及活化能。此材料可切换成为不同的固相、或可切换成为由两种以上固相所形成的混合物，提供从非晶态至晶态之间的灰阶部分。此材料中的电特性也可能随之改变。
相变合金可通过施加电脉冲而从一种相态切换至另一相态。先前观察指出，较短、较大振幅的脉冲倾向于将相变材料的相态改变成大体为非晶态。较长、较低振幅的脉冲倾向于将相变材料的相态改变成大体为晶态。在较短、较大振幅脉冲中的能量够大，因此足以破坏结晶结构的键，同时够短因此可以防止原子再次排列成晶态。在没有不适当实验的情形下，可决定特别适用于特定相变合金的适当脉冲量变分布。在本文的后续部分，此相变材料以GST代称，同时也需了解，还可使用其它类型的相变材料。在本文中所描述的一种适用于PCRAM中的材料，为Ge2Sb2Te5。
可用于本发明其它实施例中的其它可编程的存储材料包括，掺杂N2的GST、GexSby、掺杂银的SbxTey、或其它以不同晶态转换来决定电阻的物质；PrxCayMnO3、PrSrMnO、ZrOx、AlOx、TiOx、NiOx、ZnOx、以铬掺杂的SrZrO3、以铌掺杂的SrZrO3、或其它使用电脉冲以改变电阻状态的物质；TCNQ、PCBM、TCNQ-PCBM、Cu-TCNQ、Ag-TCNQ、C60-TCNQ、以其它物质掺杂的TCNQ、或任何其它聚合物材料，其包括有以电脉冲而控制的双稳定或多稳定电阻态。
如图所示，在两相变构件之间的电场以及电流密度，与在核心构件中的相同数值相较之下是相对较低的。核心构件中较小的横向面积则产生了远高于相变构件中的电流与电场密度，进而导致在核心区域的大幅度压降。因此，与相变构件相较之下，核心将受到较高的加热效果，且事实上相变现象将受限于核心区域。两个相变构件将维持于SET(晶态)状态，因为此两者并未受到足以产生相变的高电流而重置(RESET)。
此外，相变构件的低导热性将减低从核心区域所传导的热量，而有效地增加每单位电流在相变材料中所产生的热量。在核心区域的绝热效果，允许设计存储单元时使其具有较现有技术低的电流，进而缩小存储单元本身的尺寸。
此外，GST材料与金属电极相较之下，具有明显较低的导热性，使得此创新设计具有将热量维持在核心区域的效果，而非将热量导离电极。此有利于以较低电流得到理想的相变结果，进而获得较小的单元尺寸以及较大的组件密度。
从图2中显而易见的是，本发明的一个重要方面为尺寸的相对关系，更明确地为在上、下相变构件28，18与核心构件26之间的宽度相对关系。此核心区域的宽度实质上应该小于上与下构件的宽度，也就是核心构件的宽度优选地至多为上与下构件宽度的一半，最佳地为1/3宽度。
图3A示出了完整的PCRAM单元130，其使用了本发明的相变存储结构。如图所示，PCRAM双单元其包括有两个晶体管及其对应的支撑结构，包括相变构件。使用两个半导体组件以形成存储单元在本领域中是众所周知的，如图所示。可理解的是，半导体可为二极管或类似组件，视特殊应用而可选择适当的组件。此单元形成于半导体基板120之上。如浅槽隔离(STI)电介质(图中未示出)的隔离结构分隔了两列存储单元存取晶体管。此存取晶体管由作为共享源极区域的n型终端126、以及在p型基板120之中作为漏极区域的n型终端125，137所形成。多晶硅字线123，124形成存取晶体管的栅极。介电填充层12(图中仅示出其上半部)形成于多晶硅字线之上。此填充层经图案化，之后则形成包括有栓塞结构14a，14b的导电结构。此导电材料可为钨或其它材料、以及适用于栓塞与线路结构的组合物。此共享源极线128接触此n型终端126源极区域，并沿着此阵列的一列作为共享源极线。栓塞结构14a，14b分别接触至漏极终端125与137。填充层12、共享源极线128、以及栓塞结构14a，14b包括有大致平坦的上表面。
此相变存储单元10的变型，其提供两相变存储单元于单一单位中，可更清楚地见图3B的截面图中。如图所示，相变存储单元10a，10b在单元层131中形成并列的单元，由介电填充块133所分隔。单元层131包括相变存储单元10a与10b以及填充块133，其均形成于基板12之上表面。此填充块133可由与介电层12相同的材料所构成，或以其它此领域中所周知的材料所构成。每一相变单元10a与10b与先前所述的单元10相同。因此，相变单元10a包括阻挡层16a，20a与24a，相变层18a与28a、核心构件26a以及电极构件30a，且相变单元10b包括阻挡层16b，20b与24b、相变层18b，28b、核心构件26b、以及电极构件30b。
介电填充层(未标示)覆盖于单元层131之上。此介电填充层包括二氧化硅、聚亚酰胺、氮化硅、或其它介电填充材料。在实施例中，此填充层的绝热性与绝电性相对良好，因而提供相变单元绝热与绝电的效果。传统电路(未示)加入至电极层30之上，以接收从相变单元10a与10b所输出的信号。
在操作时，经由相变单元10a存取此存储单元，通过施加控制信号至字线123再传送至相变单元10a而完成，其中字线123经由终端125以及栓塞14a而耦接至共同源极线128。相同地，经由相变单元10b以存取此存储单元，通过施加控制信号至字线124而完成。
可以了解的是，许多不同的材料可使用于构建如图1与3B中所示的结构。举例而言，可使用铜金属线。其它类型的金属线如以铝、氮化钛、以及钨为基础的材料也可使用。在所述实施例中的电极材料优选为氮化钛或氮化钽。或者，此电极可为氮化铝钛或氮化铝钽，或进一步举例包括如一个以上选自下列组群的元素：钛(Ti)、钨(W)、钼(Mo)、铝(Al)、钽(Ta)、铜(Cu)、铂(Pt)、铱(Ir)、镧(La)、镍(Ni)、以及钌(Ru)、以及由上述元素所构成的合金。
图4示出内存阵列，其可利用参考图3A与3B所示的方式构建。因此，在图4中的各单元标号，对应图3A与3B中的相对单元。可了解的是，在图4中所示的阵列结构，可利用其它单元结构而完成。在图4中，共同源极线128、字线123以及124大致上平行于Y轴方向。位线141与142大致上平行于X方向。因此，在方块145中的Y-译码器以及字线驱动器，耦接至字线123，124。在方块146中的X-译码器以及一组感测放大器，则耦接至位线141，142。此共同源极线128耦接至存取晶体管150，151，152，153的源极终端。存取晶体管150的栅极则耦接至字线123。存取晶体管151的栅极则耦接至字线124。存取晶体管152的栅极耦接至字线123。存取晶体管153的栅极则耦接至字线124。晶体管150的漏极则耦接至相变存储单元10a的电极构件14，其接着再耦接至电极构件30。相同地，晶体管151的漏极耦接至相变存储单元10b的电极构件，其接着再耦接至电极构件30。电极构件30耦接至位线141。为了图解方便，电极构件30与位线141分别处于不同位置。可了解的是，分离的电极构件可在其它实施例中用作不同存储单元的导桥。存取晶体管152与153在位线142上耦接至对应的存储单元。图中可见，共同源极线128被两列存储单元所共享，其中一列在图中以Y轴方向表示。相同的，电极构件30被同一行中的两存储单元所共享，其中一行在图中以X轴方向表示。
图5是根据本发明实施例的集成电路经简化的方块图。此集成电路75包括以薄膜保险丝相变(thin film fuse phase change)存储单元植入半导体基板上的存储阵列160。行译码器161耦接多个字线162，并横向排列于存储阵列160之中。列译码器163耦接至多个位线164，并纵向排列于存储阵列160中，以读取并编程从阵列160中的多栅极存储单元所传来的数据。地址以总线165传送至行译码器161。在方块166中的感测放大器以及数据输入(data in)结构经由数据总线167而耦接至列译码器163。数据经由数据输入线171而从集成电路75的输入/输出端口、或从集成电路75的其它内部或外部数据来源，传输至方块166中的数据输入结构。在所示的实施例中，其它电路174包含于集成电路上，例如通用的处理器、特定目的应用电路、或组合模块，其可提供由薄膜保险丝相变存储单元阵列所支持的芯片系统功能。数据经由数据输出线172而从方块166中的感测放大器传输至集成电路75上的输入/输出端口，或传输至集成电路75的内部或外部数据目的地。
在此实施例中所使用的控制器，利用偏置排列状态机(biasarrangement state machine)169以控制偏置排列供给电压168，例如读取、编程、抹除、抹除确认与编程确认电压等。此控制器可使用本领域中所公知的特定目的逻辑电路而应用于本发明中。在替代实施例中，此控制器包括通用的处理器，其可实施至相同的集成电路中以执行计算机程序，进而控制此组件的操作。在又一实施例中，使用特殊目的逻辑电路与通用的处理器的组合，而应用至控制器中。
制造本发明的单元设计的工艺，参照图6-10做出详细说明。本领域技术人员当可了解，一般而言使用已知的制造技术，并与在微小纳米尺度范围的需求一致。下列叙述将不重复前述所提及的关于材料等的解释。
图6显示了此制造过程的起始，其中此单元的基底层已经形成。介电层12以已知方式形成，其包括二氧化硅、聚亚酰胺、氮化物或其它已知具有良好绝缘性(电与热)的材料。栓塞14提供了穿过此介电层的电接触，且在实施例中此栓塞为钨。其它耐热金属也可视需要应用于其中。
第一层GST材料的沉积制造过程如图7所示。层薄膜GST材料形成此下相变构件18，覆盖于介电层12之上。在一个实施例里，此下相变构件的厚度为400埃(40nm)。额外氧化层22沉积于此第一GST层之上。此第二氧化层的厚度为此单元的关键尺寸，如下所述。本发明的一个实施例中，包括有厚度约为300埃(30nm)的第二氧化层。优选地，可通过在第一GST层与氧化层之间形成薄阻挡层16，以及分别于氧化层22之上与之下各形成额外的阻挡层20，24，而控制潜在的向GST的扩散。在一个实施例中，此阻挡薄膜的厚度约为100埃(1nm)。
如本领域技术人员所知，任何已知的阻挡金属均可使用于此例中。优选使用氮化钛或氮化钽于此应用中，使用金属阻挡层的另一优点在于，其有助于使电场更平均，而在GST材料中获得可预测的电场与电流分布。
图8示出下一步骤，其中利用已知的光刻技术以沉积图案化的光阻层、各向异性蚀刻步骤以移除阻挡层与氧化层中的材料、以及剥除步骤以移除此光阻图案之后，在第二氧化层与其上的阻挡层的中央形成凹洞25。此蚀刻步骤可经控制(如本领域中所公知的选择性蚀刻或时间控制蚀刻)而停止于氮化钛层20。如下所述，实施例中将蚀刻步骤停止于阻挡层20，而其它实施例中蚀刻则完全穿过此层。图8A示出若蚀刻步骤完全穿过阻挡层20的结果结构。可了解的是，在衡量过控制电场(以阻挡层控制)或消除相变材料的电阻来源两者的优缺点后，才能决定是否蚀刻此部分的阻挡层20，因为阻挡层将在此组件中形成一定量欧姆的电阻。
图9中沉积另一GST材料而形成上相变构件以及核心构件26，两者之上则沉积有上电极层30。上电极层30优选由如氮化钛等阻挡金属所形成，以隔离GST材料的扩散。核心构件的厚度以氧化层22控制，优选为约300埃(30nm)。上相变构件以及上电极的厚度优选沉积至约400埃(40nm)。
图10所示的最终单元结构，可先图案化光阻材料于图9的结构的中央部分、并蚀刻此材料至此图案的两侧而达成，其中优选蚀刻至介电层12。经过考察如热消耗以及电流隔离需求等已知因素后，本领域技术人员可选择此单元的横向尺度以及各单元间的距离。
可了解的是，图3B中所示的两单元结构的制造，完全依照上述方式进行，唯一不同处在于，形成核心构件26a，26b时，需要图案化并形成两凹洞，而非仅一凹洞。本领域技术人员将可清楚地了解此项限制。
虽然本发明已参照优选实施例来加以描述，将要了解的是，本发明创作并未受限于其详细描述的内容。替换及修改已于先前描述中所建议，并且其它替换及修改将可为本领域技术人员所思及。特别是，根据本发明的结构与方法，所有具有实质上相同于本发明的构件结合、达成与本发明实质上相同结果的，皆不脱离本发明的精神和范围。因此，所有此类替换及修改将落在本发明在所附权利要求及其等同所界定的范围之中。任何在前文中提及的专利申请以及印刷文本，均列为本申请的参考。

Claims (20)

1.一种存储元件包括：
第一及第二电极，其垂直地分离并具有相向的接触表面；
相变单元，包括
上相变构件，其具有与所述第一电极形成电接触的接触表面；
下相变构件，其具有与所述第二电极形成电接触的接触表面；
核心构件，其夹置于所述上与下相变构件之间且与所述两者形成电接触；其中
所述相变单元由一种具有至少两种固相的材料所构成；以及
所述上与下相变构件的横向面积大于所述核心构件的横向面积；以及
中间绝缘层，其夹置于所述上与下相变构件之间并邻接至所述核心构件。
2.如权利要求1所述的存储元件，还包括薄膜阻挡金属层，其厚度在5nm到30nm之间，其夹置于所述第二电极与所述下相变构件之间、所述下相变构件与所述中间绝缘层之间、以及所述上相变构件与所述中间绝缘区域之间。
3.如权利要求1所述的存储元件，还包括薄膜阻挡金属层，其厚度在5nm到30nm之间，其夹置于所述第二电极与所述下相变构件之间、所述下相变构件与所述核心构件之间、以及所述上相变构件与所述中间绝缘区域之间。
4.如权利要求1所述的存储元件，其中所述上相变构件、下相变构件、以及核心构件均为薄膜，所述上与下相变构件与所述核心构件的厚度均在10nm到100nm之间。
5.如权利要求1所述的存储元件，其中所述核心构件与所述上相变构件同时形成。
6.如权利要求2所述的存储元件，其中所述阻挡金属层包括选自下列组群中的两个或两个以上所形成的化合物：硅、钛、铝、钽、氮、氧、与碳。
7.如权利要求1所述的存储元件，其中所述材料包括由锗、锑、及碲所组成的化合物。
8.如权利要求1所述的存储元件，其中所述相变单元包括选自下列组群中的两个或两个以上所形成的化合物：锗、锑、碲、铟、钛、镓、铋、锡、铜、钯、铅、银、硫、以及金。
9.如权利要求1所述的存储元件，其中所述第一电极包括选自以下组群的元素：钛、钨、钼、铝、钽、铜、铂、铱、镧、镍、以及钌、以及由上述元素所构成的合金。
10.如权利要求1所述的存储元件，还包括基板，其位于此单元之下，且所述第二电极垂直延伸并穿过所述基板。
11.一种用于构建相变存储单元的方法，包括下列步骤：
设置基板，其具有电极组件，该电极组件垂直延伸并穿过该基板直到其上表面；
沉积具有预定厚度的第一相变材料层于所述基板上；
沉积核心相变材料层于所述第一相变材料层之上，所述核心相变材料层具有预定厚度且其宽度小于所述第一相变材料层的宽度；以及
沉积第二相变材料层于所述核心相变材料层之上，其具有预定厚度且其宽度与所述第一相变材料层相同，其中该第一相变材料层、该核心相变材料层、该第二相变材料层由同种材料构成。
12.如权利要求11所述的方法，还包括下列步骤：
形成绝缘层于所述第一相变材料层之上；
形成凹洞于所述绝缘层中，其完全延伸穿过所述绝缘层；以及
其中所述核心相变材料层沉积步骤以及所述第二相变材料层沉积步骤包括单独沉积第二相变材料层，其具有同时形成的核心构件并自此延伸进入所述绝缘层的凹洞。
13.一种计算机存储阵列，包括：
数据传输线，其用于传输字以及位使能信号至所述阵列；
多个存储单元，每一个所述存储单元包括
至少一存取晶体管；
相变单元，其电接触至所述存取晶体管，所述相变单元包括上相变构件、下相变构件、以及核心构件，该核心构件夹置于所述上与下相变构件之间并与所述两者形成电接触；
其中：
所述相变单元由一种具有至少两种固相的物质所构成；以及
所述上与下相变构件的横向面积系大于所述核心构件的横向面积。
14.如权利要求13所述的存储阵列，还包括薄膜阻挡金属层，其厚度在5nm到30nm之间且与所述上与下相变组件接触。
15.如权利要求13所述的存储阵列，其中所述上相变构件、下相变构件、以及核心构件均为薄膜，所述上与下相变构件与所述核心构件的厚度均在10nm到100nm之间。
16.如权利要求13所述的存储阵列，其中所述核心构件与所述上相变构件同时形成。
17.如权利要求14所述的存储阵列，其中所述阻挡金属层包括选自下列组群中的两个或两个以上所形成的化合物：硅、钛、铝、钽、氮、氧、与碳。
18.如权利要求13所述的存储阵列，其中所述存储材料包括由锗、锑、及碲所组成的化合物。
19.如权利要求13所述的存储阵列，其中所述相变单元包括选自下列组群中的两个或两个以上所形成的化合物：锗、锑、碲、铟、钛、镓、铋、锡、铜、钯、铅、银、硫、以及金。
20.如权利要求13所述的存储阵列，其中每一存储单元包括两个存取晶体管以及两个相变单元，所述两个相变单元彼此相邻。
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