CN100495383C - Three-dimensional multiprocessor system chip - Google Patents
Three-dimensional multiprocessor system chip Download PDFInfo
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- CN100495383C CN100495383C CNB2007101131433A CN200710113143A CN100495383C CN 100495383 C CN100495383 C CN 100495383C CN B2007101131433 A CNB2007101131433 A CN B2007101131433A CN 200710113143 A CN200710113143 A CN 200710113143A CN 100495383 C CN100495383 C CN 100495383C
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Abstract
The present invention relates to a chip of a three-dimensional multiprocessor system and belongs to the technical field of an integrate circuit design and manufacture. The present invention comprises a plurality of processor cores, a plurality of three-dimensional network routers on the chip and a wafer chip of a semiconductor integrate circuit that integrates a plurality of processor cores with a plurality of three-dimensional network routers on the chip. The present invention relates to a manufacturing method for utilizing wafer piles to assemble a three-dimensional integrate circuit and a transmitting method of parallel network data. The present invention has the advantages that: first, the part, whole or three-dimensional data transmissions are respectively accomplished by different channels, and the transmission congestion of the network data on the chip is relieved. Second, the three-dimensional chip structure reduces the chip area of a complicated SLSI (super-large-scale integration) and improves the product yield in the course of production. Third, the length of an interconnection line is shortened, the delay time of signals is reduced, and the system performance is enhanced.
Description
(1) technical field
The present invention relates to a kind of three-dimensional multiprocessor system chip, belong to integrated circuit (IC) design manufacturing technology field.
(2) background technology
Along with the progress of integrated circuit technology level, under the deep submicron process condition, can integrated tens million of gate circuits on the single piece of chip.Integrated a plurality of processors are current and following development of integrated circuits directions on one piece of chip.American I NTEL company in 2007 and AMD have all announced to produce the System on Chip/SoC of four processors.Along with increasing of processor quantity, chip area is increasing, and global wires is more and more longer, makes in the deep-submicron semiconductor technology, and the wiring delay between semiconductor devices is compared with the delay of gate circuit and be can not ignore.The deep submicron integrated circuit arts demand reduces wiring delay, and complicated VLSI (very large scale integrated circuit) need be dwindled chip area, thereby needs the three dimensional integrated circuits chip to address these problems.The three dimensional integrated circuits manufacturing process does not also have the commodity production ability at present in the world.
The appearance of multiprocessor system chip, it is fine to make that the data computation function has showed, but the data communication between processor becomes one of key issue.Many in the world large-scale integrated circuit (IC) design manufacturer generally adopts the on-chip bus structure to the data transmission between a plurality of processors on the sheet.Yet integrated circuit research institution in the world, institution of higher education studies show that the data transmission between a plurality of processors on the sheet, adopt the INTERNET network structure to carry out data transmission, and more for a long time, network structure is than bus structure superior performance in on-chip processor quantity.
The data transmission method of on-chip bus structure is that the method for computer system organization is applied to design of integrated circuit; The shortcoming of on-chip bus structure is: when on-chip processor quantity increases, to the intensified competition of bus resource, form data congestion.In addition, long interconnection line time delay has caused the circuit function disorder.
The data transmission method of internet network structure, the working method of imitation INTERNET is carried out data transmission between a plurality of processors.The shortcoming of internet network structure is: the procotol more complicated, increased the consumption of chip area, and cost rises; The serial data transmission mode can not be given full play to the functionality advantage of System on Chip/SoC simultaneously.
Therefore, need with a kind of new structure organization, the new means of communication to adapt to the needs of multiprocessor system chip data communication.
(3) summary of the invention
For overcoming the defective of prior art, the invention provides a kind of three-dimensional multiprocessor system chip.
A kind of three-dimensional multiprocessor system chip, it is characterized in that it is to be formed by a plurality of VLSI (very large scale integrated circuit) chip stacked wafers, integrated a plurality of processors and a plurality of network on three-dimensional chip router on the VLSI (very large scale integrated circuit) chip wafer, the quantity ratio of processor and network on three-dimensional chip router is 4: 1, link to each other by the network on three-dimensional chip router between the processor, network on three-dimensional chip router between every layer of VLSI (very large scale integrated circuit) chip wafer is linked to each other by the data channel of vertical direction, carries out parallel between wafer layer by the network on three-dimensional chip router, bidirectional data transfers.
Described network on three-dimensional chip router is to be compiled by first in first out row ripple displacement memory buffer, cogradient matrices switch arrays, digital routing decision module and parallel network interface to form; Parallel network interface input port is connected with the cogradient matrices switch arrays; Output interface at storer cogradient matrices switch arrays on one side links to each other with first in first out row ripple displacement memory buffer input interface, the output interface of first in first out row ripple displacement memory buffer is connected with another side cogradient matrices switch arrays, is connected to the parallel network interface by the cogradient matrices switch arrays; Numeral routing decision module comprises header register and Status Flag register, its interface contains the order output interface, header register in the numeral routing decision module links to each other with first in first out row ripple displacement memory buffer with the state incoming line by header data with the Status Flag register, the order output interface of numeral routing decision module and the order of cogradient matrices switch receive decoding module and link to each other, and utilize order to receive the control intention that decoding module is realized digital routing decision module.
Described first in first out row ripple displacement memory buffer is made up of the shift memory of 32 of 10 capacity 4K, data width, and its capacity, data width are variable as required; Per two are combined into a bi-directional shift first in first out row ripple displacement memory buffer, and its input, output interface link to each other with the cogradient matrices switch arrays respectively.
Described two groups of cogradient matrices switch arrays by control command receive decoding module, the bi-directional digital switch arrays are formed; As the director switch of data stream, the outside links to each other with global network, localized network, perpendicular network, and inner input and output with 10 first in first out row ripples displacement memory buffer link to each other; The scale of array switch matrix is 5X5, and eight passages and three-dimensional two passages provide the data stream guiding service on the plane respectively, and parallel matrix switch is controlled by digital routing decision module, two-way simultaneous work.
Described digital routing decision module forms module, data flow con-trol module, first in first out row ripple displacement memory buffer input control module, the first in first out row ripple memory buffer output control module that is shifted by data stream header register, Status Flag register, header coding module, decision-making and forms; The input interface of numeral routing decision module links to each other with status register with header register in the first in first out row ripple displacement memory buffer, and the output interface of digital routing decision module links to each other with the command decoder of cogradient matrices switch; According to the information of data stream header register, compiling decodes data from where, be where; Decision-making forms module and makes control command and new header coded message according to the information of decoded information and Status Flag register.
Described parallel network interface is the data channel of 32 bit widths, comprises local network interface, global network interface and perpendicular network interface, and local network interface links to each other with the processor that closes on, and receives from the data of closing on processor; The global network interface links to each other with the router that closes on, and receives from long-range data; The perpendicular network interface is continuous with the router between different wafer layers, carries out data transmission between wafer layer.
Three dimensional integrated circuits manufacture method involved in the present invention is a kind of stacked wafer assemble method in vertical direction, on existing integrated circuit fabrication process basis, by circuit structure design and stacked wafer assemble method, realizes the manufacturing of three dimensional integrated circuits; Data channel with the vertical direction of digital router on the three-dimensional plate is done physical connection, chip wafer is piled up assemble, and forms three-dimensional multiprocessor system chip.
Data communications method between the related on-chip processor of three-dimensional multiprocessor system chip of the present invention, be different from the bus data communication mode, be different from existing network serial data communication mode, it has adopted a kind of network on three-dimensional chip router as the communication facilities between present multiprocessor, replaced present popular bus structure, be a kind of parallel, have the method data buffering function, bidirectional data transfers.
One of meaning of the present invention is: on existing integrated circuit fabrication process basis, by circuit structure design and stacked wafer assemble method, realize the manufacturing of three dimensional integrated circuits.Secondly, the present invention proposes the data communications equipment between a kind of new processor, a kind of without on-chip bus, method that also can the parallel transmission data has designed a kind of network on three-dimensional chip router that is different from traditional internet network equipment.
Advantage of the present invention is: 1. data transmission is finished by different passages respectively in local, the overall situation, solid, has alleviated the congested of network-on-chip data transmission.2. the three-dimensional chip structure has been dwindled complicated VLSI (very large scale integrated circuit) chip area, has improved the product yield in the production run.3. shorten interconnect length, reduced signal delay time, improved system performance.
(4) description of drawings
Fig. 1 is the structural representation of three-dimensional multiprocessor system chip, is example with two-layer, wherein:
1. processor, 2. local network interface, 3. perpendicular network interface, 4. global network interface,
5. network on three-dimensional chip router, 6. chip wafer (A: the 1st layer crystal circle, B: the 2nd layer crystal circle; )
Data channel between two layers is provided by the network on three-dimensional chip router, simultaneously doublely makes physical connection between wafer layer. This example In, the data channel of the Z direction of 4 network on three-dimensional chip routers provides 4 groups of physics lines, the number of every group of line More than or equal to the data width, if data are 32, can calculate interlayer connecting line is 128.
Provided the signal of three-dimensional multiprocessor system chip interlayer data communication passage and stacked wafer assembling method among the figure. Among the figure Give the data channel 2 of the part communication between adjacent processor and the data channel 4 of global communication. This is one 16 and processes System's chip of device has the network on three-dimensional chip router of parallel bidirectional data communications method as the transfer of data between processor Equipment, they consist of a two-dimentional multiprocessor system chip, are integrated on one piece of semiconductor crystal wafer chip.
Fig. 2 is network on three-dimensional chip router schematic diagram, wherein:
7. matrix switch module 8. digital routing decision module 9. buffered memory modules
10.FIFO I/O control line 11. data flow input information lines 12. router duty input lines
13. 15. decision-makings of order output interface 14. state flag registers form module
16. header register 17. header coding modules 18. control commands receive decoding module
19. parallel network interface 20. data transfer directions signal
Fig. 2 has provided in the plane the three-dimensional router of 4 directions and vertical direction parallel transmission data. Three-dimensional, parallel, two To 3 features that are network-on-chip router.
Provided simultaneously the data transmission method signal of network on three-dimensional chip router among the figure, the capable ripple of data flow moves, header Resolve and rearrange yard in the path, the direction service of data flow, dispatch service, security service etc. are all implemented by the routing decision module controls.
Accompanying drawing is not proportional, and emphasis illustrates principle of the present invention and method. The identical identical circuit mould of numeral among the figure Piece. Described multiprocessor core nuclear is not done restriction to certain a processor.
(5) embodiment
Embodiment
The invention process is for example shown in Fig. 1-2, it is to be piled up by two VLSI (very large scale integrated circuit) chip wafers 6 to form, integrated 16 processors and 4 network on three-dimensional chip router fives on the VLSI (very large scale integrated circuit) chip wafer 6, link to each other by the network on three-dimensional chip router five between the processor, network on three-dimensional chip router five between every layer crystal circle 6 has the data channel by vertical direction to link to each other, and carries out parallel, the bidirectional data transfers of wafer 6 interlayers by the network on three-dimensional chip router five.
Described network on three-dimensional chip router five is to be compiled by first in first out row ripple displacement memory buffer, cogradient matrices switch arrays, digital routing decision module 8 and parallel network interface to form; Parallel network interface input port is connected with the cogradient matrices switch arrays; Output interface at storer cogradient matrices switch arrays on one side links to each other with first in first out row ripple displacement memory buffer input interface, the output interface of first in first out row ripple displacement memory buffer is connected with another side cogradient matrices switch arrays, is connected to the parallel network interface by the cogradient matrices switch arrays; Numeral routing decision module 8 comprises header register 16 and Status Flag register 14, its interface contains order output interface 13, header register 16 in the numeral routing decision module 8 links to each other with first in first out row ripple displacement memory buffer with the state incoming line by header data with Status Flag register 14, the order output interface 13 of numeral routing decision module 8 and the order of cogradient matrices switch receive decoding module 18 and link to each other, and utilize order to receive the control intention that decoding module 18 is realized digital routing decision module 8.
Described first in first out row ripple displacement memory buffer is made up of the shift memory of 32 of 10 capacity 4K, data width, and its capacity, data width are variable as required; Per two are combined into a bi-directional shift first in first out row ripple displacement memory buffer, and its input, output interface link to each other with the cogradient matrices switch arrays respectively.
Described two groups of cogradient matrices switch arrays are made up of control command reception decoding module 18, bi-directional digital switch arrays; As the director switch of data stream, the outside links to each other with global network, localized network, perpendicular network, and inner input and output with 10 first in first out row ripples displacement memory buffer link to each other; The scale of array switch matrix is 5X5, and eight passages and three-dimensional two passages provide the data stream guiding service on the plane respectively, and parallel matrix switch is controlled by digital routing decision module 8, two-way simultaneous work.
Described digital routing decision module 8 forms module 15, data flow con-trol module, first in first out row ripple displacement memory buffer input control module, the first in first out row ripple memory buffer output control module that is shifted by data stream header register 16, Status Flag register 14, header coding module 17, decision-making and forms; The input interface of numeral routing decision module 8 links to each other with status register with header register in the first in first out row ripple displacement memory buffer, and the output interface of digital routing decision module 8 links to each other with the command decoder of cogradient matrices switch; According to the information of data stream header register 16, compiling decodes data from where, be where; Decision-making forms module 15 and makes control command and new header coded message according to the information of decoded information and Status Flag register 14.
Described parallel network interface 19 is data channel of 32 bit widths, comprises local network interface 2, global network interface 4 and perpendicular network interface 3, and local network interface 2 links to each other with the processor that closes on, and receives from the data of closing on processor; Global network interface 4 links to each other with the router that closes on, and receives from long-range data; Perpendicular network interface 3 is continuous with the router between different wafer layers, carries out data transmission between wafer layer.
The three dimensional integrated circuits manufacture method of present embodiment, be that a kind of two wafers 6 in vertical (Z) direction pile up assemble method, on existing integrated circuit fabrication process basis,, realize the manufacturing of three dimensional integrated circuits by circuit structure design and stacked wafer assemble method; Data channel with vertical (Z) direction of digital router five on the three-dimensional plate is done physical connection, wafer 6 chip-stacked assembling, forms three-dimensional multiprocessor system chip.
Data communications method between the related on-chip processor of three-dimensional multiprocessor system chip of the present invention, be different from the bus data communication mode, be different from existing network serial data communication mode, it has adopted a kind of network on three-dimensional chip router five as the communication facilities between present multiprocessor, replaced present popular bus structure, be a kind of parallel, have the method data buffering function, bidirectional data transfers.
The processor 1 of present embodiment adopts the soft processor NIOS of opening, adopts the MCS51 soft nuclear of series or other openings or nonopen processor core equally all within coverage of the present invention.In other words, the present invention is applicable to the processor of various styles, does not lose its patent right because of the change of processor.
Present embodiment adopts two-layer wafer 6 to pile up, and piles up the number of plies and not limited by present embodiment; Integrated 1,4 network on three-dimensional chip router five of 16 processors on the every layer crystal circle 6 among the embodiment, variation, symmetric design or the asymmetrical design of the variation of any processor quantity, router quantity is all in the coverage of this patent.
The network on three-dimensional chip router five of present embodiment has 4 two-way simultaneous data channel at two dimensional surface, 1 two-way simultaneous data channel of vertical direction; 32 of data widths; The change of any number of channels, the conversion of data width does not influence claim of the present invention.
The cogradient matrices switch arrays 7 of embodiments of the invention can carry out 32 bit data and switch synchronously, and be two-way in the 5X5 scale.Matrix size is extendible, can be combined into ultra-large Parallel Digital switch arrays.
The three-dimensional multiprocessor chip of the embodiment of the invention comprises: 1,8 network on three-dimensional chip router fives of 6,32 on-chip processors of two-layer wafer form the vertical data passage 3 of 4 groups of Z directions between wafer layer.Utilize the stacked wafer assemble method, 4 groups of vertical data passages 3 constitute three-dimensional multiprocessor system chip as physical connection.By this example, provided a kind of assembling, manufacture method of three dimensional integrated circuits.
The three-dimensional multiprocessor chip that the embodiment of the invention provides, on two dimensional surface, close processor 1 utilizes the local network interface 2 of network on three-dimensional chip router five to carry out data transmission; The processor of apart from each other carries out the remote data transmission with the global network interface 4 of network on three-dimensional chip router; The processor of different wafer layers utilizes the perpendicular network passage 3 of network on three-dimensional chip router to carry out transmitting between data Layer; This is a kind of network parallel data communications method of going up between a plurality of processors.
Claims (8)
1. three-dimensional multiprocessor system chip, it is characterized in that it is to be formed by a plurality of VLSI (very large scale integrated circuit) chip stacked wafers, integrated a plurality of processors and a plurality of network on three-dimensional chip router on the VLSI (very large scale integrated circuit) chip wafer, the quantity ratio of processor and network on three-dimensional chip router is 4:1, link to each other by the network on three-dimensional chip router between the processor, network on three-dimensional chip router between every layer of VLSI (very large scale integrated circuit) chip wafer is linked to each other by the data channel of vertical direction, carries out parallel between wafer layer by the network on three-dimensional chip router, bidirectional data transfers.
2. three-dimensional multiprocessor system chip as claimed in claim 1 is characterized in that described network on three-dimensional chip router is to be compiled by first in first out row ripple displacement memory buffer, cogradient matrices switch arrays, digital routing decision module and parallel network interface to form; Parallel network interface input port is connected with the cogradient matrices switch arrays; Output interface at storer cogradient matrices switch arrays on one side links to each other with first in first out row ripple displacement memory buffer input interface, the output interface of first in first out row ripple displacement memory buffer is connected with another side cogradient matrices switch arrays, is connected to the parallel network interface by the cogradient matrices switch arrays; Numeral routing decision module comprises header register and Status Flag register, its interface contains the order output interface, header register in the numeral routing decision module links to each other with first in first out row ripple displacement memory buffer with the state incoming line by header data with the Status Flag register, the order output interface of numeral routing decision module and the order of cogradient matrices switch receive decoding module and link to each other, and utilize order to receive the control intention that decoding module is realized digital routing decision module.
3. three-dimensional multiprocessor system chip as claimed in claim 2, it is characterized in that described first in first out row ripple displacement memory buffer is made up of the shift memory of 32 of 10 capacity 4K, data width, its capacity, data width are variable as required; Per two are combined into a bi-directional shift first in first out row ripple displacement memory buffer, and its input, output interface link to each other with the cogradient matrices switch arrays respectively.
4. three-dimensional multiprocessor system chip as claimed in claim 2, it is characterized in that described two groups of cogradient matrices switch arrays by control command receive decoding module, the bi-directional digital switch arrays are formed; As the director switch of data stream, the outside links to each other with global network, localized network, perpendicular network, and inner input and output with 10 first in first out row ripples displacement memory buffer link to each other; The scale of array switch matrix is 5 X 5, and eight passages and three-dimensional two passages provide the data stream guiding service on the plane respectively, and parallel matrix switch is controlled by digital routing decision module, two-way simultaneous work.
5. three-dimensional multiprocessor system chip as claimed in claim 2 is characterized in that described digital routing decision module forms module, data flow con-trol module, first in first out row ripple displacement memory buffer input control module, the first in first out row ripple memory buffer output control module that is shifted by data stream header register, Status Flag register, header coding module, decision-making and forms; The input interface of numeral routing decision module links to each other with status register with header register in the first in first out row ripple displacement memory buffer, and the output interface of digital routing decision module links to each other with the command decoder of cogradient matrices switch; According to the information of data stream header register, compiling decodes data from where, be where; Decision-making forms module and makes control command and new header coded message according to the information of decoded information and Status Flag register.
6. three-dimensional multiprocessor system chip as claimed in claim 2, it is characterized in that described parallel network interface is the data channel of 32 bit widths, comprise local network interface, global network interface and perpendicular network interface, local network interface links to each other with the processor that closes on, and receives from the data of closing on processor; The global network interface links to each other with the router that closes on, and receives from long-range data; The perpendicular network interface is continuous with the router between different wafer layers, carries out data transmission between wafer layer.
7. method of making three-dimensional multiprocessor system chip as claimed in claim 1, it is characterized in that it is a kind of stacked wafer assemble method in vertical direction, on existing integrated circuit fabrication process basis, by circuit structure design and stacked wafer assemble method, realize the manufacturing of three dimensional integrated circuits; Data channel with the vertical direction of network on three-dimensional chip router is done physical connection, chip wafer is piled up assemble, and forms three-dimensional multiprocessor system chip.
8. the data communications method between the three-dimensional multiprocessor system chip in the claim 1 adopts the network on three-dimensional chip router as the communication facilities between processor, be walk abreast, have the method data buffering function, bidirectional data transfers.
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Assignee: Binzhou Dongfang Carpet Co., Ltd. Assignor: Shandong University Contract record no.: 2010370000474 Denomination of invention: Three-dimensional multiprocessor system chip Granted publication date: 20090603 License type: Exclusive License Open date: 20080319 Record date: 20100823 |
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