CN100499102C - Semiconductor package substrate increasing static dissipation capability - Google Patents
Semiconductor package substrate increasing static dissipation capability Download PDFInfo
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- CN100499102C CN100499102C CNB2007100036338A CN200710003633A CN100499102C CN 100499102 C CN100499102 C CN 100499102C CN B2007100036338 A CNB2007100036338 A CN B2007100036338A CN 200710003633 A CN200710003633 A CN 200710003633A CN 100499102 C CN100499102 C CN 100499102C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Abstract
The invention relates to a semiconductor package substrate capable of reinforcing static dissipating ability, comprising a dielectric layer, a plurality of pins, a plurality of first static guide circuits, a plurality of second guide circuits and a solder mask. The first static guide circuits and the second static circuits are formed in a plurality of static dissipating areas of the dielectric layer, the static dissipating areas are in electric insulating neighbored arrangement and are exposed out of the solder mast, further the first static guide circuits are connected with a part of pins, thereby reinforcing the static dissipating ability of the substrate in manufacture procedure.
Description
Technical field
The present invention relates to a kind of conductor package substrate, particularly relate to a kind of conductor package substrate that strengthens static dissipation capability.
Background technology
Object or human body can be because of friction accumulation static in the process of moving, electrostatic potential is suitable height, can reach thousands of volts even volt up to ten thousand, can very seriously damage peripheral electronic component when sparking, promptly " discharge of electricity " similarly also can suffer from the problem of static discharge damage integrated circuit wafer in semiconductor packing process.
As shown in Figure 1, a kind of existing known conductor package substrate 100 is mainly to comprise a dielectric layer 110, a plurality of pin 120 and a welding resisting layer (figure does not draw).Be that definition has a plurality of encapsulation units 111 on this dielectric layer 110.Above-mentioned pin 120 is to be formed in the above-mentioned encapsulation unit 111.This welding resisting layer is the local above-mentioned pin 120 that covers.Two opposite sides at this substrate 100 are chain hole 140 and the both sides bus-bars 150 that are formed with a plurality of equidistant arrangements.Between above-mentioned encapsulation unit 111, be formed with lead ring a 130 (guide ring, or title earth lead), it is to connect to have grounding function in the above-mentioned pin 120 or more weak part pin and the two ends of static opposing are connected to this both sides bus-bar 150, leads the path that electrically contacts that destatics to provide.Yet, above-mentioned lead ring 130 is the elongated vertical bar circuits that are connected to both sides bus-bar 150 for two ends, only can with the mode that direct ground connection is carried out static discharge lead destatic and can't with ion wind electrically in and the mode electrostatic charge that dissipates, so the more weak pin of static opposing is easy impaired and influence the electrical functionality of wafer when only competence exertion effect when bus-bar 150 has ground connection in whole semiconductor packing process, no ground connection.
TaiWan, China letters patent I228819 number " semiconductor packaging structure " discloses a kind of and aforementioned roughly the same conductor package substrate, and the ground mat with conductive protection line electric connection pin has static discharge to cause defeated and dispersed anxiety.
TaiWan, China letters patent I227939 number " film glue brilliant formula (chip on film; COF) encapsulating structure " discloses a kind of semiconductor packaging structure, between wafer and substrate, produce " embedding bury type electric capacity " structure, it is made up of two metal fins, one is located at wafer, and another then is located on the substrate.Therefore, this one " embedding bury type electric capacity " structure is quite special, changed the design architecture of wafer and substrate in the encapsulating products simultaneously, and " embedding bury type electric capacity " structure is hidden between wafer and the substrate, be that electrostatic charge is to be accumulated in covering in the space of can't being eliminated, in encapsulation procedure, do not have obviously and benefit for electrostatic dissipation.
This shows that above-mentioned conventional semiconductor packages substrate obviously still has inconvenience and defective, and demands urgently further being improved in structure and use.In order to solve the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of novel conductor package substrate, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Because the defective that above-mentioned conventional semiconductor packages substrate exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, in the hope of founding a kind of novel conductor package substrate, can improve general conventional semiconductor packages substrate, make it have more practicality.Through constantly research, design, and, create the present invention who has practical value finally through after studying sample and improvement repeatedly.
Summary of the invention
Main purpose of the present invention is, overcome the defective that the conventional semiconductor packages substrate exists, and provide a kind of novel conductor package substrate, technical problem to be solved is in order to address the above problem, utilize potential difference to disperse electric charge, and increase the electrostatic charge dissipation area, the element that reaches the enhancing effect of static dissipation capability in semiconductor packing process and can not change encapsulating products is formed, thereby is suitable for practicality more.
The object of the invention to solve the technical problems realizes by the following technical solutions.A kind of conductor package substrate according to the present invention proposes is characterized in that comprising: a dielectric layer, its surface are that definition has a plurality of encapsulation units and a plurality of electrostatic dissipations district; A plurality of pins, it is to be formed in the above-mentioned encapsulation unit of this dielectric layer; A plurality of first electrostatic guide circuits and a plurality of second electrostatic guide circuit, it is to be formed in the above-mentioned electrostatic dissipation district of this dielectric layer, in each electrostatic dissipation district, have at least one first electrostatic guide circuit and at least one second electrostatic guide circuit, it is to be electric insulation ground disposed adjacent, and these described a plurality of pins in first electrostatic guide circuit coupling part; And a welding resisting layer, it is to be formed on this dielectric layer, covers all described a plurality of pins with the part but appears the above-mentioned first electrostatic guide circuit and the above-mentioned second electrostatic guide circuit.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid conductor package substrate, wherein said these the first electrostatic guide circuits and the adjacent second electrostatic guide circuit are be configured to correspond to each other wavy.
Aforesaid conductor package substrate, wherein said these first electrostatic guide circuits and the adjacent second electrostatic guide circuit are be configured to correspond to each other parallel palisade or pectination shape.
Aforesaid conductor package substrate, wherein said these first electrostatic guide circuits are to be interrupted shape,
Aforesaid conductor package substrate, wherein said these first electrostatic guide circuits are to be no more than 15 microns with the gap of the corresponding second electrostatic guide circuit.
Aforesaid conductor package substrate, the exposed surface of wherein said these first electrostatic guide circuits and the above-mentioned second electrostatic guide circuit is to be formed with electrotinning.
Aforesaid conductor package substrate, wherein said substrate are to be a circuit film.
Aforesaid conductor package substrate, left and right two opposite sides of wherein said substrate are to be formed with a plurality of chains hole.
Aforesaid conductor package substrate, left and right two opposite sides of wherein said substrate are to be formed with one first bus-bar and one second bus-bar respectively.
Aforesaid conductor package substrate, wherein said these first electrostatic guide circuits are to be connected to this first bus-bar.
Aforesaid conductor package substrate, wherein said these second electrostatic guide circuits are to be connected to this second bus-bar.
Aforesaid conductor package substrate, wherein said these electrostatic dissipation districts are that the difference position is between above-mentioned encapsulation unit.
Aforesaid conductor package substrate, wherein said these electrostatic dissipation districts are position at least one sides in the and arranged on left and right sides of above-mentioned encapsulation unit.
Aforesaid conductor package substrate, wherein said welding resisting layer are not to be covered in above-mentioned electrostatic dissipation district.
The present invention compared with prior art has tangible advantage and beneficial effect.By technique scheme, the conductor package substrate that the present invention strengthens static dissipation capability has following advantage at least: utilize potential difference to disperse electric charge, and increase the electrostatic charge dissipation area, the element that reaches the enhancing effect of static dissipation capability in semiconductor packing process and can not change encapsulating products is formed.
In sum, the present invention is relevant a kind of conductor package substrate that strengthens static dissipation capability, is to comprise a dielectric layer, a plurality of pin, a plurality of first electrostatic guide circuit, a plurality of second electrostatic guide circuit and a welding resisting layer.Above-mentioned first electrostatic guide circuit and the above-mentioned second electrostatic guide circuit are to be formed in a plurality of electrostatic dissipations district of this dielectric layer, it is for electric insulation ground disposed adjacent and exposes to this welding resisting layer, and the above-mentioned first electrostatic guide circuit is to connect pin partly, strengthens the static dissipation capability of substrate in the processing procedure by this.The present invention has above-mentioned plurality of advantages and practical value, no matter it all has bigger improvement on product structure or function, obvious improvement is arranged technically, and produced handy and practical effect, and the outstanding effect that has enhancement than the conventional semiconductor packages substrate, thereby being suitable for practicality more, and having the extensive value of industry, really is a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is the end face schematic diagram of existing known conductor package substrate.
Fig. 2 is according to first specific embodiment of the present invention, a kind of end face schematic diagram that strengthens the conductor package substrate of static dissipation capability.
Fig. 3 is according to first specific embodiment of the present invention, the schematic cross-section of this conductor package substrate.
Fig. 4 is according to second specific embodiment of the present invention, the another kind of end face schematic diagram that strengthens the conductor package substrate of static dissipation capability.
Fig. 5 is according to the 3rd specific embodiment of the present invention, the another kind of end face schematic diagram that strengthens the conductor package substrate of static dissipation capability.
Fig. 6 is according to the 4th specific embodiment of the present invention, the another kind of end face schematic diagram that strengthens the conductor package substrate of static dissipation capability.
Fig. 7 is according to the 5th specific embodiment of the present invention, the another kind of end face schematic diagram that strengthens the conductor package substrate of static dissipation capability.
10: wafer 11: projection
100: conductor package substrate 110: dielectric layer
111: encapsulation unit 120: pin
130: lead ring 140: the chain hole
150: bus-bar 200: conductor package substrate
210: dielectric layer 211: encapsulation unit
212: electrostatic dissipation district 220: pin
232: the second electrostatic guide circuits of 231: the first electrostatic guide circuits
240: welding resisting layer 250: electrotinning
260: 271: the first bus-bars in chain hole
271A: 272: the second bus-bars of first bus-bar
272A: second bus-bar 273: through hole
300: conductor package substrate 310: dielectric layer
311: encapsulation unit 312: the electrostatic dissipation district
320: 331: the first electrostatic guide circuits of pin
332: the second electrostatic guide circuits 340: chain hole
352: the second bus-bars of 351: the first bus-bars
362: the second electrostatic guide circuits of 361: the first electrostatic guide circuits
400: conductor package substrate 410: dielectric layer
411: encapsulation unit 412: the electrostatic dissipation district
420: 431: the first electrostatic guide circuits of pin
431A: 432: the second electrostatic guide circuits of the first electrostatic guide circuit
432A: the second electrostatic guide circuit 440: connecting line
452: the second bus-bars of 451: the first bus-bars
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, its embodiment of conductor package substrate, structure, feature and the effect thereof of the enhancing static dissipation capability that foundation the present invention is proposed, describe in detail as after.
According to first specific embodiment of the present invention, disclose a kind of conductor package substrate.As shown in Figures 2 and 3, this conductor package substrate 200 mainly comprises a dielectric layer 210, a plurality of pin 220, a plurality of first electrostatic guide circuit 231, a plurality of second electrostatic guide circuit 232 and a welding resisting layer 240.One surface of this dielectric layer 210 is that definition has a plurality of encapsulation units 211 and a plurality of electrostatic dissipations district 212.After encapsulation procedure, can cut out the semiconductor packaging structure along the periphery of these encapsulation units 211.And these encapsulation units 211 also can be referred to as to use district (use area) usually.Above-mentioned electrostatic dissipation district 212 be the position between above-mentioned encapsulation unit 211 or side, in order to grounding pin or the electrostatic charge of the more weak pin of static opposing is dispersed in these exposes to the outer electrostatic dissipation district 212 of welding resisting layer 240, eliminate static for ion wind.
Above-mentioned pin 220 is to be formed in the above-mentioned encapsulation unit 211 of this dielectric layer 210.The above-mentioned first electrostatic guide circuit 231 and the above-mentioned second electrostatic guide circuit 232, it is to be formed in the above-mentioned electrostatic dissipation district 212 of this dielectric layer 210, have at least one first electrostatic guide circuit 231 and at least one second electrostatic guide circuit 232 in each electrostatic dissipation district 212, it is to be electric insulation ground disposed adjacent.And this first electrostatic guide circuit 231 is to connect pin 220 partly, particularly to more weak pin or the grounding pin of static opposing.And this second electrostatic guide circuit 232 can connect or not connect the part pin 220 (figure does not draw) of another encapsulation unit.
This welding resisting layer 240 is to be formed on this dielectric layer 210, covers above-mentioned pin 220 with the part, but appears the above-mentioned first electrostatic guide circuit 231 and the above-mentioned second electrostatic guide circuit 232.
Preferably, the above-mentioned first electrostatic guide circuit 231 is be configured to correspond to each other wavy with the corresponding second electrostatic guide circuit 232, for example: wavy, wavy, square wave shape of circle or the like, it preferably is the square wave shape, the above-mentioned again first electrostatic guide circuit 231 is for appearing shape with the corresponding second electrostatic guide circuit 232, it can disperse the electrostatic charge of pin in the potential difference mode, and in processing procedure with the ion wind elimination electrostatic charge that neutralizes gradually, eliminate ability with the static of promoting in the whole encapsulation procedure.Particularly, the gap of the above-mentioned first electrostatic guide circuit 231 and the corresponding second electrostatic guide circuit 232 is to be no more than 15 microns, to keep better electrical potential difference effect best.In addition, as shown in Figure 3, the above-mentioned first electrostatic guide circuit 231 is to be formed with electrotinning 250 with the exposed surface of the above-mentioned second electrostatic guide circuit 232, in case oxidation is got rusty.
Moreover, this welding resisting layer 240 is to can be liquid photosensitive welding cover layer (liquid photoimagablesolder mask, LPI), photosensitive cover lay (photoimagable cover layer, PIC) or can be the non-conductive printing ink or the cover layer (cover layer) of general non-photosensitive dielectric material.Wherein, this welding resisting layer 240 is the inner end portion that appear above-mentioned pin 220, projection 11 for a wafer 10 engages (as shown in Figure 3), and this welding resisting layer 240 more appears the outer end portion and the above-mentioned first electrostatic guide circuit 231 and the above-mentioned second electrostatic guide circuit 232 of above-mentioned pin 220.
In the present embodiment, this substrate 200 is to be a circuit film, its be applicable to membrane of flip chip encapsulation (COF, Chip-On-Film) or winding carrying encapsulation (TCP, Tape Carrier Package).As shown in Figure 2, two opposite sides of this substrate 200 are to be formed with a plurality of chains hole 260, for the coil type transmission of this substrate 200.Usually two opposite sides of this substrate 200 are to be formed with one first bus-bar 271 and one second bus-bar 272 respectively, and it is for appearing shape, eliminating area the ground connection approach to be provided and to increase static.Preferably, the above-mentioned first electrostatic guide circuit 231 is to be connected to this first bus-bar 271, so that the above-mentioned first electrostatic guide circuit 231 forms potential difference with the above-mentioned second electrostatic guide circuit 232.In addition, be not limited to, the above-mentioned second electrostatic guide circuit 232 is to be connected to this second bus-bar 272, or can not connect.
In the above-described embodiments, this first electrostatic guide circuit 231 can not need be connected to first bus-bar 271, still can form potential difference with the above-mentioned second electrostatic guide circuit 232, also has identical electrostatic dissipation effect.
This first bus-bar 271 is the through holes 273 with corresponding above-mentioned chain hole 260 with this second bus-bar 272, and its width can be a bit larger tham the width in above-mentioned chain hole 260, and corresponding chain hole 260 and be arranged at two opposite sides of substrate 200.
In the semiconductor packages operation, this substrate 200 is coil type transmission (reel-to-reel), can on existing board, the ion fan be set, when the ion wind of ion fan blows to this substrate 200, nature can blow to above-mentioned electrostatic dissipation district 212 on predetermined transmission path, in air, electrically neutralize,, prevent that the defeated and dispersed phenomenon that the short circuit contact connects from producing to eliminate the electrostatic charge on above-mentioned first electrostatic guide circuit 231 and the above-mentioned second electrostatic guide circuit 232.Therefore, but conductor package substrate particularly suitable of the present invention significantly has the enhancing static dissipation capability at the circuit film of membrane of flip chip encapsulation or winding carrying encapsulation.
In addition, the present invention does not limit to the shape of the first electrostatic guide circuit and the second electrostatic guide circuit.As shown in Figure 4, second embodiment discloses another kind of conductor package substrate 300, mainly comprises a dielectric layer 310, a plurality of pin 320, a plurality of first electrostatic guide circuit 331, a plurality of second electrostatic guide circuit 332 and a welding resisting layer (figure does not draw).The surface of this dielectric layer 310 be definition have a plurality of encapsulation units 311 and a plurality of can the electrostatic dissipation district 312 of position between above-mentioned encapsulation unit 311.
Above-mentioned pin 320 is to be formed in the above-mentioned encapsulation unit 311 of this dielectric layer 310.The above-mentioned first electrostatic guide circuit 331 is to be formed in the above-mentioned electrostatic dissipation district 312 of this dielectric layer 310 with the above-mentioned second electrostatic guide circuit 332, have at least one first electrostatic guide circuit 331 and at least one second electrostatic guide circuit 332 in each electrostatic dissipation district 312, it is to be electric insulation ground disposed adjacent.And this first electrostatic guide circuit 331 is to connect pin 320 partly to expose in the outer electrostatic dissipation district 312 of welding resisting layer to above-mentioned with the electrostatic charge that disperses static to be resisted more weak pin or grounding pin.In the present embodiment, the above-mentioned first electrostatic guide circuit 331 and the corresponding second electrostatic guide circuit 332 are be configured to correspond to each other parallel palisade or pectination shape, using provides and can disperse electrostatic charge and with the dribble electrostatic dissipation district 312 of electrostatic charge of ion fan in the potential difference mode, eliminates ability to promote in processing procedure static.This welding resisting layer is to be formed on this dielectric layer 310, covers above-mentioned pin 320 with the part but appears above-mentioned first electrostatic guide circuit 331 and the above-mentioned second electrostatic guide circuit 332.In the present embodiment, two opposite sides of this substrate 300 also can be formed with a plurality of chains hole 340.Two opposite sides of this substrate 300 are to be formed with one first bus-bar 351 and one second bus-bar 352 respectively, and wherein, the above-mentioned first electrostatic guide circuit 331 is can connect (or not connecting) to this first bus-bar 351; The above-mentioned second electrostatic guide circuit 332 is to be connected to this second bus-bar 352, or does not connect.
The third embodiment of the present invention discloses the semiconductor base plate for packaging in addition, as shown in Figure 5, the main element of this substrate, for example dielectric layer 210, pin 220, the first electrostatic guide circuit 231, the second electrostatic guide circuit 232 and welding resisting layer 240 or the like, all identical with first embodiment, repeat no more.Other includes one first bus-bar 271A and one second bus-bar 272A, and this first bus-bar 271A and the second bus-bar 272A can and be arranged between substrate cochain hole and the encapsulation unit at two opposite sides of this substrate.In addition, the above-mentioned first electrostatic guide circuit 231 can be connected to this first bus-bar 271A and the above-mentioned second electrostatic guide circuit 232 also can be connected to this second bus-bar 272A, so that the potential difference effect of 232 in the first electrostatic guide circuit 231 and the second electrostatic guide circuit to be provided.
The fourth embodiment of the present invention discloses the semiconductor base plate for packaging in addition, and as shown in Figure 6, the main element of this substrate is roughly identical with second embodiment, thus continue to use same reference numbers, as dielectric layer 310, pin 320, chain hole 340 and bus-bar 351 and 352.This substrate includes a plurality of first electrostatic guide circuits 361 and a plurality of second electrostatic guide circuits 362 in addition, it is to be formed in the above-mentioned electrostatic dissipation district 312 of this dielectric layer 310 and to be emerging in outside the welding resisting layer, and 312 positions, above-mentioned electrostatic dissipation district are between encapsulation unit 311.Wherein, in each electrostatic dissipation district 312, have at least one first electrostatic guide circuit 361 and at least one second electrostatic guide circuit 362, it is to be electric insulation ground disposed adjacent, and this first electrostatic guide circuit 361 is that to can be interrupted shape and connect part pin 320, the second electrostatic guide circuits 362 in the encapsulation unit 311 be to be connected at least one bus-bar 351 or/and 352.By this, can promote the static dissipation capability of the signal pin of no ground connection.
The fifth embodiment of the present invention discloses the semiconductor base plate for packaging in addition.As shown in Figure 7, a kind of conductor package substrate 400 is mainly to comprise a dielectric layer 410, a plurality of pin 420, a plurality of first electrostatic guide circuit 431, a plurality of second electrostatic guide circuit 432 and a welding resisting layer (figure does not draw).One surface of this dielectric layer 410 is that definition has a plurality of encapsulation units 411 and a plurality of electrostatic dissipations district 412.Above-mentioned pin 420 is to be formed in the above-mentioned encapsulation unit 411 of this dielectric layer 410.In the present embodiment, above-mentioned electrostatic dissipation district 412 be can the position at least one side of the both sides of above-mentioned encapsulation unit 411.
And, be to have at least one first electrostatic guide circuit 431 and at least one second electrostatic guide circuit 432 in each electrostatic dissipation district 412, it is to be electric insulation ground disposed adjacent.And this first electrostatic guide circuit 431 is to connect pin 420 partly.The above-mentioned first electrostatic guide circuit 431 is to be formed in the above-mentioned electrostatic dissipation district 412 of this dielectric layer 410 with the above-mentioned second electrostatic guide circuit 432, most area of common above-mentioned encapsulation unit 411 is covered by welding resisting layer, but this welding resisting layer is not to be covered in above-mentioned electrostatic dissipation district 412, in order to define the edge in above-mentioned electrostatic dissipation district 412.Therefore, be formed at welding resisting layer on this dielectric layer 410 and be and locally to cover above-mentioned pin 420 but appear the above-mentioned first electrostatic guide circuit 431 and the above-mentioned second electrostatic guide circuit 432, for the effect of electrostatic dissipation.In the present embodiment, this conductor package substrate 400 is to can be a coil type circuit film, can comprise one first bus-bar 451 and one second bus-bar 452 in addition, this first bus-bar 451 and this second bus-bar 452 are to be arranged at two opposite sides of substrate and to have through hole corresponding to substrate two opposite side chain holes, and its width can be a bit larger tham the width in above-mentioned chain hole.
In one embodiment, the above-mentioned first electrostatic guide circuit 431 is can be continuous bend wavy with the above-mentioned second electrostatic guide circuit 432, utilizes at least one connecting line 440 to connect the wherein at least one pin 420 and the first electrostatic guide circuit 431.Wherein, an end of the first electrostatic guide circuit 431 is that an end that can be connected to these first bus-bar, 451, the second electrostatic guide circuits 432 is to connect or to be not attached to this first bus-bar 451.In another embodiment, the first above-mentioned electrostatic guide circuit 431 can be done different variations with the shape of the second electrostatic guide circuit 432, for example the first electrostatic guide circuit 431A and the second electrostatic guide circuit 432A with comb shape and square waveform changes it, the first electrostatic guide circuit 431A is connected to wherein at least one pin 420 with a connecting line 440, the first electrostatic guide circuit 431A and the second electrostatic guide circuit 432A other end is to be connected to second bus-bar 452, to reach the effect of preferable electrostatic dissipation.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (14)
1, a kind of conductor package substrate is characterized in that comprising:
One dielectric layer, its surface are that definition has a plurality of encapsulation units and a plurality of electrostatic dissipations district;
A plurality of pins, it is to be formed in the above-mentioned encapsulation unit of this dielectric layer;
A plurality of first electrostatic guide circuits and a plurality of second electrostatic guide circuit, it is to be formed in the above-mentioned electrostatic dissipation district of this dielectric layer, in each electrostatic dissipation district, have at least one first electrostatic guide circuit and at least one second electrostatic guide circuit, it is to be electric insulation ground disposed adjacent, and these described a plurality of pins in first electrostatic guide circuit coupling part; And
One welding resisting layer, it is to be formed on this dielectric layer, covers all described a plurality of pins with the part but appears the above-mentioned first electrostatic guide circuit and the above-mentioned second electrostatic guide circuit.
2, conductor package substrate according to claim 1 is characterized in that wherein said these the first electrostatic guide circuits and the adjacent second electrostatic guide circuit are be configured to correspond to each other wavy.
3, conductor package substrate according to claim 1 is characterized in that wherein said these the first electrostatic guide circuits and the adjacent second electrostatic guide circuit are be configured to correspond to each other parallel palisade or pectination shape.
4, conductor package substrate according to claim 1 is characterized in that wherein said these first electrostatic guide circuits are to be interrupted shape,
5, conductor package substrate according to claim 1 is characterized in that wherein said these first electrostatic guide circuits are to be no more than 15 microns with the gap of the corresponding second electrostatic guide circuit.
6, conductor package substrate according to claim 1 is characterized in that the exposed surface of wherein said these first electrostatic guide circuits and the above-mentioned second electrostatic guide circuit is to be formed with electrotinning.
7, conductor package substrate according to claim 1 is characterized in that wherein said substrate is to be a circuit film.
8, conductor package substrate according to claim 7, left and right two opposite sides that it is characterized in that wherein said substrate are to be formed with a plurality of chains hole.
9, according to claim 1 or 8 described conductor package substrates, left and right two opposite sides that it is characterized in that wherein said substrate are to be formed with one first bus-bar and one second bus-bar respectively.
10, conductor package substrate according to claim 9 is characterized in that wherein said these first electrostatic guide circuits are to be connected to this first bus-bar.
11, conductor package substrate according to claim 9 is characterized in that wherein said these second electrostatic guide circuits are to be connected to this second bus-bar.
12, conductor package substrate according to claim 1 is characterized in that wherein said these electrostatic dissipation districts are that the difference position is between above-mentioned encapsulation unit.
13, conductor package substrate according to claim 1 is characterized in that wherein said these electrostatic dissipation districts are position at least one sides in the and arranged on left and right sides of above-mentioned encapsulation unit.
14, conductor package substrate according to claim 1 is characterized in that wherein said welding resisting layer is not to be covered in above-mentioned electrostatic dissipation district.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100036338A CN100499102C (en) | 2007-01-18 | 2007-01-18 | Semiconductor package substrate increasing static dissipation capability |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100036338A CN100499102C (en) | 2007-01-18 | 2007-01-18 | Semiconductor package substrate increasing static dissipation capability |
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| CN101226919A CN101226919A (en) | 2008-07-23 |
| CN100499102C true CN100499102C (en) | 2009-06-10 |
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| CN102222662B (en) * | 2011-07-01 | 2013-11-06 | 中国科学院微电子研究所 | Packaging structure for electrostatic protection by using point discharge |
| TWI510150B (en) * | 2014-05-30 | 2015-11-21 | Chipmos Technologies Inc | Flexible circuit board |
| CN113301709A (en) * | 2020-02-24 | 2021-08-24 | 颀邦科技股份有限公司 | Circuit board |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6521981B2 (en) * | 1996-03-22 | 2003-02-18 | Hitachi, Ltd. | Semiconductor device and manufacturing method thereof |
| CN1484306A (en) * | 2002-09-16 | 2004-03-24 | 日月光半导体制造股份有限公司 | Package substrate with electrostatic discharge protection |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6521981B2 (en) * | 1996-03-22 | 2003-02-18 | Hitachi, Ltd. | Semiconductor device and manufacturing method thereof |
| CN1484306A (en) * | 2002-09-16 | 2004-03-24 | 日月光半导体制造股份有限公司 | Package substrate with electrostatic discharge protection |
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| CN101226919A (en) | 2008-07-23 |
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