CN100501926C - A making method of EEPROM for increasing coupling voltage of float grating - Google Patents

Abstract

The invention discloses an EEPROM manufacture method which can increase the floating gate coupling voltage. The method besides includes steps of growing a high voltage oxide film, carrying out channel etching, growing a layer of channel oxides, growing a layer of floating gate polycrystals, growing a ONO, and growing two layers of the polycrystals; the floating gate etching is carried out after growing a layer is carried out and before growing the ONO is carried out. A pattern of the floating gate etching is composed of a cubic block or a plurality of small cubic blocks. Because the invention increases one time floating gate etching and the capacitance of the ONO in a traditional EEPROM manufacture method, that is, the coupling ratio and the coupling voltage of the floating gate are increased, the recordable efficiency of the EEPROM can be enhanced or the recordable voltage is decreased.

Description

A kind of EEPROM manufacture method that increases coupling voltage of float grating

Technical field

The present invention relates to a kind of semiconductor fabrication process, relate in particular to a kind of EEPROM manufacture method that increases coupling voltage of float grating.

Background technology

At present growing along with semiconductor fabrication especially at the design aspect of memory cell, in order to enhance competitiveness, need as much as possible dwindle cellar area, simplifies manufacture craft.In EEPROM (electrically erasable programmable ROM), in order to guarantee the reliability of cell (memory cell of EEPROM), ONO (is oxide-nitride-oxide, oxide-film nitride film oxide-film sandwich structure, ONO mainly is used in EEPROM, FLASH, the DRAM technology as insulating barrier, advantages such as little, the defective of electric leakage is few are arranged) thickness can not reduce a lot, so operating voltage and erasable speed are subjected to certain restriction.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of EEPROM manufacture method that increases coupling voltage of float grating, can improve the erasable efficient of EEPROM or reduce erasable voltage.

For solving the problems of the technologies described above, the inventive method is removed and is comprised sequential steps: growth high pressure oxidation film, carry out channel etching, growth one deck tunnel oxide then, the floating boom polycrystal of growth one deck (floating poly) is outside two layers of polycrystal (Poly2) of growth ONO, growth; Also behind one deck floating poly that grows up, before the ONO that grows up, carry out floating boom (floating gate) etching.The pattern of above-mentioned floating boom etching is a square or is made up of a plurality of blockages.

The present invention is owing to increase a floating gate etching in traditional E EPROM manufacture method, increased the electric capacity of ONO, promptly increase coupling ratio (coupling factor) and the coupled voltages of floating gate, improve erasable efficient or reduce erasable voltage.

Description of drawings

Fig. 1 is traditional concrete schematic diagram of implementing of EEPROM;

Fig. 2 is the schematic diagram of a specific embodiment of the inventive method;

Fig. 3 is the schematic diagram of another specific embodiment of the inventive method;

Fig. 4 is the pattern 1 that carries out the floating boom etching in the inventive method;

Fig. 5 is the pattern 2 that carries out the floating boom etching in the inventive method;

Fig. 6 is the effect contrast figure of the inventive method and conventional method, wherein scheming a is EEPROM storage unit structure normal under the conventional method, figure b is the EEPROM memory cell structure of increase floating boom etching shown in Figure 2, and figure c is the EEPROM memory cell structure of increase floating boom etching shown in Figure 3.

Embodiment

The present invention is further detailed explanation below in conjunction with drawings and the specific embodiments.

As shown in Figure 1, the EEPROM manufacture method flow process for traditional comprises following sequential steps: growth high pressure oxidation film, carry out raceway groove (tunnel) etching then; Growth one deck tunnel oxide (tunneloxide); The floating boom polycrystal of growth one deck (floating poly); Growth ONO; Two layers of polycrystal (Poly2) of growing up etc.

The present invention has then increased the electric capacity that floatinggate etching increases ONO on above-mentioned traditional EEPROM manufacture method flow process, promptly increase floating gate (floating boom) coupled voltages and improve erasable efficient or reduce erasable voltage.The principle of the invention is: realize because the erasable FN of utilization of EEPROM wears then, electric field strength that need be certain (~ 10MV/cm), since reliability (reliability) thus consideration ONO and the thickness of the tunnel oxide attenuate that can not continue again, so under the prerequisite that guarantees erasable efficient, operating voltage also can not reduce.Therefore solution of the present invention is: increase a floating gate etching and increase the ONO area, so electric capacity (the C of ONO _ONO) also increase, and erasable efficient also can increase thereupon, perhaps erasable voltage also can decrease. thereupon

Further describe the present invention below in conjunction with specific embodiment.

Embodiment 1:

As shown in Figure 2, be a specific embodiment of the inventive method.

As Fig. 2, the same with the making of common EEPROM, also the high pressure oxidation film of at first growing up in the present embodiment, carry out the tunnel etching then; The tunnel oxide of one deck 80A again grows up; The floating poly of one deck 1500A again grows up; Present embodiment and conventional method difference have promptly increased by a step this moment, and promptly Floating gate etching is in this example on tunnel window and digs pit; Carry out ONO again and grow up, thickness is 60/60/60A (dust); Carry out Poly2 again and grow up, thickness is 2000A; The manufacture method of following step and common EEPROM is identical.

Embodiment 2:

As shown in Figure 3, be another specific embodiment of the inventive method.

This example is that with most important difference embodiment illustrated in fig. 2 Floating gate etching pattern is different, in the last example on tunnel window, to dig pit, and in this example for keeping the poly on the tunnel window, and the poly on next door is dug up.

Fig. 6 is the effect contrast figure of the inventive method and conventional method, wherein scheming a is EEPROM storage unit structure normal under the conventional method, figure b is the EEPROM memory cell structure of increase floating boom etching shown in Figure 2, and figure c is the EEPROM memory cell structure of increase floating boom etching shown in Figure 3.

Below we come ONO electric capacity and the erasable coupling efficiency of the EEPROM Cell that increases (comprising different floating gate etch patterns) after EEPROM floating gate etching and common manufacturing process are done one relatively.

According to the electric capacity computing formula:

$C_{\mathrm{ono}}={\mathrm{\ϵ\ϵ}}_0\frac{S}{d}$

The area of the EEPROM CELL that we are common is S=1.2*1=1.2um^2

After increasing Floating gate etching, illustrate with taking Fig. 4 pattern to carry out etching here, and the area of EEPROM CELL ONO is

S’＝1.2*1+(0.3+0.2)*2*0.08*6＝1.68um^2

In the top formula 0.08 is after increasing Floatlng gate etching, the degree of depth of Floating gate etching.

After increasing Floating gate etching, the area of ONO and electric capacity are original S '/S=1.34.

We can be drawn by following two formulas by the coupling factor (coupling ratio) of read-write:

$\mathrm{Kw}=\frac{C_{\mathrm{ONO}}}{C_{\mathrm{ONO}}+\mathrm{Cox}+\mathrm{Ctun}}$

$\mathrm{Ke}=1-\frac{\mathrm{Ctun}}{C_{\mathrm{ONO}}+\mathrm{Cox}+\mathrm{Ctun}}$

Below we calculate the variation that increases the couplingratio of read-write after the Floating gate etching, the modal value that more employed parameters are 0.18umEEPROM in the calculating, ONO is 60/60/60A, tunnel oxide thickness 80A, tunnel size (size of read-write window) 0.3um.

By top coupling ratio computing formula, we can draw, Kw and the Ke of common EEPROMCELL (area of ONO is S=1.2um^2) are respectively 0.59 and 0.87, and by increase EEPROM CELL after the Floating gate etching (S '=3um^2) Kw and Ke be respectively 0.68 and 0.89.

Hence one can see that, after Floating gate etching of increase, the coupling factor Kw and the Ke of read-write are a lot of than original raising respectively, so just can be under the constant situation of operating voltage, the voltage that really is coupled on the floating gate will increase, just increased the electric current of F-N, so read-write efficiency also has corresponding raising.

In sum, the inventive method is utilized increased a lithography layer before Floating gate etching, the degree of depth that etching is certain on the cell of EEPROM (this paper does the example explanation with 0.5um), after ONO grows up up like this, the area of ONO will be than original big a lot (2.5 times), the electric capacity of ONO also increases a lot thereupon, and so erasable coupling ratio also can improve accordingly, can improve erasable efficient accordingly or reduce erasable voltage.

Claims (2)

1, a kind of EEPROM manufacture method that increases coupling voltage of float grating comprises following sequential steps: growth high pressure oxidation film, carry out channel etching then to form the read-write window of EEPROM, growth one deck tunnel oxide, the floating boom polycrystal of growth one deck, growth ONO, the two layers of polycrystal of growing up;

It is characterized in that, after carrying out the floating boom polycrystal of described growth one deck, before the ONO that grows up, carry out the floating boom etching, etch away the floating boom polycrystal of one deck of segment thickness.

2, the EEPROM manufacture method that increases coupling voltage of float grating according to claim 1 is characterized in that, the pattern of described floating boom etching is a square or is made up of a plurality of blockages.

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