CN100508184C - Stack type semiconductor packaging structure - Google Patents

Stack type semiconductor packaging structure Download PDF

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Publication number
CN100508184C
CN100508184C CN 200610127544 CN200610127544A CN100508184C CN 100508184 C CN100508184 C CN 100508184C CN 200610127544 CN200610127544 CN 200610127544 CN 200610127544 A CN200610127544 A CN 200610127544A CN 100508184 C CN100508184 C CN 100508184C
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CN
China
Prior art keywords
substrate
semiconductor element
package structure
conductor package
adhesive member
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CN 200610127544
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Chinese (zh)
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CN101145557A (en
Inventor
翁国良
卢勇利
李政颖
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to CN 200610127544 priority Critical patent/CN100508184C/en
Publication of CN101145557A publication Critical patent/CN101145557A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Abstract

A stackable semiconductor package structure is provided, which comprises a first substrate, a semiconductor element, a second substrate, a plurality of first lead wires, a support adhesive member and a first packaging adhesive. The semiconductor element is positioned on the first substrate. The second substrate is positioned above the semiconductor element and has an area larger than the semiconductor element. The first lead wire is electrically connected with the second substrate and the first substrate. The support adhesive member is positioned between the first substrate and the second substrate, to support the second substrate. The first packaging adhesive exposes a part of solder pads of the second substrate. Therefore, during the wire bonding operation, the suspension part of the second substrate doesn't swing and vibrate, and the area of the second substrate can be increased to store more elements. Additionally, the thickness of the second substrate can be reduced to reduce the total thickness of the stackable semiconductor package structure.

Description

Stackable semi-conductor package structure
Technical field
The present invention relates to a kind of Stackable semi-conductor package structure, particularly a kind of Stackable semi-conductor package structure with support adhesive member.
Background technology
Please refer to Fig. 1, show the cross-sectional schematic of existing Stackable semi-conductor package structure.Existing Stackable semi-conductor package structure 1 comprises first substrate 11, chip 12, second substrate 13, plural wires 14 and adhesive material 15.First substrate 11 has first surface 111 and second surface 112.Chip 12 is with on the first surface 111 that covers crystal type and be attached to first substrate 11.Second substrate 13 utilizes mucigel 16 to be attached on the chip 12, and second substrate 13 has first surface 131 and second surface 132, wherein has a plurality of first weld pads 133 and a plurality of second weld pad 134 on the first surface 131.The area of second substrate 13 is with the meeting of the overlooking sight area greater than chip 12, and makes second substrate, 13 some part can extend outside the chip 12, and forms overhanging portion.
Lead 14 is electrically connected the first surface 111 of first weld pad, 133 to first substrates 11 of second substrate 13.Adhesive material 15 coats first surface 111, chip 12, lead 14 and part second substrate 13 of first substrate 11, and exposes second weld pad 134 on the first surface 131 of second substrate 13, and forms sealing opening (Mold Area Opening) 17.Under normal conditions, existing Stackable semi-conductor package structure 1 can repeatedly be put another encapsulating structure 18 or other element again in sealing opening 17, and wherein the soldered ball 181 of encapsulating structure 18 is electrically connected second weld pad 134 of second substrate 13.
The shortcoming of existing Stackable semi-conductor package structure 1 is as follows.At first, because second substrate 13 has overhanging portion, first weld pad 133 is positioned at the periphery (being overhanging portion) of chip 12 relative positions, and the distance definition between the relative position at the edge of first weld pad 133 and chip 12 is unsettled length L 1, show under thickness T the situation 1 three times or more of unsettled length L 1 through experiment greater than second substrate 13, when routing (Wire Bonding) operation, overhanging portion has the situation of rocking or shaking, and is unfavorable for carrying out the routing operation.What is more, when the routing operation, second substrate 13 is subjected to downward stress when too big, can cause second substrate 13 break (crack).Secondly, owing to have and above-mentionedly rock, shake or the situation of breaking, therefore overhanging portion can not be oversize, makes the area of second substrate 13 be restricted, thereby be limited to the arrangement space of second weld pad 134 on the first surface 131 that sealing opening 17 exposes second substrate 13.At last, in order to reduce the above-mentioned situation of rocking, shaking or breaking, the thickness of second substrate 13 can not be too thin, therefore can't effectively reduce the integral thickness of existing Stackable semi-conductor package structure 1.
Therefore, be necessary to provide a kind of Stackable semi-conductor package structure of innovating and having progressive, to address the above problem.
Summary of the invention
Main purpose of the present invention is to provide a kind of Stackable semi-conductor package structure, to address the above problem.
For realizing described purpose, the present invention includes: first substrate, semiconductor element, second substrate, a plurality of first leads, support adhesive member and first adhesive material.First substrate has first surface and second surface.Semiconductor element is positioned at the first surface of first substrate, and is electrically connected to the first surface of first substrate.Second substrate is positioned at the semiconductor element top, second substrate has first surface and second surface, have a plurality of first weld pads and a plurality of second weld pad on the first surface of second substrate, the area of second substrate is greater than the area of semiconductor element, and the formation overhanging portion.First lead is electrically connected the first surface of first weld pad to the first substrate of second substrate.Support adhesive member is positioned between the second surface of the first surface of first substrate and second substrate, to support second substrate.First adhesive material coats first surface, semiconductor element, first lead, support adhesive member and part second substrate of first substrate, and exposes second weld pad on the first surface of second substrate.
A kind of Stackable semi-conductor package structure that the invention provides, when the routing operation, the overhanging portion of second substrate does not have and rocks, shakes or the situation of breaking, and the area of second substrate can strengthen, to place more multicomponent, in addition, the thickness of second substrate can reduce, and then reduces the thickness of Stackable semi-conductor package structure integral body.
The present invention's purpose feature and advantage will be elaborated in conjunction with the accompanying drawings with embodiment.
Description of drawings
Fig. 1 is the cross-sectional schematic of existing Stackable semi-conductor package structure;
Fig. 2 is the cross-sectional schematic of first embodiment of Stackable semi-conductor package structure of the present invention;
Fig. 3 is the schematic top plan view of Stackable semi-conductor package structure under the situation of ignoring first adhesive material of Fig. 2;
Fig. 4 is the cross-sectional schematic along the line 4-4 of Fig. 3;
Fig. 5 is the cross-sectional schematic of second embodiment of Stackable semi-conductor package structure of the present invention;
Fig. 6 is the cross-sectional schematic of the 3rd embodiment of Stackable semi-conductor package structure of the present invention.
Embodiment
Please refer to Fig. 2, be the cross-sectional schematic of first embodiment of Stackable semi-conductor package structure of the present invention.Stackable semi-conductor package structure 2 comprises first substrate 21, semiconductor element 22, second substrate 23, a plurality of first leads 24, support adhesive member 29 and first adhesive material 25.First substrate 21 has first surface 211 and second surface 212.Semiconductor element 22 is positioned at the first surface 211 of first substrate 21, and is electrically connected to the first surface 211 of first substrate 21.In the present embodiment, semiconductor element 22 is a chip, and chip is with on the first surface 211 that covers crystal type and be attached to first substrate 21.
Second substrate 23 utilizes mucigel 26 to be attached on the semiconductor element 22, and second substrate 23 has first surface 231 and second surface 232, wherein has a plurality of first weld pads 233 and a plurality of second weld pad 234 on the first surface 231.The area of second substrate 23 is big in the area of semiconductor element 22 to overlook sight, and makes second substrate, 23 some part can extend outside the semiconductor element 22, and forms overhanging portion.
First lead 24 is electrically connected the first surface 211 of first weld pad, 233 to first substrates 21 of second substrate 23.Support adhesive member 29 is between the second surface 232 of the first surface 211 of first substrate 21 and second substrate 23, to support second substrate 23.First adhesive material 25 coats first surface 211, semiconductor element 22, first lead 24, support adhesive member 29 and part second substrate 23 of first substrate 21, and expose second weld pad 234 on the first surface 231 of second substrate 23, and form a sealing opening 27.Under normal conditions, Stackable semi-conductor package structure 2 can repeatedly be put another encapsulating structure 28 or other element again in sealing opening 27, and wherein the soldered ball 281 of encapsulating structure 28 is electrically connected second weld pad 234 of second substrate 23.
Please refer to Fig. 3, be the schematic top plan view of Stackable semi-conductor package structure under the situation of ignoring first adhesive material of Fig. 2.In the present embodiment, four sides of second substrate 23 all extend outside the semiconductor element 22, yet are understandable that, second substrate 23 also may have only a side, two sides or three sides to extend outside the semiconductor element 22.In the present embodiment, support adhesive member 29 is an annular sidewall, its around the space with ccontaining semiconductor element 22.In other is used, if second substrate 23 only has a side to extend outside the semiconductor element 22, and the formation overhanging portion, then support adhesive member 29 only is the strip sidewall, and between the overhanging portion of the first surface 211 of first substrate 21 and second substrate 23, to support the overhanging portion of second substrate 23.First weld pad 233 is positioned at the periphery (being overhanging portion) of chip 22 relative positions, and the distance definition between the relative position at the edge of first weld pad 233 and chip 22 is unsettled length L 2.In the present embodiment, because the support of support adhesive member 29, even therefore work as under the situation of thickness T more than 2 three times of unsettled length L 2 greater than second substrate 23, when the routing operation, the overhanging portion of second substrate 23 does not have the situation of rocking or shaking.
In the present embodiment, support adhesive member 29 is the 3rd adhesive material, and it forms in pre-filling mould (Pre-molding) mode, and its material can be identical or different with first adhesive material 25.In other was used, support adhesive member 29 formed in a glue mode for the some glue material.
Please refer to Fig. 4, be the cross-sectional schematic of Fig. 3 along line 4-4.In the present embodiment, have a plurality of open-works 291 on the sidewall of support adhesive member 29, be beneficial to flowing of first adhesive material 25.In other was used, open-work 291 ran through the sidewall of support adhesive member 29 from top to bottom, made support adhesive member 29 be made up of a plurality of discontinuous side wall.Similarly, discontinuous side wall is also around the space, with ccontaining semiconductor element 22.
Please refer to Fig. 5, be the cross-sectional schematic of second embodiment of Stackable semi-conductor package structure of the present invention.Stackable semi-conductor package structure 3 comprises first substrate 31, semiconductor element 32, second substrate 33, a plurality of first leads 34, support adhesive member 39 and first adhesive material 35.First substrate 31 has first surface 311 and second surface 312.Semiconductor element 32 is positioned at the first surface 311 of first substrate 31, and is electrically connected to the first surface 311 of first substrate 31.In the present embodiment, semiconductor element 32 is a time encapsulating structure, inferior encapsulating structure comprises chip 321, a plurality of second leads 322 and second adhesive material 323, chip 321 is attached on the first surface 311 of first substrate 31, second lead 322 is electrically connected the first surface 311 of first surface 311, the second sealings 323 coating chips 321, second lead 322 and part first substrate 31 of the chip 321 and first substrate 31.
Second substrate 33 utilizes mucigel 36 to be attached on the semiconductor element 32, and second substrate 33 has first surface 331 and second surface 332, wherein has a plurality of first weld pads 333 and a plurality of second weld pad 334 on the first surface 331.The area of second substrate 33 is big in the area of semiconductor element 32 to overlook sight, and makes second substrate, 33 some part can extend outside the semiconductor element 32, and forms overhanging portion.
First lead 34 is electrically connected the first surface 311 of first weld pad, 333 to first substrates 31 of second substrate 33.Support adhesive member 39 is between the second surface 332 of the first surface 311 of first substrate 31 and second substrate 33, to support second substrate 33.The support adhesive member 39 of present embodiment and the support adhesive member 29 of first embodiment are identical.First adhesive material 35 coats first surface 311, semiconductor element 32, first lead 34, support adhesive member 39 and part second substrate 33 of first substrate 31, and expose second weld pad 334 on the first surface 331 of second substrate 33, and form sealing opening 37.Under normal conditions, Stackable semi-conductor package structure 3 can repeatedly be put another encapsulating structure 38 or other element again in sealing opening 37, and wherein the soldered ball 381 of encapsulating structure 38 is electrically connected second weld pad 334 of second substrate 33.
Please refer to Fig. 6, be the cross-sectional schematic of the 3rd embodiment of Stackable semi-conductor package structure of the present invention.The Stackable semi-conductor package structure 2 (Fig. 2) of the Stackable semi-conductor package structure 5 of present embodiment and first embodiment is roughly the same, and wherein similar elements is given identical numbering.Not the existing together of Stackable semi-conductor package structure 2 (Fig. 2) of the Stackable semi-conductor package structure 5 of present embodiment and first embodiment only is, in the present embodiment, semiconductor element 22 (that is chip) is attached on substrate 21 upper surfaces, and utilizes a plurality of second leads 591 to be electrically connected to substrate 21 upper surfaces.In addition, in the present embodiment, also comprise active member 59 (for example analog chip (Analog)) at least, active member 59 is positioned on the first surface 231 of second substrate 23 and is coated within first adhesive material 25.Be understandable that the Stackable semi-conductor package structure 2 of first embodiment can also comprise active member 59.
The foregoing description only is explanation principle of the present invention and effect thereof, but not in order to restriction the present invention.Therefore, person skilled in the art scholar can make amendment to the foregoing description without prejudice to spirit of the present invention and change.Interest field of the present invention claim as described later is listed.

Claims (10)

1, a kind of Stackable semi-conductor package structure is characterized in that, comprising:
One first substrate has a first surface and a second surface;
Semiconductor element is positioned at the first surface of this first substrate, and is electrically connected to the first surface of this first substrate;
One second substrate, be positioned at this semiconductor element top, this second substrate has a first surface and a second surface, has a plurality of first weld pads and a plurality of second weld pad on the first surface of this second substrate, and the area of this second substrate is greater than the area of this semiconductor element;
A plurality of first leads are electrically connected the first surface of this first weld pad of this second substrate to this first substrate;
One support adhesive member is positioned between the second surface of the first surface of this first substrate and this second substrate, to support this second substrate; And
One first adhesive material coats first surface, this semiconductor element, this first lead, this support adhesive member and this second substrate of part of this first substrate, and exposes this second weld pad on the first surface of this second substrate.
2, Stackable semi-conductor package structure as claimed in claim 1 is characterized in that, described semiconductor element is a chip, and this chip is attached on the first surface of this first substrate, and is electrically connected to the first surface of this first substrate.
3, Stackable semi-conductor package structure as claimed in claim 1, it is characterized in that, described semiconductor element is an encapsulating structure, this time encapsulating structure comprises a chip, a plurality of second leads and one second adhesive material, this chip is attached on the first surface of this first substrate, this second lead is electrically connected the first surface of this chip and this first substrate, the first surface of this this chip of second sealant covers, this second lead and this first substrate of part.
4, Stackable semi-conductor package structure as claimed in claim 1, it is characterized in that, described second substrate extends outside this semiconductor element, and form an overhanging portion, this support adhesive member is between the overhanging portion of the first surface of this first substrate and this second substrate, to support the overhanging portion of this second substrate.
5, Stackable semi-conductor package structure as claimed in claim 1 is characterized in that, described support adhesive member is one the 3rd adhesive material, forms in pre-filling mould mode.
6, Stackable semi-conductor package structure as claimed in claim 1 is characterized in that, described support adhesive member is some glue materials, forms in a glue mode.
7, Stackable semi-conductor package structure as claimed in claim 1 is characterized in that, the sidewall of described support adhesive member one ring-type, around a space, with ccontaining this semiconductor element, have a plurality of open-works on this sidewall, be beneficial to flowing of this first adhesive material.
8, Stackable semi-conductor package structure as claimed in claim 1 is characterized in that, described support adhesive member is made up of a plurality of discontinuous side wall, and this sidewall is around a space, with ccontaining this semiconductor element.
9, Stackable semi-conductor package structure as claimed in claim 1 is characterized in that, further comprises at least one driving component, and this driving component is positioned on the first surface of this second substrate and is coated within this first adhesive material.
10, Stackable semi-conductor package structure as claimed in claim 1 is characterized in that, described first weld pad is positioned at the periphery of this semiconductor element relative position.
CN 200610127544 2006-09-12 2006-09-12 Stack type semiconductor packaging structure Active CN100508184C (en)

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Application Number Priority Date Filing Date Title
CN 200610127544 CN100508184C (en) 2006-09-12 2006-09-12 Stack type semiconductor packaging structure

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Application Number Priority Date Filing Date Title
CN 200610127544 CN100508184C (en) 2006-09-12 2006-09-12 Stack type semiconductor packaging structure

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CN101145557A CN101145557A (en) 2008-03-19
CN100508184C true CN100508184C (en) 2009-07-01

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105280621B (en) * 2014-06-12 2019-03-19 意法半导体(格勒诺布尔2)公司 The stacking and electronic device of IC chip
CN112038299B (en) * 2019-06-04 2022-05-06 胜丽国际股份有限公司 Stacked sensor package structure

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