CN100521090C - 掩模材料转化 - Google Patents

掩模材料转化 Download PDF

Info

Publication number
CN100521090C
CN100521090C CNB200580035659XA CN200580035659A CN100521090C CN 100521090 C CN100521090 C CN 100521090C CN B200580035659X A CNB200580035659X A CN B200580035659XA CN 200580035659 A CN200580035659 A CN 200580035659A CN 100521090 C CN100521090 C CN 100521090C
Authority
CN
China
Prior art keywords
layer
spacer
described method
etching
mask lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CNB200580035659XA
Other languages
English (en)
Other versions
CN101044595A (zh
Inventor
米尔扎夫·K·阿巴切夫
古尔特基·桑赫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of CN101044595A publication Critical patent/CN101044595A/zh
Application granted granted Critical
Publication of CN100521090C publication Critical patent/CN100521090C/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Abstract

掩模图案如间距倍增的隔体的尺寸通过在将它们形成之后，控制在所述图案中的特征的增长得到控制。为了形成间距倍增的隔体(175a)的图案，首先形成芯棒的图案，使其覆盖在半导体衬底(110)上面。然后通过在所述芯棒上面沉积材料的覆盖层，并且从水平面上优先除去隔体材料，在所述芯棒的侧壁上形成隔体。然后选择性除去所述芯棒，从而留下自立的隔体的图案。所述隔体包含已知在氧化之后增加尺寸的材料，如多晶硅和非晶硅。所述隔体被氧化以使它们增长至需要的宽度(95)。在达到所述需要的宽度之后，可以使用隔体(175a)用作掩模以将下层(150)和所述衬底(110)形成图案。有利地，因为通过氧化使所述隔体(175a)增长，所以可以在所述芯棒上面沉积较薄的覆盖层，从而允许沉积更共形的覆盖层并且加宽用于形成隔体的加工窗口。

Description

掩模材料转化
技术领域
总体而言，本发明涉及集成电路制造，更具体而言，涉及掩模技术。
背景技术
在现代电子仪器中，作为包括增加的可携带性、计算能力、存储容量和能量效率的需要的诸多因素的结果，集成电路正在不断降低尺寸。为了促进这种尺寸降低，形成集成电路的组件特征的尺寸如电器件和互连线宽度也在不断降低。
例如，在存储电路或器件如动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)、铁电(FE)存储器等中，降低特征尺寸的趋向是明显的。举例来说，DRAM典型地包含数百万相同的称为存储单元的电路元件。在其最普通的形式中，存储单元典型地由两种电器件组成：存储电容器和存取场效应晶体管。每一个存储单元是可以存储一位(二进制数字)数据的可寻址位置。可以通过晶体管将位写入到单元中，并且通过从参比电极侧感应在存储电极上的电荷进行读取。通过降低组件电器件和接入它们的导线的尺寸，可以降低结合这些特征的存储器的尺寸。另外，通过将更多的存储单元安装到存储器中，可以增加存储容量。
特征尺寸的连续降低对用于形成所述特征的技术寄予更高的要求。例如，通常使用光刻将衬底上的特征如导线形成图案。可以使用间距的概念描述这些特征的尺寸。间距定义为在两个相邻的特征中的相同点之间的距离。这些特征典型地由相邻的特征之间的空间限定，所述空间典型地由一种材料如绝缘体或导体填充。结果，间距可以被视为特征的宽度和隔开该特征与相邻特征的空间的宽度之和。然而，由于如光学和光或辐射波长的因素，每一种光刻技术均具有最小间距，在该最小间距之下，特定的光刻技术不能可靠地形成特征。因此，光刻技术的最小间距可能限制特征尺寸的降低。
“间距加倍”是提出用于将光刻技术的能力扩展到它们的最小间距之外的一种方法。在图1A-1F中说明了这种方法，并且在授予Lowrey等的美国专利5,328,810中描述了这种方法。参考图1A，首先使用光刻在覆盖在消耗性材料层20和衬底30上面的光致抗蚀剂层中形成线10的图案。如图1B所示，然后通过蚀刻步骤(优选为各向异性的)将所述图案转移到层20中，从而形成占位符或者芯棒40。如图1C中所示，可以剥离光致抗蚀剂线10，并且可以各向同性蚀刻芯棒40以增加在相邻芯棒40之间的距离。如图1D所示，随后在芯棒40上沉积材料层50。如图1E所示，然后通过在定向隔体蚀刻中从水平表面70和80优先蚀刻隔体材料，在芯棒40的侧面上形成隔体60，即延伸的或原来形成的从另一种材料的侧壁延伸的材料。如图1F所示，然后除去保留的芯棒40，从而只留下隔体60，隔体60同时担当用于将下层形成图案的蚀刻掩模。因此，在原来包含限定一个特征和一个空间的图案的给定间距的地方，现在相同的宽度包含两个特征和由隔体60限定的两个空间。结果，有效降低了光刻技术所能实现的最小特征尺寸。
应该理解，尽管间距在上述实例中实际上是减半的，但是这种间距的降低常规上称为间距＂加倍＂，或者更普遍地称为间距＂倍增＂。即，常规上通过某个因素的间距＂倍增＂实际上涉及通过该因素降低间距。在此保留常规的术语。
特征的临界尺寸是特征的最小尺寸。对于使用隔体60形成的特征，临界尺寸典型地对应隔体的宽度。而隔体的宽度典型地依赖于层50的厚度90(参见图1D和1E)。因此，将层50典型地形成至对应需要的临界尺寸的厚度90。
隔体60的质量和均匀性直接影响使用隔体作为掩模在衬底30中部分限定的集成电路的质量。然而，在需要的隔体60与芯棒40和/或隔开隔体60的空间相比较宽的地方，观察到得到的隔体60和由隔体60产生的蚀刻掩模可以具有差的均匀性。而这种差的均匀性可能导致将要在衬底中形成的界限不清和不均匀的特征。结果，在衬底中形成的集成电路的电性能可能下降，或者集成电路可能是不可用的。
因此，需要形成具有高度均匀和界限分明的图案的蚀刻掩模的方法，特别是在结合以间距倍增形成的隔体时。
发明内容
根据本发明的一个方面，提供用于制造集成电路的方法。所述方法包括提供具有上覆的掩模层的衬底。所述掩模层包含形成图案的掩模材料和开口。将所述掩模材料氧化，和随后将所述图案转移到所述衬底中。
根据本发明的另一个方面，提供用于形成集成电路的方法。所述方法包括提供在覆盖在衬底上面的掩模层中包含多条掩模线的图案。所述掩模线包含前体材料。通过使所述前体材料进行化学反应以形成占据比所述前体材料更大体积的化合物，使所述掩模线增长至需要的宽度。
根据本发明的另一个方面，提供用于形成集成电路的方法。所述方法包括提供在覆盖在衬底上面的形成图案的掩模层。所述掩模层包含进行化学反应以形成蚀刻阻止材料的前体材料。随后将掩模层中的图案转移到下层中。
根据本发明的再一个方面，提供半导体加工的方法。所述方法包括提供衬底。临时层覆盖在所述衬底上面，并且可光限定层覆盖在所述临时层上面。在所述可光限定层中形成图案，并且将其转移到所述临时层中以在所述临时层中形成多个占位符。在所述多个占位符上沉积隔体材料的覆盖层。从水平表面上选择性除去所述隔体材料。相对于所述隔体材料选择性除去所述占位符。使所述隔体材料膨胀至需要的尺寸。
根据本发明的另一个方面，提供用于形成存储器的方法。所述方法包括通过间距倍增形成多根掩模线。相邻的掩模线通过开口空间相互隔开，和使相邻的掩模线之间的开口空间变窄。
根据本发明的再一个方面，提供用于半导体加工的方法。所述方法包括通过间距倍增形成多根掩模线。通过将材料转化为另一种材料，使形成所述掩模线的材料的体积膨胀至需要的宽度。
附图说明
从优选实施方案的详细描述和附图可以更好地理解本发明，所述附图意在说明而不是限制本发明，并且其中：
图1A-1F是根据现有技术间距倍增方法形成的掩模线的示意性横截面侧视图；
图2是根据本发明的优选实施方案，部分形成的存储器的示意性横截面侧视图；
图3是根据本发明的优选实施方案，图2的部分形成的存储器在可光限定层中形成线之后的示意性横截面侧视图；
图4是根据本发明的优选实施方案，图3的部分形成的存储器在加宽光致抗蚀剂线之间的空间之后的示意性横截面侧视图；
图5是根据本发明的优选实施方案，图6的部分形成的存储器在通过硬质掩模层进行蚀刻之后的示意性横截面侧视图；
图6是根据本发明的优选实施方案，图5的部分形成的存储器在将图案从光致抗蚀剂层和硬质掩模层转移到临时层中之后的示意性横截面侧视图；
图7是根据本发明的优选实施方案，图6的部分形成的存储器在沉积隔体材料的覆盖层之后的示意性横截面侧视图；
图8是根据本发明的优选实施方案，图7的部分形成的存储器在隔体蚀刻之后的示意性横截面侧视图；
图9是根据本发明的优选实施方案，图8的部分形成的存储器在用可除去层进行涂覆之后的示意性横截面侧视图；
图10是根据本发明的优选实施方案，图9的部分形成的存储器在蚀刻所述光致抗蚀剂和硬质掩模层之后的示意性横截面侧视图；
图11是根据本发明的优选实施方案，图10的部分形成的存储器在除去所述光致抗蚀剂和临时层之后的示意性横截面侧视图；
图12是根据本发明的优选实施方案，图11的部分形成的存储器在将隔体增大至需要的宽度之后的示意性横截面侧视图；
图13是根据本发明的优选实施方案，图12的部分形成的存储器在将隔体图案转移到下面的硬质掩模层中之后的示意性横截面侧视图；
图14是根据本发明的优选实施方案，图13的部分形成的存储器在除去所述隔体之后的示意性横截面侧视图；
图15是根据本发明的优选实施方案，具有附加掩模层的图1的部分形成的存储器的示意性横截面侧视图；
图16是根据本发明的优选实施方案，图15的部分形成的存储器在形成隔体之后的示意性横截面侧视图；
图17是根据本发明的优选实施方案，图16的部分形成的存储器在使隔体膨胀之后的示意性横截面侧视图；
图18是根据本发明的优选实施方案，图17的部分形成的存储器在通过硬质掩模层蚀刻之后的示意性横截面侧视图；
图19是根据本发明的优选实施方案，图18的部分形成的存储器在将隔体图案转移到附加掩模层之后的示意性横截面侧视图；
图20是根据本发明的优选实施方案，图6的部分形成的存储器在沉积隔体材料的覆盖层之后的示意性横截面侧视图；
图21是根据本发明的优选实施方案，图20的部分形成的存储器在使所述覆盖层增大至需要的厚度之后的示意性横截面侧视图；和
图22是根据本发明的优选实施方案，图21的部分形成的存储器在除去硬质掩模和临时层之后的示意性横截面侧视图。
具体实施方式
已经发现一些隔体图案的差的质量归因于沉积隔体材料的共形层和/或蚀刻这种材料以形成隔体的困难。因为典型地在复杂的掩模形貌上的隔体材料的覆盖层的垂直延伸部分以外形成隔体，所以所述层的共形性将影响由所述层形成的隔体的均匀性，例如宽度、高度和物理布局。应该理解层越共形，其复制它沉积其上的表面的形状越接近。
然而，因为临界尺寸继续降低，在芯棒之间的空间或开口的纵横比继续降低。这部分归因于需要通过减小在芯棒之间的空间的宽度，将特征更紧密地集中在一起。另外，在转移图案的普通方法中，使隔体和下面的层都暴露于优选蚀刻衬底材料的蚀刻剂。然而，尽管速度较慢，但是所述蚀刻剂还损耗隔体。因此，即使在临界尺寸降低时，隔体的垂直高度也必须保持在允许在所述隔体被蚀刻剂全部损耗之前完成图案转移的水平。
因此，部分由于前体气体扩散到芯棒之间的空间的底部越来越有限，沉积隔体材料的高度共形的层可能愈加困难。因为侧壁填充有隔体材料，所以在沉积的过程中，这种扩散变得越来越有限，从而进一步增加在侧壁之间的空间的纵横比。由于这种原因，与较厚的层相比，更容易和可靠地沉积较薄的层。由于较厚沉积层的差的共形性，由所述层形成的隔体均匀性可能也差。
另外，正是由于对于前体可能难以到达高纵横比的空间的底部，所以一些空间的纵横比也可能限制渗透到那些空间的底部的蚀刻剂的量。因此，当蚀刻隔体材料层的侧面延伸部分以限定单独的隔体时，一些隔体材料可能不适宜地残留在这些空间的底部，从而导致具有宽度与预期宽度不同的底部表面的隔体形成。因此，在沉积以及蚀刻隔体材料层方面的困难使隔体宽度的精确控制变得困难。
有利地，本发明的优选实施方案允许更精确地控制使用掩模图案形成的特征的宽度和均匀性。在优选实施方案中，使用通过随后的处理如氧化，可以使它本身增大至需要的尺寸或临界尺寸的材料，形成掩模图案。然后将所述掩模图案进行膨胀处理以将掩模特征的宽度增加至需要的宽度。然后可以使用刚增大的掩模特征在下层中形成图案。如在此所用，应该理解＂特征＂指在材料中，例如在掩模层或衬底中形成的并且具有不连续边界的任何容积或开口。
优选地，进行增大处理的图案是通过间距倍增形成的隔体的图案。所述隔体优选包含硅，例如多晶硅或非晶硅。所述增大处理可以是导致隔体膨胀的任何处理。在所述隔体包含硅的地方，膨胀处理优选包括隔体的氧化以形成氧化硅。此外，将所述隔体氧化直至它们增长至需要的宽度。在增长至需要的宽度之后，可以使用隔体在下面的层中将特征形成图案。任选地，可以在氧化之后，将隔体修整至需要的临界尺寸。
有利地，通过在形成隔体之后使它们增长至需要的宽度，可以沉积隔体材料的较薄层。通过沉积比需要的临界尺寸另外所需的层更薄的层，层的共形性对沉积和/或蚀刻处理的限度依赖性较小。结果，加宽了用于形成给定的临界尺寸的隔体的加工窗口。
另外，如上所述，将隔体典型地形成至部分受以下需要支配的特定高度：将要通过掩模进行的特定的半导体加工(例如，蚀刻、注入、掺杂、氧化等)和将要暴露在所述加工下的下面的衬底的特定材料。例如，将隔体典型地形成至考虑在随后的下层的蚀刻过程中除去一些材料的高度。有利地，因为在例如氧化的过程中，隔体典型地既在侧面上又垂直增长，所以在将隔体图案转移到下层中时，不太可能将得到的较高隔体蚀刻掉。而且，因为通过隔体蚀刻形成的隔体的初始高度取决于芯棒的高度，所以芯棒的高度可以小于在不将隔体进行后续增大时需要的高度。因此，因为可以降低芯棒的高度，所以也降低在芯棒之间的空间的纵横比，从而进一步放松隔体材料沉积的需要，并且进一步增大加工窗口。
应该理解，部分由于可得到相对于包含多种其它材料，包括金属、氧化物和硅的衬底的选择性蚀刻化学品，硅的氮化物和硅的氧化物特别适合作为用于形成掩模的隔体材料。有利地，将硅隔体转化为氧化硅允许将本发明的优选实施方案容易地插入到各种工艺流程中，特别是对于间距倍增，而无需相当大地改变加工流程。另外，将硅隔体部分转化为氧化硅还允许侵蚀例如碳材料，而不侵蚀氧化硅或剩余的硅的选择性化学品。
现在将参考附图，其中相同的标记全部指相同的部分。应该理解没有必要将图2-22按比例进行绘制。
还应该理解尽管优选实施方案将应用于其中在形成这些部分之后，可能需要增加构成掩模图案的独立部分的尺寸的任何环境中，但是在特别有利的实施方案中，掩模图案包含通过间距倍增形成的隔体。因此，间距倍增的特征优选具有在用于将芯棒形成图案的光刻技术的最小间距以下的间距，所述芯棒用于形成隔体。另外，尽管可以使用优选实施方案形成任何集成电路，但是它们特别有利地用于形成具有电器件的阵列的器件，包括逻辑或栅极阵列以及易失性和非易失性存储器如DRAM、ROM或闪存。
参考图2，提供部分形成的集成电路100。将衬底110安置在各种掩模层120-150之下。如下所述，蚀刻层120-150以形成用于将衬底110形成图案的掩模，从而形成各种特征。
应该理解＂衬底＂可以包括单一材料的层、不同材料的多层、具有不同材料的区域或它们中结构不同的一层或多层等。这些材料可以包括半导体、绝缘体、导体或它们的组合。例如，衬底可以包含掺杂的多晶硅、电器件活性区、硅化物、或金属层如钨、铝或铜层、或它们的组合。因此，下述的掩模特征可以直接对应在衬底中的需要的导电特征如互连的布局。在其它实施方案中，衬底可以是绝缘体，并且掩模特征的位置可以对应需要的绝缘体的位置。
优选基于考虑在此描述的各种图案形成和图案转移步骤的化学品和加工条件，选择覆盖在衬底110上面的层120-150的材料。因为在最顶层可光限定层120和衬底110之间的层起着将从可光限定层120得到的图案转移到衬底110中的作用，所以优选选择在可光限定层120和衬底110之间的层，使得可以将它们相对于其它暴露材料进行选择性蚀刻。应该理解在材料的刻蚀速率比材料周围的刻蚀速率大至少约5倍，优选约10倍并且更优选约20倍时，该材料被认为是选择性或优先刻蚀的。
在举例说明的实施方案中，可光限定层120覆盖在第一硬质掩模，或刻蚀阻止层130上面，所述第一硬质掩模层130覆盖在临时层140上面，所述临时层140覆盖在第二硬质掩模或刻蚀阻止层150上面，所述第二掩模层150覆盖在衬底110上面，所述衬底110将通过例如第二掩模层150进行蚀刻形成图案。
可光限定层120优选由光致抗蚀剂形成，所述光致抗蚀剂包括本领域中已知的任何光致抗蚀剂。例如，所述光致抗蚀剂可以是与157nm、193nm或248nm波长系统、193nm波长浸没系统或电子束系统相容的任何光致抗蚀剂。优选的光致抗蚀剂材料的实例包括氟化氩(ArF)敏感的光致抗蚀剂，即适合与ArF光源一起使用的光致抗蚀剂，和氟化氪(KrF)敏感的光致抗蚀剂，即适合与KrF光源一起使用的光致抗蚀剂。优选将ArF光致抗蚀剂与使用较短波长光，例如193nm的光刻系统一起使用。优选将KrF光致抗蚀剂与较长波长光刻系统，如248nm系统一起使用。
用于第一硬质掩模层130的材料优选包括无机材料，并且示例性材料包括氧化硅(SiO2)、硅或电介质抗反射涂料(DARC)，如富含硅的氧氮化硅。在举例说明的实施方案中，第一硬质掩模层130是电介质抗反射涂层(DARC)。临时层140优选由相对于优选的硬质掩模材料提供很高的刻蚀选择性的无定形碳形成。更优选地，无定形碳是对光高度透明并且进一步改善对准的无定形碳的形式。在A.Helmbold，D.Meissner，Thin Solid Films，283(1996)196-203中可以找到用于形成高透明碳的沉积技术。
因为用于蚀刻光致抗蚀剂的优选化学品还典型地蚀刻显著量的无定形碳，并且因为化学品可用于蚀刻相对于各种非光致抗蚀剂材料具有优异选择性的无定形碳，所以选自这些材料的硬质掩模层130优选隔开层120和140。如上所述，第一硬质掩模层130优选包含相对于无定形碳可以优先除去的氧化硅、硅或DARC。
另外，将DARC用于第一硬质掩模层130对于形成具有接近光刻技术的分辨率极限的间距的图案可以是特别有利的。DARC可以通过使光反射减至最少提高分辨率，从而可以降低光刻可以限定图案边缘的精确度。任选地，除第一硬质掩模层130以外，还可以类似地使用底部抗反射涂层(BARC)(没有显示)以控制光反射。
第二硬质掩模层150优选包含电介质抗反射涂料(DARC)(例如，氧氮化硅)、硅或氧化铝(Al2O3)。另外，还可以任选使用底部抗反射涂层(BARC)(没有显示)控制光反射。在举例说明的实施方案中，第二硬质掩模层150包含Al2O3。
除选择用于各层的适合的材料以外，层120-150的厚度优选根据与在此所述的蚀刻化学品和加工条件的相容性进行选择。例如，在通过选择性蚀刻下面的层，将图案从覆盖层转移到下面的层时，某种程度上将材料从两层中均除去。因此，上层优选足够厚，使其在图案转移过程中不被消耗殆尽。
在举例说明的实施方案中，可光限定层120优选厚度在约100nm和约300nm之间，并且更优选厚度在约150nm和约250之间。第一硬质掩模层130优选厚度在约10nm和约500nm之间，并且更优选厚度在约15nm和约300nm之间。临时层140优选厚度在约100nm和约300nm之间，并且更优选厚度在约100nm和约200nm之间。第二硬质掩模层150优选厚度在约10nm和约50nm之间，并且更优选厚度在约10nm和约30nm之间。
应该理解可以通过本领域技术人员已知的各种方法形成在此所述的各种层。例如，可以使用各种气相沉积方法，如化学气相沉积，以形成硬质掩模层。可以使用旋涂法形成可光限定层。另外，通过使用烃化合物或这些化合物的混合物作为碳前体的化学气相沉积，可以形成无定形碳层。示例性前体包括丙烯、丙炔、丙烷、丁烷、丁烯、丁二烯和乙炔。在于2003年6月3日授予Fairbairn等的美国专利6,573,030 B1中描述了用于形成无定形碳层的适合的方法。
在根据优选实施方案的方法的第一阶段中并且参考图3-11，通过间距倍增形成隔体的图案。
参考图3，在可光限定层120上形成图案，所述图案包含由可光限定材料特征124定界的空间或沟122。可以通过例如光刻形成沟122，其中使层120暴露于通过分划板的辐照中，然后进行显影。在显影之后，保留的可光限定材料，即在举例说明的实施方案中的光致抗蚀剂形成特征，如举例说明的线124(只以横截面显示)。
得到的线124和空间122的间距等于线124的宽度和相邻的空间122的宽度之和。为了将使用这种线124和空间122的图案形成的特征的临界尺寸减至最小，间距优选在或接近用于将可光限定层120形成图案的光刻技术的极限。因此，所述间距可以是光刻技术的最小间距，并且下述隔体图案可以有利地具有在光刻技术的最小间距以下的间距。
如图4所示，可以任选通过蚀刻光致抗蚀剂线124加宽空间122，以形成变化的空间122a和线124a。优选使用各向同性蚀刻，如氧化硫等离子体，例如包含SO2、O2、N2和Ar的等离子体，蚀刻光致抗蚀剂线124。优选选择蚀刻的程度，使得到的空间122a和线124a的宽度基本上等于在后续形成的隔体之间所需的间距，如从下面对图8-10的论述中所理解的。有利地，这种蚀刻允许线124a与使用用于将可光限定层120形成图案的光刻技术所能实现的相比变得更窄。另外，这种蚀刻可以使线124a的边缘变平滑，从而提高那些线124a的均匀性。
优选将在(变化的)可光限定层120中的图案转移到临时层140中以允许隔体材料层170的沉积(图7)。因此，临时层140优选由可以经受下述隔体材料沉积的加工条件的材料形成。在其中隔体材料的沉积与可光限定层120相容的其它实施方案中，可以省略临时层140，并且将隔体材料直接沉积在可光限定层120自身的光限定特征124或变化的光限定特征124a上。
在举例说明的实施方案中，除具有比光致抗蚀剂更高的耐热性以外，优选选择形成临时层140的材料，使得可以相对于隔体175(图8)的材料和下面的蚀刻阻止层150，将它选择性除去。如上所述，层140优选由无定形碳形成。
如图5中所示，首先，优选将在可光限定层120中的图案转移到硬质掩模层130中。尽管在硬质掩模层130薄时，湿法(各向同性)蚀刻也可以是适合的，但是优选使用各向异性蚀刻如使用氟碳等离子体的蚀刻，实现这种转移。优选的氟碳等离子体蚀刻化学品包括CF4、CHF3、CH2F2和CF3H。
如图6中所示，然后优选使用含SO2的等离子体，例如含SO2、O2和Ar的等离子体，将在可光限定层120中的图案转移到临时层140中。有利地，所述含SO2的等离子体可以以比蚀刻硬质掩模层130的速率大20倍以上、更优选大40倍以上的速率蚀刻优选的临时层140的碳。在2004年8月31日提交的Abatchev等的题目为Critical Dimension Control的美国专利申请10/931,772中描述了适合的含SO2的等离子体。应该理解所述含SO2的等离子体可以同时蚀刻临时层140并且还除去可光限定层120。得到的线124b构成将形成隔体175(图8)的图案的占位符或芯棒。
接着，如图7中所示，优选将隔体材料层170在暴露表面上进行共形覆盖沉积，所述暴露表面包括硬质掩模层130、硬质掩模150和临时层140的侧壁。任选地，可以在沉积层170之前除去硬质掩模层130。隔体材料可以是任何这样的材料，所述材料可以作为用于将图案转移到下面的衬底110中的掩模，或者另外可以允许通过形成的掩模加工在下面的结构。所述隔体材料优选：1)可以以良好的阶梯覆盖度进行沉积；2)可以在与临时层140相容的温度进行沉积；3)可以进行进一步加工以增大的它的尺寸；并且4)可以在增大之后，相对于临时层140和在临时层140下面的任何层进行选择性刻蚀。优选的材料包括多晶硅和非晶硅。优选将层170沉积至在约20nm至约60nm且更优选约20nm至约50nm之间的厚度。更优选地，所述阶梯覆盖度是约80％或更大，并且更优选是约90％或更大。
如图8中所示，然后将隔体层170进行各向异性刻蚀以从部分形成的集成电路100的水平表面180除去隔体材料。这种刻蚀也称为隔体刻蚀，可以使用HBr/Cl等离子体进行。所述蚀刻可以包括物理部分并且还优选包括化学部分，例如反应离子蚀刻(RIE)，如Cl2、HBr蚀刻。例如使用LAMTCP9400，在约7-60mTorr的压力下使约0-50sccm Cl2和约0-200sccm HBr流动，其中顶部功率是约300-1000W，并且底部功率是约50-250W，可以进行这种蚀刻。
接着除去硬质掩模层130(在还存在时)和临时层140以留下自立的隔体175(图11)。如图9中所示，因为隔体175可以是薄的，并且因为硬质掩模层130可以由与隔体175类似的材料形成，可以在隔体175上和周围形成空间填充层155以帮助保持隔体175的结构完整性和帮助蚀刻层130和140。优选地，层155包含可以以旋压方法沉积的光致抗蚀剂。在例如其中隔体175足够宽并且可得到适当的蚀刻化学品的其它实施方案中，可以在不沉积层155的情况下除去层130和140。
参考图10，将硬质掩模层130连同空间填充层155的顶部一起通过例如平面化除去。用于蚀刻层130和155的优选化学处理包括两步骤蚀刻：首先使用CF4/He等离子体直至除去层130(图9)，然后使用O2等离子体以将临时层140连同空间填充层155的保留部分一起除去。在图11中显示了得到的结构。备选地，为了在蚀刻的第一部分中除去层130，可以将层130和155进行化学机械抛光。
因此，形成自立的隔体175的图案。用于蚀刻层140和155的优选化学处理包括氧化硫等离子体蚀刻。有利地，与典型用于隔体的材料如硅的氮化物或硅的氧化物相比，硅更容易进行各向同性蚀刻和各向异性蚀刻中的任一种。在一些实施方案中，在隔体蚀刻之后，通过修整隔体175调整隔体175的临界尺寸。
从而，实现了间距倍增。在举例说明的实施方案中，隔体175的间距大致是最初通过光刻形成的光致抗蚀剂线124(图3)的一半。有利地，可以形成具有约100nm或更小的间距的隔体175。应该理解因为在特征或线124b的侧壁上形成隔体175，隔体175通常遵循最初在可光限定层120中形成的特征或线124的图案的轮廓。
接着，在根据优选实施方案的方法的第二阶段中，使隔体175增大，使得它们的宽度对应将在衬底110中形成的特征的需要的临界尺寸。优选地，通过使隔体175反应以形成占据更多空间的新化合物或合金实现这种增大。在举例说明的具有由硅形成的隔体的实施方案中，所述增大处理优选包括隔体的氧化。应该理解如图12中所示，隔体175在被氧化之后增长。隔体175a的尺寸将根据隔体175被氧化的程度变化。因此，优选选择氧化的持续时间和程度，使得隔体175达到需要的宽度95。通过本领域中已知的任何氧化方法，包括热氧化、使用氧自由基或等离子体的氧化等，可以实现隔体175的氧化。在其它实施方案中，可以通过使用本领域中已知的任何氮化方法进行氮化，使隔体175增大。因此，可以形成具有需要的宽度95的隔体175的图案。
应该理解隔体175可以由任何这样的材料形成，所述材料可以进行膨胀，可以进行共形沉积，并且可得到用于其的适当的蚀刻化学品。例如，可以使用钛形成隔体175，并且可以通过氧化或氮化形成TiO2或TiN2使其增大。材料的其它实例包括钽(可以通过氧化或氮化形成氧化坦或氮化钽进行膨胀)和钨(可以通过氧化或氮化形成氧化钨或氮化钨进行膨胀)。
优选地，选择增大的程度，使得将隔体175增大至基本上等于特征所需的临界尺寸的宽度，所述特征如互连、字线、位线、晶体管行或在镶嵌线之间的间隙，它们将使用由隔体175a形成的图案在衬底110中形成图案。例如，根据需要的临界尺寸比没有氧化的隔体175的尺寸只是略大还是大很多，可以将隔体175a氧化至较大或较小的程度。因此，选择加工条件，如持续时间、化学反应性、温度等，以得到隔体膨胀的需要程度。
应该理解隔体175的增长还使隔开那些隔体175的空间变窄。优选地，隔体175是考虑到这种变窄进行定位的。另外，可以通过修整隔体175a，例如，使用各向同性蚀刻，调整隔体175a的临界尺寸。
还应该理解隔体175a本身可以直接用作硬质掩模以将下面的衬底110形成图案。然而，优选地，将隔体175a的图案转移到一个或多个下面的层中，所述下面的层提供比隔体175a更好的相对于衬底110的蚀刻选择性。参考图13，可以将由隔体175a产生的图案转移到第二硬质掩模层150中。优选地，使用BCl3/Cl2等离子体蚀刻，蚀刻第二硬质掩模层150。
参考图14，可以任选在将衬底110形成图案之前除去隔体175a。可以使用湿法蚀刻的方法除去隔体175a。有利地，通过除去隔体175a，减小覆盖在衬底110上面的掩模的纵横比，从而允许蚀刻剂、其它加工化学品更容易到达衬底，因而改善垂直侧壁的成形，或者另外清楚地刻划并且完成加工。
在其它实施方案中，如图15中所示，可以将另外的掩模层160用于难以将衬底110形成图案的图案。这些衬底可以包括例如，需要多次连续蚀刻以形成图案的多层。由于可得到允许相对于多种含硅的衬底材料高度选择除去无定形碳的化学品，另外的掩模层160优选由无定形碳形成。
应该理解可以使用上述步骤形成覆盖在另外的掩模层160上面的隔体175a。参考图16，形成隔体175的图案。如图17中所示，如上所述，然后通过例如氧化使隔体175膨胀至需要的宽度。如图18中所示，然后可以优选使用BCl3/Cl2等离子体蚀刻，将隔体175a的图案转移到第二硬质掩模层150中。如图19中所示，然后，优选通过各向异性蚀刻另外的掩模层160，将图案转移到另外的掩模层160中。优选地，各向异性蚀刻包括使另外的掩模层160暴露于含SO2的等离子体。在其它实施方案中，应该理解，如上面对图14论述的，可以在蚀刻层150之前或在蚀刻衬底110之前除去隔体175。
然后可以通过掩模层160和150以及隔体175a加工衬底110以限定各种特征，例如，晶体管、电容器和/或互连。在衬底110包含不同材料的层时，可以使用一系列不同的化学品，优选为干法湿刻的化学品，以通过不同的层依次进行蚀刻。应该理解，根据使用的一种或多种化学品，可以蚀刻隔体175a和硬质掩模层150。然而，对于常规的蚀刻化学品，特别是用于蚀刻含硅材料的那些，另外的掩模层160的无定形碳有利地提供优异的抵抗力。因此，可以有效地使用另外的掩模层160作为用于通过多个衬底层进行蚀刻，或用于形成高的纵横比的沟的掩模。随后可以除去另外的掩模层160以进一步加工衬底110。
应该理解在此所述的步骤的任何一个中，将图案从第一水平面转移到第二水平面涉及在第二水平面中形成通常与第一水平面上的特征对应的特征。例如，在第二水平面中的线的路径通常遵循在第一水平面上的线的路径，并且在第二水平面上的其它特征的位置对应在第一水平面上的类似特征的位置。然而，从第一水平面到第二水平面，特征的精确形状和尺寸可以变化。例如，依赖于蚀刻化学品和条件，相对于在第一水平面上的图案，可以增大或减小形成转移图案的特征的尺寸和之间的相对间距，但是仍然类似于上述最初的＂图案＂。因此，仍然将转移图案认为是与最初的图案相同的图案。相反，形成在掩模特征周围的隔体可以改变图案。
应该理解，根据优选实施方案形成接触提供许多优点。例如，因为较薄的层比较厚的层更容易进行共形沉积，所以可以以提高的共形性沉积形成隔体的隔体材料的层。结果，隔体可以由这些具有提高的一致性的层形成。此外，这些较薄的层减小衬有隔体材料覆盖层的沟的纵横比，从而允许蚀刻剂更容易渗透到沟的底部，从而便于隔体蚀刻。
还应该理解，举例说明的实施方案的各种变更是可以的。例如，可以使隔体175或175a的间距增加两倍以上。可以通过在隔体175或175a周围形成另外的隔体，然后除去隔体175或175a，然后在先前在隔体175或175a周围的隔体周围形成隔体，等等，可以实现进一步的间距倍增。在Lowrey等的美国专利5,328,810中描述了用于进一步间距倍增的示例性方法。
另外，可以在与隔体175或175a相邻处覆盖或形成用于将不同尺寸的特征形成图案的各种其它图案。例如，可以形成另外的可光限定层，使其覆盖隔体175或175a，然后形成图案以形成其它图案。在如下专利申请中公开了用于形成这些图案的方法：Tran等的美国专利申请10/931,771，题目为Methods for Increasing Photo-Alignment Margins，2004年8月31日提交。
此外，尽管可以将所有隔体175氧化至具有类似的宽度，但是在其它实施方案中，可以只氧化隔体175中的一些。例如，可以通过沉积并且将保护层(可得到用于其的选择性蚀刻化学品)形成图案，然后氧化暴露的隔体，防止一些隔体175被氧化。
另外，根据被转化的材料和转化处理的程度，氧化或随后的化学转化处理可以不可观地增加隔体175的尺寸。在这种情况下，仍然可以使用在此公开的方法将隔体175转化为可得到用于其的高度选择性的蚀刻化学品的材料。由此，转化方法可以有利地将隔体转化为对随后的蚀刻步骤更好的蚀刻阻止层。例如，可以将掩模前体材料转化为硅或金属的氧化物或氮化物，从而相对周围，即下面的材料可以有利地提供良好的蚀刻选择性。
参考图20-22，在使隔体175增大时，应该理解可以在沉积隔体材料之后并且在形成自立的隔体175之前的任何点，通过例如氧化，使隔体175或层170增大。例如，在沉积隔体材料170的覆盖层(图20)之后，如图21中所示，可以使整个覆盖层170膨胀以形成膨胀的覆盖层170a。如上所述，考虑到在随后的隔体蚀刻过程中的任何水平方向的缩小，优选选择膨胀方法，包括加工条件(例如持续时间、化学反应性、温度等)，以使覆盖层170膨胀至与所需临界尺寸对应的所需厚度。因此，膨胀处理可以容许层170只被部分氧化。如图22中所示，在隔体蚀刻之后，可以除去芯棒124b以留下自立的隔体175a。有利地，因为隔体175a比隔体175更厚，可以无需保护性的空间填充层155(图9)，并且可以使用各向同性蚀刻，例如，使用氟碳等离子体蚀刻芯棒124b。
在其它实施方案中，可以在隔体蚀刻之后并且在蚀刻芯棒之前使隔体175膨胀{例如，可以使图8中的隔体175膨胀}。有利地，因为允许隔体175只在一个方向上进行侧向上的增长，所以这种类型的膨胀允许将在独立的多对隔体175之间的距离保持恒定，而减小在一对隔体175的组成隔体之间的距离。然而，如上所述，优选在将隔体175形成为自立的结构之后进行膨胀步骤，以便于蚀刻层170。
而且，尽管通过各种掩模层的＂加工＂优选涉及蚀刻下面的层，但是通过掩模层的加工可以涉及将在掩模层下面的层进行任何半导体制造加工。例如，加工可以涉及通过掩模层且在下面的层上的掺杂、氧化、氮化或沉积材料。
因此，本领域技术人员应该理解，在不偏离本发明的范围的情况下，可以对上述方法和结构进行各种其它的省略、添加和修改。所有这些修改和改变意在落入由后附权利要求限定的本发明的范围内。

Claims (45)

1.一种半导体加工的方法，所述方法包括：
提供用于隔体材料特征的需要的尺寸；
提供衬底，其中临时层覆盖在所述衬底上面，并且可光限定层覆盖在所述临时层上面；
在所述可光限定层中形成图案；
将所述图案转移到所述临时层中以在所述临时层中形成多个占位符；
在所述多个占位符上沉积隔体材料的覆盖层；
从水平表面上选择性除去所述隔体材料；
相对于所述隔体材料蚀刻所述占位符，从而除去所述占位符；和
使所述隔体材料膨胀至所述需要的尺寸。
2.权利要求1所述的方法，其中选择性除去所述占位符形成自立的隔体的图案，并且其中在选择性除去所述占位符之后，进行所述隔体材料的膨胀。
3.权利要求1所述的方法，其中在从水平表面上选择性除去所述隔体材料之前，进行所述隔体材料的膨胀。
4.权利要求1所述的方法，其中在从水平表面上选择性除去所述隔体材料之后，并且在选择性除去所述占位符之前，进行所述隔体材料的膨胀。
5.权利要求1所述的方法，其中所述临时层包含无定形碳。
6.权利要求5所述的方法，其中所述可光限定层包含光致抗蚀剂。
7.权利要求6所述的方法，其中在所述可光限定层中形成图案包括进行光刻，并且随后各向同性蚀刻所述可光限定层。
8.权利要求6所述的方法，其中硬质掩模层隔开所述临时层和所述可光限定层。
9.权利要求8所述的方法，其中所述硬质掩模层包含电介质抗反射涂料。
10.权利要求9所述的方法，其中所述电介质抗反射涂料包含氧氮化硅。
11.权利要求9所述的方法，其中选择性除去所述占位符包括：
在所述隔体材料之上和周围沉积填充材料；
同时蚀刻所述填充材料和所述硬质掩模层；和
随后同时蚀刻所述填充材料和所述临时层。
12.权利要求11所述的方法，其中沉积填充材料包括沉积光致抗蚀剂。
13.权利要求12所述的方法，其中沉积光致抗蚀剂包括进行旋压处理。
14.权利要求11所述的方法，其中同时蚀刻所述填充材料和所述硬质掩模层包括进行CF4/He等离子体蚀刻。
15.权利要求11所述的方法，其中随后同时蚀刻所述填充材料和所述临时层包括进行O2等离子体蚀刻。
16.权利要求1所述的方法，其中沉积隔体材料的覆盖层包括通过化学气相沉积沉积硅层。
17.权利要求16所述的方法，其中使所述隔体材料膨胀包括形成氧化硅。
18.权利要求16所述的方法，其中从水平表面上选择性除去所述隔体材料包括各向异性蚀刻所述硅层。
19.权利要求18所述的方法，其中各向异性蚀刻所述硅层包括使用HBr/Cl2等离子体蚀刻所述硅层。
20.权利要求1所述的方法，其中所述隔体材料选自钛、钽和钨。
21.一种用于形成存储器的方法，所述方法包括：
通过进行间距倍增形成多根掩模线，其中进行间距倍增包括：
形成多根芯棒；
在所述芯棒上面沉积隔体材料的覆盖层；和
各向异性蚀刻隔体材料的所述覆盖层以在所述芯棒的侧壁上形成所述掩模线，其中相邻的掩模线通过开口空间相互隔开；和
使相邻的掩模线之间的所述开口空间变窄。
22.权利要求21所述的方法，其中所述掩模线包含多晶硅或非晶硅。
23.权利要求21所述的方法，其中使所述开口空间变窄包括使所述掩模线反应以形成不同化合物或合金。
24.权利要求23所述的方法，其中使所述掩模线反应包括通过氧化使所述掩模线膨胀。
25.权利要求24所述的方法，其中使所述掩模线反应包括完全氧化所述掩模线。
26.权利要求21所述的方法，所述方法还包括将由所述掩模线形成的图案转移到下层中。
27.权利要求26所述的方法，其中所述下层包含无定形碳。
28.权利要求27所述的方法，其中将所述图案转移到所述无定形碳层中包括将所述图案转移到硬质掩模层中，然后将所述图案从所述硬质掩模层转移到所述无定形碳层中。
29.权利要求28所述的方法，其中将所述图案转移到硬质掩模层中包括使用BCl3/Cl2等离子体蚀刻所述硬质掩模层。
30.权利要求28所述的方法，其中将所述图案从所述硬质掩模层转移到所述无定形碳层中包括使所述无定形碳层暴露于含SO2的等离子体。
31.权利要求28所述的方法，其中所述硬掩模层包含氧化铝。
32.一种用于半导体加工的方法，所述方法包括：
提供用于掩模线的需要的宽度；
通过进行间距倍增形成多根掩模线，其中进行间距倍增包括：
形成多根芯棒；
在所述芯棒上面沉积隔体材料的覆盖层；和
各向异性蚀刻隔体材料的所述覆盖层以在所述芯棒的侧壁上形成所述掩模线；和
通过将材料转化为另一种材料，使形成所述掩模线的材料的体积膨胀至所述需要的宽度。
33.权利要求32所述的方法，其中使形成所述掩模线的材料的体积膨胀包括在通过间距倍增形成多根掩模线的过程中，使隔体材料的覆盖层膨胀。
34.权利要求33所述的方法，所述方法包括：
在各向异性蚀刻隔体材料的所述覆盖层之前，使形成所述掩模线的材料的体积膨胀。
35.权利要求33所述的方法，所述方法包括：
在各向异性蚀刻隔体材料的所述覆盖层之后，使形成所述掩模线的材料的体积膨胀；和
随后，在使形成所述掩模线的材料的体积膨胀之后，相对于所述隔体材料优先除去所述芯棒。
36.权利要求32所述的方法，其中使形成所述掩模线的材料的体积膨胀包括在间距倍增之后，使隔体的图案膨胀。
37.权利要求32所述的方法，其中将材料转化为另一种材料包括氧化形成所述掩模线的所述材料。
38.权利要求32所述的方法，其中将材料转化为另一种材料包括氮化形成所述掩模线的所述材料。
39.权利要求32所述的方法，所述方法还包括通过在所述掩模线之间的开口，使下层暴露于反应物。
40.权利要求39所述的方法，其中所述反应物是蚀刻剂。
41.权利要求40所述的方法，其中使下层暴露包括蚀刻无定形碳。
42.权利要求40所述的方法，其中使下层暴露包括蚀刻导电衬底。
43.权利要求32所述的方法，所述方法还包括在使形成所述掩模线的材料的体积膨胀之后，修整所述掩模线。
44.权利要求32所述的方法，其中所述掩模线包含多晶硅或非晶硅。
45.权利要求32所述的方法，其中所述需要的宽度是在集成电路中的导电互连线的临界尺寸。
CNB200580035659XA 2004-09-01 2005-08-23 掩模材料转化 Active CN100521090C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/932,993 US7910288B2 (en) 2004-09-01 2004-09-01 Mask material conversion
US10/932,993 2004-09-01

Publications (2)

Publication Number Publication Date
CN101044595A CN101044595A (zh) 2007-09-26
CN100521090C true CN100521090C (zh) 2009-07-29

Family

ID=35715387

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB200580035659XA Active CN100521090C (zh) 2004-09-01 2005-08-23 掩模材料转化

Country Status (7)

Country Link
US (3) US7910288B2 (zh)
EP (1) EP1794777B1 (zh)
JP (1) JP4822077B2 (zh)
KR (1) KR100874196B1 (zh)
CN (1) CN100521090C (zh)
TW (1) TWI267904B (zh)
WO (1) WO2006028705A2 (zh)

Families Citing this family (460)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4223348B2 (ja) * 2003-07-31 2009-02-12 Ｔｄｋ株式会社 磁気記録媒体の製造方法及び製造装置
JP2006012332A (ja) * 2004-06-28 2006-01-12 Tdk Corp ドライエッチング方法、磁気記録媒体の製造方法及び磁気記録媒体
US7151040B2 (en) * 2004-08-31 2006-12-19 Micron Technology, Inc. Methods for increasing photo alignment margins
US7910288B2 (en) 2004-09-01 2011-03-22 Micron Technology, Inc. Mask material conversion
US7655387B2 (en) 2004-09-02 2010-02-02 Micron Technology, Inc. Method to align mask patterns
US7115525B2 (en) 2004-09-02 2006-10-03 Micron Technology, Inc. Method for integrated circuit fabrication using pitch multiplication
JP2006186562A (ja) * 2004-12-27 2006-07-13 Sanyo Electric Co Ltd ビデオ信号処理装置
US7604908B2 (en) * 2005-03-09 2009-10-20 Tokyo Electron Limited Fine pattern forming method
US7390746B2 (en) 2005-03-15 2008-06-24 Micron Technology, Inc. Multiple deposition for integration of spacers in pitch multiplication process
US7253118B2 (en) * 2005-03-15 2007-08-07 Micron Technology, Inc. Pitch reduced patterns relative to photolithography features
US7611944B2 (en) 2005-03-28 2009-11-03 Micron Technology, Inc. Integrated circuit fabrication
US7429536B2 (en) 2005-05-23 2008-09-30 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7560390B2 (en) 2005-06-02 2009-07-14 Micron Technology, Inc. Multiple spacer steps for pitch multiplication
US7396781B2 (en) * 2005-06-09 2008-07-08 Micron Technology, Inc. Method and apparatus for adjusting feature size and position
US7541632B2 (en) * 2005-06-14 2009-06-02 Micron Technology, Inc. Relaxed-pitch method of aligning active area to digit line
US7888721B2 (en) 2005-07-06 2011-02-15 Micron Technology, Inc. Surround gate access transistors with grown ultra-thin bodies
US7768051B2 (en) * 2005-07-25 2010-08-03 Micron Technology, Inc. DRAM including a vertical surround gate transistor
US7413981B2 (en) 2005-07-29 2008-08-19 Micron Technology, Inc. Pitch doubled circuit layout
US8123968B2 (en) * 2005-08-25 2012-02-28 Round Rock Research, Llc Multiple deposition for integration of spacers in pitch multiplication process
US7816262B2 (en) 2005-08-30 2010-10-19 Micron Technology, Inc. Method and algorithm for random half pitched interconnect layout with constant spacing
US7696567B2 (en) 2005-08-31 2010-04-13 Micron Technology, Inc Semiconductor memory device
US7829262B2 (en) 2005-08-31 2010-11-09 Micron Technology, Inc. Method of forming pitch multipled contacts
US7393789B2 (en) * 2005-09-01 2008-07-01 Micron Technology, Inc. Protective coating for planarization
US7572572B2 (en) 2005-09-01 2009-08-11 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7759197B2 (en) * 2005-09-01 2010-07-20 Micron Technology, Inc. Method of forming isolated features using pitch multiplication
US7557032B2 (en) * 2005-09-01 2009-07-07 Micron Technology, Inc. Silicided recessed silicon
US7687342B2 (en) * 2005-09-01 2010-03-30 Micron Technology, Inc. Method of manufacturing a memory device
US7776744B2 (en) * 2005-09-01 2010-08-17 Micron Technology, Inc. Pitch multiplication spacers and methods of forming the same
US7416943B2 (en) * 2005-09-01 2008-08-26 Micron Technology, Inc. Peripheral gate stacks and recessed array gates
US7538858B2 (en) * 2006-01-11 2009-05-26 Micron Technology, Inc. Photolithographic systems and methods for producing sub-diffraction-limited features
KR100744683B1 (ko) * 2006-02-27 2007-08-01 주식회사 하이닉스반도체 반도체 소자 제조 방법
US7476933B2 (en) * 2006-03-02 2009-01-13 Micron Technology, Inc. Vertical gated access transistor
US7842558B2 (en) * 2006-03-02 2010-11-30 Micron Technology, Inc. Masking process for simultaneously patterning separate regions
US8734583B2 (en) * 2006-04-04 2014-05-27 Micron Technology, Inc. Grown nanofin transistors
US8354311B2 (en) 2006-04-04 2013-01-15 Micron Technology, Inc. Method for forming nanofin transistors
US7491995B2 (en) 2006-04-04 2009-02-17 Micron Technology, Inc. DRAM with nanofin transistors
US7425491B2 (en) * 2006-04-04 2008-09-16 Micron Technology, Inc. Nanowire transistor with surrounding gate
KR20090007393A (ko) * 2006-04-04 2009-01-16 마이크론 테크놀로지, 인크. 나노핀 터널링 트랜지스터
US7902074B2 (en) 2006-04-07 2011-03-08 Micron Technology, Inc. Simplified pitch doubling process flow
US7572482B2 (en) * 2006-04-14 2009-08-11 Bae Systems Information And Electronic Systems Integration Inc. Photo-patterned carbon electronics
US8003310B2 (en) * 2006-04-24 2011-08-23 Micron Technology, Inc. Masking techniques and templates for dense semiconductor fabrication
US7488685B2 (en) * 2006-04-25 2009-02-10 Micron Technology, Inc. Process for improving critical dimension uniformity of integrated circuit arrays
US7795149B2 (en) 2006-06-01 2010-09-14 Micron Technology, Inc. Masking techniques and contact imprint reticles for dense semiconductor fabrication
US7723009B2 (en) 2006-06-02 2010-05-25 Micron Technology, Inc. Topography based patterning
US8852851B2 (en) 2006-07-10 2014-10-07 Micron Technology, Inc. Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
WO2008015212A1 (en) * 2006-08-02 2008-02-07 Koninklijke Philips Electronics N.V. Novel hard mask structure for patterning features in semiconductor devices
US7611980B2 (en) * 2006-08-30 2009-11-03 Micron Technology, Inc. Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
US7959818B2 (en) * 2006-09-12 2011-06-14 Hynix Semiconductor Inc. Method for forming a fine pattern of a semiconductor device
US7666578B2 (en) 2006-09-14 2010-02-23 Micron Technology, Inc. Efficient pitch multiplication process
US8129289B2 (en) * 2006-10-05 2012-03-06 Micron Technology, Inc. Method to deposit conformal low temperature SiO2
KR100816753B1 (ko) * 2006-10-09 2008-03-25 삼성전자주식회사 반도체 소자의 형성방법
KR100752674B1 (ko) * 2006-10-17 2007-08-29 삼성전자주식회사 미세 피치의 하드마스크 패턴 형성 방법 및 이를 이용한반도체 소자의 미세 패턴 형성 방법
TWI334163B (en) 2007-03-30 2010-12-01 Nanya Technology Corp Method of pattern transfer
US7807578B2 (en) * 2007-06-01 2010-10-05 Applied Materials, Inc. Frequency doubling using spacer mask
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
KR100934981B1 (ko) * 2007-06-11 2010-01-06 주식회사 하이닉스반도체 반도체 소자의 미세 패턴 형성 방법
US8980756B2 (en) 2007-07-30 2015-03-17 Micron Technology, Inc. Methods for device fabrication using pitch reduction
US8563229B2 (en) * 2007-07-31 2013-10-22 Micron Technology, Inc. Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures
US8283258B2 (en) * 2007-08-16 2012-10-09 Micron Technology, Inc. Selective wet etching of hafnium aluminum oxide films
KR100905157B1 (ko) * 2007-09-18 2009-06-29 주식회사 하이닉스반도체 반도체 소자의 미세 패턴 형성 방법
JP4976977B2 (ja) * 2007-10-17 2012-07-18 株式会社東芝 半導体装置の製造方法
US7737039B2 (en) 2007-11-01 2010-06-15 Micron Technology, Inc. Spacer process for on pitch contacts and related structures
US8048616B2 (en) * 2008-03-12 2011-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Double patterning strategy for contact hole and trench in photolithography
US7659208B2 (en) 2007-12-06 2010-02-09 Micron Technology, Inc Method for forming high density patterns
US7790531B2 (en) 2007-12-18 2010-09-07 Micron Technology, Inc. Methods for isolating portions of a loop of pitch-multiplied material and related structures
JP2009206394A (ja) * 2008-02-29 2009-09-10 Nippon Zeon Co Ltd 炭素系ハードマスクの形成方法
US8030218B2 (en) 2008-03-21 2011-10-04 Micron Technology, Inc. Method for selectively modifying spacing between pitch multiplied structures
KR20090110172A (ko) * 2008-04-17 2009-10-21 삼성전자주식회사 반도체 소자의 미세 패턴 형성 방법
US7989307B2 (en) 2008-05-05 2011-08-02 Micron Technology, Inc. Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and semiconductor structures including the same
TWI426543B (zh) * 2008-05-13 2014-02-11 Macronix Int Co Ltd 積體電路製程中縮小間距的方法
US10151981B2 (en) 2008-05-22 2018-12-11 Micron Technology, Inc. Methods of forming structures supported by semiconductor substrates
JP2009289974A (ja) * 2008-05-29 2009-12-10 Toshiba Corp 半導体装置の製造方法
US20090311634A1 (en) * 2008-06-11 2009-12-17 Tokyo Electron Limited Method of double patterning using sacrificial structure
US8076208B2 (en) 2008-07-03 2011-12-13 Micron Technology, Inc. Method for forming transistor with high breakdown voltage using pitch multiplication technique
US8101497B2 (en) 2008-09-11 2012-01-24 Micron Technology, Inc. Self-aligned trench formation
JP2010087300A (ja) * 2008-09-30 2010-04-15 Toshiba Corp 半導体装置の製造方法
US10378106B2 (en) 2008-11-14 2019-08-13 Asm Ip Holding B.V. Method of forming insulation film by modified PEALD
US8492282B2 (en) * 2008-11-24 2013-07-23 Micron Technology, Inc. Methods of forming a masking pattern for integrated circuits
US8273634B2 (en) * 2008-12-04 2012-09-25 Micron Technology, Inc. Methods of fabricating substrates
US8247302B2 (en) * 2008-12-04 2012-08-21 Micron Technology, Inc. Methods of fabricating substrates
US8796155B2 (en) * 2008-12-04 2014-08-05 Micron Technology, Inc. Methods of fabricating substrates
KR20100069954A (ko) * 2008-12-17 2010-06-25 삼성전자주식회사 미세 패턴 형성 방법 및 이를 이용한 트랜지스터 제조 방법
US7829466B2 (en) * 2009-02-04 2010-11-09 GlobalFoundries, Inc. Methods for fabricating FinFET structures having different channel lengths
JP5238556B2 (ja) * 2009-03-10 2013-07-17 東京エレクトロン株式会社 基板処理方法
US8268543B2 (en) * 2009-03-23 2012-09-18 Micron Technology, Inc. Methods of forming patterns on substrates
US9394608B2 (en) 2009-04-06 2016-07-19 Asm America, Inc. Semiconductor processing reactor and components thereof
US9330934B2 (en) * 2009-05-18 2016-05-03 Micron Technology, Inc. Methods of forming patterns on substrates
US8802201B2 (en) 2009-08-14 2014-08-12 Asm America, Inc. Systems and methods for thin-film deposition of metal oxides using excited nitrogen-oxygen species
US20110129991A1 (en) * 2009-12-02 2011-06-02 Kyle Armstrong Methods Of Patterning Materials, And Methods Of Forming Memory Cells
JP5192016B2 (ja) * 2010-05-07 2013-05-08 東京エレクトロン株式会社 半導体装置の製造方法及び半導体装置の製造装置
US8518788B2 (en) 2010-08-11 2013-08-27 Micron Technology, Inc. Methods of forming a plurality of capacitors
US8455341B2 (en) 2010-09-02 2013-06-04 Micron Technology, Inc. Methods of forming features of integrated circuitry
US8901016B2 (en) * 2010-12-28 2014-12-02 Asm Japan K.K. Method of forming metal oxide hardmask
US8890318B2 (en) 2011-04-15 2014-11-18 International Business Machines Corporation Middle of line structures
US9054160B2 (en) 2011-04-15 2015-06-09 International Business Machines Corporation Interconnect structure and method for fabricating on-chip interconnect structures by image reversal
US8900988B2 (en) 2011-04-15 2014-12-02 International Business Machines Corporation Method for forming self-aligned airgap interconnect structures
US8575032B2 (en) 2011-05-05 2013-11-05 Micron Technology, Inc. Methods of forming a pattern on a substrate
US9312155B2 (en) 2011-06-06 2016-04-12 Asm Japan K.K. High-throughput semiconductor-processing apparatus equipped with multiple dual-chamber modules
US9793148B2 (en) 2011-06-22 2017-10-17 Asm Japan K.K. Method for positioning wafers in multiple wafer transport
US10364496B2 (en) 2011-06-27 2019-07-30 Asm Ip Holding B.V. Dual section module having shared and unshared mass flow controllers
US10854498B2 (en) 2011-07-15 2020-12-01 Asm Ip Holding B.V. Wafer-supporting device and method for producing same
US20130023129A1 (en) 2011-07-20 2013-01-24 Asm America, Inc. Pressure transmitter for a semiconductor processing environment
US8822137B2 (en) * 2011-08-03 2014-09-02 International Business Machines Corporation Self-aligned fine pitch permanent on-chip interconnect structures and method of fabrication
US20130062732A1 (en) 2011-09-08 2013-03-14 International Business Machines Corporation Interconnect structures with functional components and methods for fabrication
US9076680B2 (en) 2011-10-18 2015-07-07 Micron Technology, Inc. Integrated circuitry, methods of forming capacitors, and methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array
US9017481B1 (en) 2011-10-28 2015-04-28 Asm America, Inc. Process feed management for semiconductor substrate processing
US9177794B2 (en) 2012-01-13 2015-11-03 Micron Technology, Inc. Methods of patterning substrates
US8946830B2 (en) 2012-04-04 2015-02-03 Asm Ip Holdings B.V. Metal oxide protective layer for a semiconductor device
US9087753B2 (en) 2012-05-10 2015-07-21 International Business Machines Corporation Printed transistor and fabrication method
CN102768956A (zh) * 2012-07-02 2012-11-07 北京大学 一种制备边缘粗糙度较小的细线条的方法
US8629048B1 (en) 2012-07-06 2014-01-14 Micron Technology, Inc. Methods of forming a pattern on a substrate
US8735296B2 (en) * 2012-07-18 2014-05-27 International Business Machines Corporation Method of simultaneously forming multiple structures having different critical dimensions using sidewall transfer
US9558931B2 (en) 2012-07-27 2017-01-31 Asm Ip Holding B.V. System and method for gas-phase sulfur passivation of a semiconductor surface
US9659799B2 (en) 2012-08-28 2017-05-23 Asm Ip Holding B.V. Systems and methods for dynamic semiconductor process scheduling
US9021985B2 (en) 2012-09-12 2015-05-05 Asm Ip Holdings B.V. Process gas management for an inductively-coupled plasma deposition reactor
US9324811B2 (en) 2012-09-26 2016-04-26 Asm Ip Holding B.V. Structures and devices including a tensile-stressed silicon arsenic layer and methods of forming same
US10714315B2 (en) 2012-10-12 2020-07-14 Asm Ip Holdings B.V. Semiconductor reaction chamber showerhead
US9640416B2 (en) 2012-12-26 2017-05-02 Asm Ip Holding B.V. Single-and dual-chamber module-attachable wafer-handling chamber
US20140234466A1 (en) * 2013-02-21 2014-08-21 HGST Netherlands B.V. Imprint mold and method for making using sidewall spacer line doubling
US8623770B1 (en) 2013-02-21 2014-01-07 HGST Netherlands B.V. Method for sidewall spacer line doubling using atomic layer deposition of a titanium oxide
US9589770B2 (en) 2013-03-08 2017-03-07 Asm Ip Holding B.V. Method and systems for in-situ formation of intermediate reactive species
US9484191B2 (en) 2013-03-08 2016-11-01 Asm Ip Holding B.V. Pulsed remote plasma method and system
US9437443B2 (en) * 2013-06-12 2016-09-06 Globalfoundries Inc. Low-temperature sidewall image transfer process using ALD metals, metal oxides and metal nitrides
US8993054B2 (en) 2013-07-12 2015-03-31 Asm Ip Holding B.V. Method and system to reduce outgassing in a reaction chamber
US9018111B2 (en) 2013-07-22 2015-04-28 Asm Ip Holding B.V. Semiconductor reaction chamber with plasma capabilities
US9793115B2 (en) 2013-08-14 2017-10-17 Asm Ip Holding B.V. Structures and devices including germanium-tin films and methods of forming same
US9240412B2 (en) 2013-09-27 2016-01-19 Asm Ip Holding B.V. Semiconductor structure and device and methods of forming same using selective epitaxial process
US9556516B2 (en) 2013-10-09 2017-01-31 ASM IP Holding B.V Method for forming Ti-containing film by PEALD using TDMAT or TDEAT
US9159579B2 (en) * 2013-10-25 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Lithography using multilayer spacer for reduced spacer footing
US10179947B2 (en) 2013-11-26 2019-01-15 Asm Ip Holding B.V. Method for forming conformal nitrided, oxidized, or carbonized dielectric film by atomic layer deposition
US9177797B2 (en) * 2013-12-04 2015-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Lithography using high selectivity spacers for pitch reduction
US10683571B2 (en) 2014-02-25 2020-06-16 Asm Ip Holding B.V. Gas supply manifold and method of supplying gases to chamber using same
US9447498B2 (en) 2014-03-18 2016-09-20 Asm Ip Holding B.V. Method for performing uniform processing in gas system-sharing multiple reaction chambers
US10167557B2 (en) 2014-03-18 2019-01-01 Asm Ip Holding B.V. Gas distribution system, reactor including the system, and methods of using the same
US11015245B2 (en) 2014-03-19 2021-05-25 Asm Ip Holding B.V. Gas-phase reactor and system having exhaust plenum and components thereof
US9404587B2 (en) 2014-04-24 2016-08-02 ASM IP Holding B.V Lockout tagout for semiconductor vacuum valve
US10858737B2 (en) 2014-07-28 2020-12-08 Asm Ip Holding B.V. Showerhead assembly and components thereof
JP2016033968A (ja) 2014-07-31 2016-03-10 マイクロン テクノロジー， インク． 半導体装置の製造方法
US9543180B2 (en) 2014-08-01 2017-01-10 Asm Ip Holding B.V. Apparatus and method for transporting wafers between wafer carrier and process tool under vacuum
US9890456B2 (en) 2014-08-21 2018-02-13 Asm Ip Holding B.V. Method and system for in situ formation of gas-phase compounds
US9165765B1 (en) * 2014-09-09 2015-10-20 Tokyo Electron Limited Method for patterning differing critical dimensions at sub-resolution scales
US9564342B2 (en) 2014-09-26 2017-02-07 Tokyo Electron Limited Method for controlling etching in pitch doubling
US9657845B2 (en) 2014-10-07 2017-05-23 Asm Ip Holding B.V. Variable conductance gas distribution apparatus and method
US10941490B2 (en) 2014-10-07 2021-03-09 Asm Ip Holding B.V. Multiple temperature range susceptor, assembly, reactor and system including the susceptor, and methods of using the same
KR102300403B1 (ko) 2014-11-19 2021-09-09 에이에스엠 아이피 홀딩 비.브이. 박막 증착 방법
US9564312B2 (en) 2014-11-24 2017-02-07 Lam Research Corporation Selective inhibition in atomic layer deposition of silicon-containing films
KR102263121B1 (ko) 2014-12-22 2021-06-09 에이에스엠 아이피 홀딩 비.브이. 반도체 소자 및 그 제조 방법
US9673059B2 (en) * 2015-02-02 2017-06-06 Tokyo Electron Limited Method for increasing pattern density in self-aligned patterning integration schemes
US9478415B2 (en) 2015-02-13 2016-10-25 Asm Ip Holding B.V. Method for forming film having low resistance and shallow junction depth
US9443731B1 (en) 2015-02-20 2016-09-13 Tokyo Electron Limited Material processing to achieve sub-10nm patterning
US9530646B2 (en) * 2015-02-24 2016-12-27 United Microelectronics Corp. Method of forming a semiconductor structure
US10529542B2 (en) 2015-03-11 2020-01-07 Asm Ip Holdings B.V. Cross-flow reactor and method
US10276355B2 (en) 2015-03-12 2019-04-30 Asm Ip Holding B.V. Multi-zone reactor, system including the reactor, and method of using the same
US9741566B2 (en) * 2015-03-30 2017-08-22 Applied Materials, Inc. Methods for manufacturing a spacer with desired profile in an advanced patterning process
KR102338363B1 (ko) * 2015-04-15 2021-12-09 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR102345538B1 (ko) 2015-04-16 2021-12-30 삼성전자주식회사 라인 패턴들을 포함하는 반도체 소자
US10458018B2 (en) 2015-06-26 2019-10-29 Asm Ip Holding B.V. Structures including metal carbide material, devices including the structures, and methods of forming same
US10600673B2 (en) 2015-07-07 2020-03-24 Asm Ip Holding B.V. Magnetic susceptor to baseplate seal
US10043661B2 (en) 2015-07-13 2018-08-07 Asm Ip Holding B.V. Method for protecting layer by forming hydrocarbon-based extremely thin film
US9899291B2 (en) 2015-07-13 2018-02-20 Asm Ip Holding B.V. Method for protecting layer by forming hydrocarbon-based extremely thin film
US10083836B2 (en) 2015-07-24 2018-09-25 Asm Ip Holding B.V. Formation of boron-doped titanium metal films with high work function
US10087525B2 (en) 2015-08-04 2018-10-02 Asm Ip Holding B.V. Variable gap hard stop design
US9647114B2 (en) 2015-08-14 2017-05-09 Asm Ip Holding B.V. Methods of forming highly p-type doped germanium tin films and structures and devices including the films
US9711345B2 (en) 2015-08-25 2017-07-18 Asm Ip Holding B.V. Method for forming aluminum nitride-based film by PEALD
US9640481B2 (en) 2015-09-03 2017-05-02 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US9601693B1 (en) 2015-09-24 2017-03-21 Lam Research Corporation Method for encapsulating a chalcogenide material
US9960072B2 (en) 2015-09-29 2018-05-01 Asm Ip Holding B.V. Variable adjustment for precise matching of multiple chamber cavity housings
US9909214B2 (en) 2015-10-15 2018-03-06 Asm Ip Holding B.V. Method for depositing dielectric film in trenches by PEALD
US10211308B2 (en) 2015-10-21 2019-02-19 Asm Ip Holding B.V. NbMC layers
US10322384B2 (en) 2015-11-09 2019-06-18 Asm Ip Holding B.V. Counter flow mixer for process chamber
US9455138B1 (en) 2015-11-10 2016-09-27 Asm Ip Holding B.V. Method for forming dielectric film in trenches by PEALD using H-containing gas
US9905420B2 (en) 2015-12-01 2018-02-27 Asm Ip Holding B.V. Methods of forming silicon germanium tin films and structures and devices including the films
US9607837B1 (en) 2015-12-21 2017-03-28 Asm Ip Holding B.V. Method for forming silicon oxide cap layer for solid state diffusion process
US9627221B1 (en) 2015-12-28 2017-04-18 Asm Ip Holding B.V. Continuous process incorporating atomic layer etching
US9735024B2 (en) 2015-12-28 2017-08-15 Asm Ip Holding B.V. Method of atomic layer etching using functional group-containing fluorocarbon
US11139308B2 (en) 2015-12-29 2021-10-05 Asm Ip Holding B.V. Atomic layer deposition of III-V compounds to form V-NAND devices
US10157742B2 (en) 2015-12-31 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Method for mandrel and spacer patterning
US10468251B2 (en) 2016-02-19 2019-11-05 Asm Ip Holding B.V. Method for forming spacers using silicon nitride film for spacer-defined multiple patterning
US10529554B2 (en) 2016-02-19 2020-01-07 Asm Ip Holding B.V. Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches
US9754779B1 (en) 2016-02-19 2017-09-05 Asm Ip Holding B.V. Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches
US10501866B2 (en) 2016-03-09 2019-12-10 Asm Ip Holding B.V. Gas distribution apparatus for improved film uniformity in an epitaxial system
US10343920B2 (en) 2016-03-18 2019-07-09 Asm Ip Holding B.V. Aligned carbon nanotubes
US9892913B2 (en) 2016-03-24 2018-02-13 Asm Ip Holding B.V. Radial and thickness control via biased multi-port injection settings
US20170294354A1 (en) * 2016-04-07 2017-10-12 Globalfoundries Inc. Integration of nominal gate width finfets and devices having larger gate width
US9852900B2 (en) * 2016-04-07 2017-12-26 Globalfoundries Inc. Oxidizing filler material lines to increase width of hard mask lines
US10865475B2 (en) 2016-04-21 2020-12-15 Asm Ip Holding B.V. Deposition of metal borides and silicides
US10190213B2 (en) 2016-04-21 2019-01-29 Asm Ip Holding B.V. Deposition of metal borides
US10087522B2 (en) 2016-04-21 2018-10-02 Asm Ip Holding B.V. Deposition of metal borides
US10367080B2 (en) 2016-05-02 2019-07-30 Asm Ip Holding B.V. Method of forming a germanium oxynitride film
US10032628B2 (en) 2016-05-02 2018-07-24 Asm Ip Holding B.V. Source/drain performance through conformal solid state doping
KR102592471B1 (ko) 2016-05-17 2023-10-20 에이에스엠 아이피 홀딩 비.브이. 금속 배선 형성 방법 및 이를 이용한 반도체 장치의 제조 방법
US11453943B2 (en) 2016-05-25 2022-09-27 Asm Ip Holding B.V. Method for forming carbon-containing silicon/metal oxide or nitride film by ALD using silicon precursor and hydrocarbon precursor
US10388509B2 (en) 2016-06-28 2019-08-20 Asm Ip Holding B.V. Formation of epitaxial layers via dislocation filtering
US9685440B1 (en) 2016-06-29 2017-06-20 International Business Machines Corporation Forming fins utilizing alternating pattern of spacers
US9882028B2 (en) * 2016-06-29 2018-01-30 International Business Machines Corporation Pitch split patterning for semiconductor devices
US9859151B1 (en) 2016-07-08 2018-01-02 Asm Ip Holding B.V. Selective film deposition method to form air gaps
US10612137B2 (en) 2016-07-08 2020-04-07 Asm Ip Holdings B.V. Organic reactants for atomic layer deposition
US9793135B1 (en) 2016-07-14 2017-10-17 ASM IP Holding B.V Method of cyclic dry etching using etchant film
US10714385B2 (en) 2016-07-19 2020-07-14 Asm Ip Holding B.V. Selective deposition of tungsten
US9779942B1 (en) 2016-07-26 2017-10-03 United Microelectronics Corp. Method of forming patterned mask layer
KR102354490B1 (ko) 2016-07-27 2022-01-21 에이에스엠 아이피 홀딩 비.브이. 기판 처리 방법
KR102532607B1 (ko) 2016-07-28 2023-05-15 에이에스엠 아이피 홀딩 비.브이. 기판 가공 장치 및 그 동작 방법
US9887082B1 (en) 2016-07-28 2018-02-06 Asm Ip Holding B.V. Method and apparatus for filling a gap
US10395919B2 (en) 2016-07-28 2019-08-27 Asm Ip Holding B.V. Method and apparatus for filling a gap
US10177025B2 (en) 2016-07-28 2019-01-08 Asm Ip Holding B.V. Method and apparatus for filling a gap
US9812320B1 (en) 2016-07-28 2017-11-07 Asm Ip Holding B.V. Method and apparatus for filling a gap
US10629435B2 (en) * 2016-07-29 2020-04-21 Lam Research Corporation Doped ALD films for semiconductor patterning applications
US10074543B2 (en) 2016-08-31 2018-09-11 Lam Research Corporation High dry etch rate materials for semiconductor patterning applications
US10090316B2 (en) 2016-09-01 2018-10-02 Asm Ip Holding B.V. 3D stacked multilayer semiconductor memory using doped select transistor channel
WO2018057499A1 (en) * 2016-09-20 2018-03-29 Tokyo Electron Limited Spacer formation for self-aligned multi-patterning technique
US10410943B2 (en) 2016-10-13 2019-09-10 Asm Ip Holding B.V. Method for passivating a surface of a semiconductor and related systems
US10643826B2 (en) 2016-10-26 2020-05-05 Asm Ip Holdings B.V. Methods for thermally calibrating reaction chambers
US11532757B2 (en) 2016-10-27 2022-12-20 Asm Ip Holding B.V. Deposition of charge trapping layers
US10229833B2 (en) 2016-11-01 2019-03-12 Asm Ip Holding B.V. Methods for forming a transition metal nitride film on a substrate by atomic layer deposition and related semiconductor device structures
US10643904B2 (en) 2016-11-01 2020-05-05 Asm Ip Holdings B.V. Methods for forming a semiconductor device and related semiconductor device structures
US10714350B2 (en) 2016-11-01 2020-07-14 ASM IP Holdings, B.V. Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures
US10435790B2 (en) 2016-11-01 2019-10-08 Asm Ip Holding B.V. Method of subatmospheric plasma-enhanced ALD using capacitively coupled electrodes with narrow gap
US10134757B2 (en) 2016-11-07 2018-11-20 Asm Ip Holding B.V. Method of processing a substrate and a device manufactured by using the method
US10454029B2 (en) 2016-11-11 2019-10-22 Lam Research Corporation Method for reducing the wet etch rate of a sin film without damaging the underlying substrate
US10832908B2 (en) 2016-11-11 2020-11-10 Lam Research Corporation Self-aligned multi-patterning process flow with ALD gapfill spacer mask
US10134579B2 (en) 2016-11-14 2018-11-20 Lam Research Corporation Method for high modulus ALD SiO2 spacer
KR102546317B1 (ko) 2016-11-15 2023-06-21 에이에스엠 아이피 홀딩 비.브이. 기체 공급 유닛 및 이를 포함하는 기판 처리 장치
US10340135B2 (en) 2016-11-28 2019-07-02 Asm Ip Holding B.V. Method of topologically restricted plasma-enhanced cyclic deposition of silicon or metal nitride
KR20180068582A (ko) 2016-12-14 2018-06-22 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치
US11447861B2 (en) 2016-12-15 2022-09-20 Asm Ip Holding B.V. Sequential infiltration synthesis apparatus and a method of forming a patterned structure
US9916980B1 (en) 2016-12-15 2018-03-13 Asm Ip Holding B.V. Method of forming a structure on a substrate
US11581186B2 (en) 2016-12-15 2023-02-14 Asm Ip Holding B.V. Sequential infiltration synthesis apparatus
KR20180070971A (ko) 2016-12-19 2018-06-27 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치
US10269558B2 (en) 2016-12-22 2019-04-23 Asm Ip Holding B.V. Method of forming a structure on a substrate
US10867788B2 (en) 2016-12-28 2020-12-15 Asm Ip Holding B.V. Method of forming a structure on a substrate
US11390950B2 (en) 2017-01-10 2022-07-19 Asm Ip Holding B.V. Reactor system and method to reduce residue buildup during a film deposition process
US10655221B2 (en) 2017-02-09 2020-05-19 Asm Ip Holding B.V. Method for depositing oxide film by thermal ALD and PEALD
US10468261B2 (en) 2017-02-15 2019-11-05 Asm Ip Holding B.V. Methods for forming a metallic film on a substrate by cyclical deposition and related semiconductor device structures
US10529563B2 (en) 2017-03-29 2020-01-07 Asm Ip Holdings B.V. Method for forming doped metal oxide films on a substrate by cyclical deposition and related semiconductor device structures
US10283353B2 (en) 2017-03-29 2019-05-07 Asm Ip Holding B.V. Method of reforming insulating film deposited on substrate with recess pattern
US10103040B1 (en) 2017-03-31 2018-10-16 Asm Ip Holding B.V. Apparatus and method for manufacturing a semiconductor device
USD830981S1 (en) 2017-04-07 2018-10-16 Asm Ip Holding B.V. Susceptor for semiconductor substrate processing apparatus
KR102457289B1 (ko) 2017-04-25 2022-10-21 에이에스엠 아이피 홀딩 비.브이. 박막 증착 방법 및 반도체 장치의 제조 방법
US10770286B2 (en) 2017-05-08 2020-09-08 Asm Ip Holdings B.V. Methods for selectively forming a silicon nitride film on a substrate and related semiconductor device structures
US10892156B2 (en) 2017-05-08 2021-01-12 Asm Ip Holding B.V. Methods for forming a silicon nitride film on a substrate and related semiconductor device structures
US10446393B2 (en) 2017-05-08 2019-10-15 Asm Ip Holding B.V. Methods for forming silicon-containing epitaxial layers and related semiconductor device structures
CN108962742B (zh) * 2017-05-25 2021-05-28 中芯国际集成电路制造(上海)有限公司 半导体结构的制造方法
US10504742B2 (en) 2017-05-31 2019-12-10 Asm Ip Holding B.V. Method of atomic layer etching using hydrogen plasma
US10886123B2 (en) 2017-06-02 2021-01-05 Asm Ip Holding B.V. Methods for forming low temperature semiconductor layers and related semiconductor device structures
US11306395B2 (en) 2017-06-28 2022-04-19 Asm Ip Holding B.V. Methods for depositing a transition metal nitride film on a substrate by atomic layer deposition and related deposition apparatus
US10685834B2 (en) 2017-07-05 2020-06-16 Asm Ip Holdings B.V. Methods for forming a silicon germanium tin layer and related semiconductor device structures
KR20190009245A (ko) 2017-07-18 2019-01-28 에이에스엠 아이피 홀딩 비.브이. 반도체 소자 구조물 형성 방법 및 관련된 반도체 소자 구조물
US10541333B2 (en) 2017-07-19 2020-01-21 Asm Ip Holding B.V. Method for depositing a group IV semiconductor and related semiconductor device structures
US11018002B2 (en) 2017-07-19 2021-05-25 Asm Ip Holding B.V. Method for selectively depositing a Group IV semiconductor and related semiconductor device structures
US11374112B2 (en) 2017-07-19 2022-06-28 Asm Ip Holding B.V. Method for depositing a group IV semiconductor and related semiconductor device structures
US10312055B2 (en) 2017-07-26 2019-06-04 Asm Ip Holding B.V. Method of depositing film by PEALD using negative bias
US10590535B2 (en) 2017-07-26 2020-03-17 Asm Ip Holdings B.V. Chemical treatment, deposition and/or infiltration apparatus and method for using the same
US10605530B2 (en) 2017-07-26 2020-03-31 Asm Ip Holding B.V. Assembly of a liner and a flange for a vertical furnace as well as the liner and the vertical furnace
US10692741B2 (en) 2017-08-08 2020-06-23 Asm Ip Holdings B.V. Radiation shield
US10770336B2 (en) 2017-08-08 2020-09-08 Asm Ip Holding B.V. Substrate lift mechanism and reactor including same
US11769682B2 (en) 2017-08-09 2023-09-26 Asm Ip Holding B.V. Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith
US11139191B2 (en) 2017-08-09 2021-10-05 Asm Ip Holding B.V. Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith
US10249524B2 (en) 2017-08-09 2019-04-02 Asm Ip Holding B.V. Cassette holder assembly for a substrate cassette and holding member for use in such assembly
US10236177B1 (en) 2017-08-22 2019-03-19 ASM IP Holding B.V.. Methods for depositing a doped germanium tin semiconductor and related semiconductor device structures
USD900036S1 (en) 2017-08-24 2020-10-27 Asm Ip Holding B.V. Heater electrical connector and adapter
US11830730B2 (en) 2017-08-29 2023-11-28 Asm Ip Holding B.V. Layer forming method and apparatus
KR102491945B1 (ko) 2017-08-30 2023-01-26 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치
US11295980B2 (en) 2017-08-30 2022-04-05 Asm Ip Holding B.V. Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process and related semiconductor device structures
US11056344B2 (en) 2017-08-30 2021-07-06 Asm Ip Holding B.V. Layer forming method
US10269559B2 (en) 2017-09-13 2019-04-23 Lam Research Corporation Dielectric gapfill of high aspect ratio features utilizing a sacrificial etch cap layer
US10607895B2 (en) 2017-09-18 2020-03-31 Asm Ip Holdings B.V. Method for forming a semiconductor device structure comprising a gate fill metal
KR102630301B1 (ko) 2017-09-21 2024-01-29 에이에스엠 아이피 홀딩 비.브이. 침투성 재료의 순차 침투 합성 방법 처리 및 이를 이용하여 형성된 구조물 및 장치
US10844484B2 (en) 2017-09-22 2020-11-24 Asm Ip Holding B.V. Apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods
US10658205B2 (en) 2017-09-28 2020-05-19 Asm Ip Holdings B.V. Chemical dispensing apparatus and methods for dispensing a chemical to a reaction chamber
US10403504B2 (en) 2017-10-05 2019-09-03 Asm Ip Holding B.V. Method for selectively depositing a metallic film on a substrate
US10319588B2 (en) 2017-10-10 2019-06-11 Asm Ip Holding B.V. Method for depositing a metal chalcogenide on a substrate by cyclical deposition
US10923344B2 (en) 2017-10-30 2021-02-16 Asm Ip Holding B.V. Methods for forming a semiconductor structure and related semiconductor structures
KR102443047B1 (ko) 2017-11-16 2022-09-14 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치 방법 및 그에 의해 제조된 장치
US10910262B2 (en) 2017-11-16 2021-02-02 Asm Ip Holding B.V. Method of selectively depositing a capping layer structure on a semiconductor device structure
US11022879B2 (en) 2017-11-24 2021-06-01 Asm Ip Holding B.V. Method of forming an enhanced unexposed photoresist layer
US11639811B2 (en) 2017-11-27 2023-05-02 Asm Ip Holding B.V. Apparatus including a clean mini environment
CN111316417B (zh) 2017-11-27 2023-12-22 阿斯莫Ip控股公司 与批式炉偕同使用的用于储存晶圆匣的储存装置
US10290508B1 (en) 2017-12-05 2019-05-14 Asm Ip Holding B.V. Method for forming vertical spacers for spacer-defined patterning
US10872771B2 (en) 2018-01-16 2020-12-22 Asm Ip Holding B. V. Method for depositing a material film on a substrate within a reaction chamber by a cyclical deposition process and related device structures
TW202325889A (zh) 2018-01-19 2023-07-01 荷蘭商Ａｓｍ 智慧財產控股公司 沈積方法
CN111630203A (zh) 2018-01-19 2020-09-04 Asm Ip私人控股有限公司 通过等离子体辅助沉积来沉积间隙填充层的方法
USD903477S1 (en) 2018-01-24 2020-12-01 Asm Ip Holdings B.V. Metal clamp
US11018047B2 (en) 2018-01-25 2021-05-25 Asm Ip Holding B.V. Hybrid lift pin
US10535516B2 (en) 2018-02-01 2020-01-14 Asm Ip Holdings B.V. Method for depositing a semiconductor structure on a surface of a substrate and related semiconductor structures
USD880437S1 (en) 2018-02-01 2020-04-07 Asm Ip Holding B.V. Gas supply plate for semiconductor manufacturing apparatus
US11081345B2 (en) 2018-02-06 2021-08-03 Asm Ip Holding B.V. Method of post-deposition treatment for silicon oxide film
US10896820B2 (en) 2018-02-14 2021-01-19 Asm Ip Holding B.V. Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process
CN116732497A (zh) 2018-02-14 2023-09-12 Asm Ip私人控股有限公司 通过循环沉积工艺在衬底上沉积含钌膜的方法
US10731249B2 (en) 2018-02-15 2020-08-04 Asm Ip Holding B.V. Method of forming a transition metal containing film on a substrate by a cyclical deposition process, a method for supplying a transition metal halide compound to a reaction chamber, and related vapor deposition apparatus
US10658181B2 (en) 2018-02-20 2020-05-19 Asm Ip Holding B.V. Method of spacer-defined direct patterning in semiconductor fabrication
KR102636427B1 (ko) 2018-02-20 2024-02-13 에이에스엠 아이피 홀딩 비.브이. 기판 처리 방법 및 장치
US10975470B2 (en) 2018-02-23 2021-04-13 Asm Ip Holding B.V. Apparatus for detecting or monitoring for a chemical precursor in a high temperature environment
US11473195B2 (en) 2018-03-01 2022-10-18 Asm Ip Holding B.V. Semiconductor processing apparatus and a method for processing a substrate
US11404275B2 (en) 2018-03-02 2022-08-02 Lam Research Corporation Selective deposition using hydrolysis
US11629406B2 (en) 2018-03-09 2023-04-18 Asm Ip Holding B.V. Semiconductor processing apparatus comprising one or more pyrometers for measuring a temperature of a substrate during transfer of the substrate
US11114283B2 (en) 2018-03-16 2021-09-07 Asm Ip Holding B.V. Reactor, system including the reactor, and methods of manufacturing and using same
KR102646467B1 (ko) 2018-03-27 2024-03-11 에이에스엠 아이피 홀딩 비.브이. 기판 상에 전극을 형성하는 방법 및 전극을 포함하는 반도체 소자 구조
US10510536B2 (en) 2018-03-29 2019-12-17 Asm Ip Holding B.V. Method of depositing a co-doped polysilicon film on a surface of a substrate within a reaction chamber
US11230766B2 (en) 2018-03-29 2022-01-25 Asm Ip Holding B.V. Substrate processing apparatus and method
US11088002B2 (en) 2018-03-29 2021-08-10 Asm Ip Holding B.V. Substrate rack and a substrate processing system and method
KR102501472B1 (ko) 2018-03-30 2023-02-20 에이에스엠 아이피 홀딩 비.브이. 기판 처리 방법
KR102572514B1 (ko) * 2018-04-17 2023-08-31 삼성전자주식회사 반도체 소자 및 이의 제조 방법
TWI811348B (zh) 2018-05-08 2023-08-11 荷蘭商Ａｓｍ 智慧財產控股公司 藉由循環沉積製程於基板上沉積氧化物膜之方法及相關裝置結構
TW202349473A (zh) 2018-05-11 2023-12-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 用於基板上形成摻雜金屬碳化物薄膜之方法及相關半導體元件結構
KR102596988B1 (ko) 2018-05-28 2023-10-31 에이에스엠 아이피 홀딩 비.브이. 기판 처리 방법 및 그에 의해 제조된 장치
US11718913B2 (en) 2018-06-04 2023-08-08 Asm Ip Holding B.V. Gas distribution system and reactor system including same
TW202013553A (zh) 2018-06-04 2020-04-01 荷蘭商Ａｓｍ 智慧財產控股公司 水氣降低的晶圓處置腔室
CN110581066A (zh) * 2018-06-07 2019-12-17 长鑫存储技术有限公司 多倍掩膜层的制作方法
US11286562B2 (en) 2018-06-08 2022-03-29 Asm Ip Holding B.V. Gas-phase chemical reactor and method of using same
US10797133B2 (en) 2018-06-21 2020-10-06 Asm Ip Holding B.V. Method for depositing a phosphorus doped silicon arsenide film and related semiconductor device structures
KR102568797B1 (ko) 2018-06-21 2023-08-21 에이에스엠 아이피 홀딩 비.브이. 기판 처리 시스템
WO2020002995A1 (en) 2018-06-27 2020-01-02 Asm Ip Holding B.V. Cyclic deposition methods for forming metal-containing material and films and structures including the metal-containing material
KR20210027265A (ko) 2018-06-27 2021-03-10 에이에스엠 아이피 홀딩 비.브이. 금속 함유 재료를 형성하기 위한 주기적 증착 방법 및 금속 함유 재료를 포함하는 막 및 구조체
US10612136B2 (en) 2018-06-29 2020-04-07 ASM IP Holding, B.V. Temperature-controlled flange and reactor system including same
KR20200002519A (ko) 2018-06-29 2020-01-08 에이에스엠 아이피 홀딩 비.브이. 박막 증착 방법 및 반도체 장치의 제조 방법
US10755922B2 (en) 2018-07-03 2020-08-25 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US10388513B1 (en) 2018-07-03 2019-08-20 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US10767789B2 (en) 2018-07-16 2020-09-08 Asm Ip Holding B.V. Diaphragm valves, valve components, and methods for forming valve components
US10483099B1 (en) 2018-07-26 2019-11-19 Asm Ip Holding B.V. Method for forming thermally stable organosilicon polymer film
US11053591B2 (en) 2018-08-06 2021-07-06 Asm Ip Holding B.V. Multi-port gas injection system and reactor system including same
US10883175B2 (en) 2018-08-09 2021-01-05 Asm Ip Holding B.V. Vertical furnace for processing substrates and a liner for use therein
US10829852B2 (en) 2018-08-16 2020-11-10 Asm Ip Holding B.V. Gas distribution device for a wafer processing apparatus
US11430674B2 (en) 2018-08-22 2022-08-30 Asm Ip Holding B.V. Sensor array, apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods
KR20200030162A (ko) 2018-09-11 2020-03-20 에이에스엠 아이피 홀딩 비.브이. 박막 증착 방법
US11024523B2 (en) 2018-09-11 2021-06-01 Asm Ip Holding B.V. Substrate processing apparatus and method
US11049751B2 (en) 2018-09-14 2021-06-29 Asm Ip Holding B.V. Cassette supply system to store and handle cassettes and processing apparatus equipped therewith
CN110970344A (zh) 2018-10-01 2020-04-07 Asm Ip控股有限公司 衬底保持设备、包含所述设备的系统及其使用方法
US11232963B2 (en) 2018-10-03 2022-01-25 Asm Ip Holding B.V. Substrate processing apparatus and method
KR102592699B1 (ko) 2018-10-08 2023-10-23 에이에스엠 아이피 홀딩 비.브이. 기판 지지 유닛 및 이를 포함하는 박막 증착 장치와 기판 처리 장치
US10957549B2 (en) 2018-10-08 2021-03-23 Micron Technology, Inc. Methods of forming semiconductor devices using mask materials, and related semiconductor devices and systems
US10847365B2 (en) 2018-10-11 2020-11-24 Asm Ip Holding B.V. Method of forming conformal silicon carbide film by cyclic CVD
US10811256B2 (en) 2018-10-16 2020-10-20 Asm Ip Holding B.V. Method for etching a carbon-containing feature
KR102546322B1 (ko) 2018-10-19 2023-06-21 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치 및 기판 처리 방법
KR102605121B1 (ko) 2018-10-19 2023-11-23 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치 및 기판 처리 방법
USD948463S1 (en) 2018-10-24 2022-04-12 Asm Ip Holding B.V. Susceptor for semiconductor substrate supporting apparatus
US10381219B1 (en) 2018-10-25 2019-08-13 Asm Ip Holding B.V. Methods for forming a silicon nitride film
US11087997B2 (en) 2018-10-31 2021-08-10 Asm Ip Holding B.V. Substrate processing apparatus for processing substrates
KR20200051105A (ko) 2018-11-02 2020-05-13 에이에스엠 아이피 홀딩 비.브이. 기판 지지 유닛 및 이를 포함하는 기판 처리 장치
US11572620B2 (en) 2018-11-06 2023-02-07 Asm Ip Holding B.V. Methods for selectively depositing an amorphous silicon film on a substrate
US11031242B2 (en) 2018-11-07 2021-06-08 Asm Ip Holding B.V. Methods for depositing a boron doped silicon germanium film
US10847366B2 (en) 2018-11-16 2020-11-24 Asm Ip Holding B.V. Methods for depositing a transition metal chalcogenide film on a substrate by a cyclical deposition process
US10818758B2 (en) 2018-11-16 2020-10-27 Asm Ip Holding B.V. Methods for forming a metal silicate film on a substrate in a reaction chamber and related semiconductor device structures
US10559458B1 (en) 2018-11-26 2020-02-11 Asm Ip Holding B.V. Method of forming oxynitride film
US11217444B2 (en) 2018-11-30 2022-01-04 Asm Ip Holding B.V. Method for forming an ultraviolet radiation responsive metal oxide-containing film
KR102636428B1 (ko) 2018-12-04 2024-02-13 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치를 세정하는 방법
US11158513B2 (en) 2018-12-13 2021-10-26 Asm Ip Holding B.V. Methods for forming a rhenium-containing film on a substrate by a cyclical deposition process and related semiconductor device structures
TW202037745A (zh) 2018-12-14 2020-10-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 形成裝置結構之方法、其所形成之結構及施行其之系統
TWI819180B (zh) 2019-01-17 2023-10-21 荷蘭商Ａｓｍ 智慧財產控股公司 藉由循環沈積製程於基板上形成含過渡金屬膜之方法
KR20200091543A (ko) 2019-01-22 2020-07-31 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치
CN111524788B (zh) 2019-02-01 2023-11-24 Asm Ip私人控股有限公司 氧化硅的拓扑选择性膜形成的方法
KR20200102357A (ko) 2019-02-20 2020-08-31 에이에스엠 아이피 홀딩 비.브이. 3-d nand 응용의 플러그 충진체 증착용 장치 및 방법
KR102638425B1 (ko) 2019-02-20 2024-02-21 에이에스엠 아이피 홀딩 비.브이. 기판 표면 내에 형성된 오목부를 충진하기 위한 방법 및 장치
KR102626263B1 (ko) 2019-02-20 2024-01-16 에이에스엠 아이피 홀딩 비.브이. 처리 단계를 포함하는 주기적 증착 방법 및 이를 위한 장치
TW202104632A (zh) 2019-02-20 2021-02-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 用來填充形成於基材表面內之凹部的循環沉積方法及設備
TW202100794A (zh) 2019-02-22 2021-01-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 基材處理設備及處理基材之方法
KR20200108242A (ko) 2019-03-08 2020-09-17 에이에스엠 아이피 홀딩 비.브이. 실리콘 질화물 층을 선택적으로 증착하는 방법, 및 선택적으로 증착된 실리콘 질화물 층을 포함하는 구조체
US11742198B2 (en) 2019-03-08 2023-08-29 Asm Ip Holding B.V. Structure including SiOCN layer and method of forming same
KR20200108243A (ko) 2019-03-08 2020-09-17 에이에스엠 아이피 홀딩 비.브이. SiOC 층을 포함한 구조체 및 이의 형성 방법
KR20200116033A (ko) 2019-03-28 2020-10-08 에이에스엠 아이피 홀딩 비.브이. 도어 개방기 및 이를 구비한 기판 처리 장치
KR20200116855A (ko) 2019-04-01 2020-10-13 에이에스엠 아이피 홀딩 비.브이. 반도체 소자를 제조하는 방법
KR20200123380A (ko) 2019-04-19 2020-10-29 에이에스엠 아이피 홀딩 비.브이. 층 형성 방법 및 장치
KR20200125453A (ko) 2019-04-24 2020-11-04 에이에스엠 아이피 홀딩 비.브이. 기상 반응기 시스템 및 이를 사용하는 방법
KR20200130121A (ko) 2019-05-07 2020-11-18 에이에스엠 아이피 홀딩 비.브이. 딥 튜브가 있는 화학물질 공급원 용기
KR20200130118A (ko) 2019-05-07 2020-11-18 에이에스엠 아이피 홀딩 비.브이. 비정질 탄소 중합체 막을 개질하는 방법
KR20200130652A (ko) 2019-05-10 2020-11-19 에이에스엠 아이피 홀딩 비.브이. 표면 상에 재료를 증착하는 방법 및 본 방법에 따라 형성된 구조
JP2020188255A (ja) 2019-05-16 2020-11-19 エーエスエム アイピー ホールディング ビー．ブイ． ウェハボートハンドリング装置、縦型バッチ炉および方法
USD975665S1 (en) 2019-05-17 2023-01-17 Asm Ip Holding B.V. Susceptor shaft
USD947913S1 (en) 2019-05-17 2022-04-05 Asm Ip Holding B.V. Susceptor shaft
USD935572S1 (en) 2019-05-24 2021-11-09 Asm Ip Holding B.V. Gas channel plate
USD922229S1 (en) 2019-06-05 2021-06-15 Asm Ip Holding B.V. Device for controlling a temperature of a gas supply unit
KR20200141002A (ko) 2019-06-06 2020-12-17 에이에스엠 아이피 홀딩 비.브이. 배기 가스 분석을 포함한 기상 반응기 시스템을 사용하는 방법
KR20200143254A (ko) 2019-06-11 2020-12-23 에이에스엠 아이피 홀딩 비.브이. 개질 가스를 사용하여 전자 구조를 형성하는 방법, 상기 방법을 수행하기 위한 시스템, 및 상기 방법을 사용하여 형성되는 구조
USD944946S1 (en) 2019-06-14 2022-03-01 Asm Ip Holding B.V. Shower plate
USD931978S1 (en) 2019-06-27 2021-09-28 Asm Ip Holding B.V. Showerhead vacuum transport
KR20210005515A (ko) 2019-07-03 2021-01-14 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치용 온도 제어 조립체 및 이를 사용하는 방법
JP2021015791A (ja) 2019-07-09 2021-02-12 エーエスエム アイピー ホールディング ビー．ブイ． 同軸導波管を用いたプラズマ装置、基板処理方法
CN112216646A (zh) 2019-07-10 2021-01-12 Asm Ip私人控股有限公司 基板支撑组件及包括其的基板处理装置
KR20210010307A (ko) 2019-07-16 2021-01-27 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치
KR20210010820A (ko) 2019-07-17 2021-01-28 에이에스엠 아이피 홀딩 비.브이. 실리콘 게르마늄 구조를 형성하는 방법
KR20210010816A (ko) 2019-07-17 2021-01-28 에이에스엠 아이피 홀딩 비.브이. 라디칼 보조 점화 플라즈마 시스템 및 방법
US11643724B2 (en) 2019-07-18 2023-05-09 Asm Ip Holding B.V. Method of forming structures using a neutral beam
TW202121506A (zh) 2019-07-19 2021-06-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 形成形貌受控的非晶碳聚合物膜之方法
CN112309843A (zh) 2019-07-29 2021-02-02 Asm Ip私人控股有限公司 实现高掺杂剂掺入的选择性沉积方法
CN112309899A (zh) 2019-07-30 2021-02-02 Asm Ip私人控股有限公司 基板处理设备
CN112309900A (zh) 2019-07-30 2021-02-02 Asm Ip私人控股有限公司 基板处理设备
US11587814B2 (en) 2019-07-31 2023-02-21 Asm Ip Holding B.V. Vertical batch furnace assembly
US11227782B2 (en) 2019-07-31 2022-01-18 Asm Ip Holding B.V. Vertical batch furnace assembly
US11587815B2 (en) 2019-07-31 2023-02-21 Asm Ip Holding B.V. Vertical batch furnace assembly
KR20210018759A (ko) 2019-08-05 2021-02-18 에이에스엠 아이피 홀딩 비.브이. 화학물질 공급원 용기를 위한 액체 레벨 센서
USD965524S1 (en) 2019-08-19 2022-10-04 Asm Ip Holding B.V. Susceptor support
USD965044S1 (en) 2019-08-19 2022-09-27 Asm Ip Holding B.V. Susceptor shaft
JP2021031769A (ja) 2019-08-21 2021-03-01 エーエスエム アイピー ホールディング ビー．ブイ． 成膜原料混合ガス生成装置及び成膜装置
USD949319S1 (en) 2019-08-22 2022-04-19 Asm Ip Holding B.V. Exhaust duct
KR20210024423A (ko) 2019-08-22 2021-03-05 에이에스엠 아이피 홀딩 비.브이. 홀을 구비한 구조체를 형성하기 위한 방법
USD979506S1 (en) 2019-08-22 2023-02-28 Asm Ip Holding B.V. Insulator
USD930782S1 (en) 2019-08-22 2021-09-14 Asm Ip Holding B.V. Gas distributor
USD940837S1 (en) 2019-08-22 2022-01-11 Asm Ip Holding B.V. Electrode
KR20210024420A (ko) 2019-08-23 2021-03-05 에이에스엠 아이피 홀딩 비.브이. 비스(디에틸아미노)실란을 사용하여 peald에 의해 개선된 품질을 갖는 실리콘 산화물 막을 증착하기 위한 방법
US11286558B2 (en) 2019-08-23 2022-03-29 Asm Ip Holding B.V. Methods for depositing a molybdenum nitride film on a surface of a substrate by a cyclical deposition process and related semiconductor device structures including a molybdenum nitride film
KR20210029090A (ko) 2019-09-04 2021-03-15 에이에스엠 아이피 홀딩 비.브이. 희생 캡핑 층을 이용한 선택적 증착 방법
KR20210029663A (ko) 2019-09-05 2021-03-16 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치
US11189561B2 (en) * 2019-09-18 2021-11-30 International Business Machines Corporation Placing top vias at line ends by selective growth of via mask from line cut dielectric
US11562901B2 (en) 2019-09-25 2023-01-24 Asm Ip Holding B.V. Substrate processing method
CN112593212B (zh) 2019-10-02 2023-12-22 Asm Ip私人控股有限公司 通过循环等离子体增强沉积工艺形成拓扑选择性氧化硅膜的方法
TW202129060A (zh) 2019-10-08 2021-08-01 荷蘭商Ａｓｍ Ｉｐ控股公司 基板處理裝置、及基板處理方法
TW202115273A (zh) 2019-10-10 2021-04-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 形成光阻底層之方法及包括光阻底層之結構
KR20210045930A (ko) 2019-10-16 2021-04-27 에이에스엠 아이피 홀딩 비.브이. 실리콘 산화물의 토폴로지-선택적 막의 형성 방법
US11637014B2 (en) 2019-10-17 2023-04-25 Asm Ip Holding B.V. Methods for selective deposition of doped semiconductor material
KR20210047808A (ko) 2019-10-21 2021-04-30 에이에스엠 아이피 홀딩 비.브이. 막을 선택적으로 에칭하기 위한 장치 및 방법
US11646205B2 (en) 2019-10-29 2023-05-09 Asm Ip Holding B.V. Methods of selectively forming n-type doped material on a surface, systems for selectively forming n-type doped material, and structures formed using same
KR20210054983A (ko) 2019-11-05 2021-05-14 에이에스엠 아이피 홀딩 비.브이. 도핑된 반도체 층을 갖는 구조체 및 이를 형성하기 위한 방법 및 시스템
US11501968B2 (en) 2019-11-15 2022-11-15 Asm Ip Holding B.V. Method for providing a semiconductor device with silicon filled gaps
KR20210062561A (ko) 2019-11-20 2021-05-31 에이에스엠 아이피 홀딩 비.브이. 기판의 표면 상에 탄소 함유 물질을 증착하는 방법, 상기 방법을 사용하여 형성된 구조물, 및 상기 구조물을 형성하기 위한 시스템
US11450529B2 (en) 2019-11-26 2022-09-20 Asm Ip Holding B.V. Methods for selectively forming a target film on a substrate comprising a first dielectric surface and a second metallic surface
CN112951697A (zh) 2019-11-26 2021-06-11 Asm Ip私人控股有限公司 基板处理设备
CN112885693A (zh) 2019-11-29 2021-06-01 Asm Ip私人控股有限公司 基板处理设备
CN112885692A (zh) 2019-11-29 2021-06-01 Asm Ip私人控股有限公司 基板处理设备
JP2021090042A (ja) 2019-12-02 2021-06-10 エーエスエム アイピー ホールディング ビー．ブイ． 基板処理装置、基板処理方法
KR20210070898A (ko) 2019-12-04 2021-06-15 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치
TW202125596A (zh) 2019-12-17 2021-07-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 形成氮化釩層之方法以及包括該氮化釩層之結構
US11527403B2 (en) 2019-12-19 2022-12-13 Asm Ip Holding B.V. Methods for filling a gap feature on a substrate surface and related semiconductor structures
KR20210095050A (ko) 2020-01-20 2021-07-30 에이에스엠 아이피 홀딩 비.브이. 박막 형성 방법 및 박막 표면 개질 방법
TW202130846A (zh) 2020-02-03 2021-08-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 形成包括釩或銦層的結構之方法
TW202146882A (zh) 2020-02-04 2021-12-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 驗證一物品之方法、用於驗證一物品之設備、及用於驗證一反應室之系統
US11776846B2 (en) 2020-02-07 2023-10-03 Asm Ip Holding B.V. Methods for depositing gap filling fluids and related systems and devices
TW202146715A (zh) 2020-02-17 2021-12-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 用於生長磷摻雜矽層之方法及其系統
KR20210116240A (ko) 2020-03-11 2021-09-27 에이에스엠 아이피 홀딩 비.브이. 조절성 접합부를 갖는 기판 핸들링 장치
US11876356B2 (en) 2020-03-11 2024-01-16 Asm Ip Holding B.V. Lockout tagout assembly and system and method of using same
KR20210124042A (ko) 2020-04-02 2021-10-14 에이에스엠 아이피 홀딩 비.브이. 박막 형성 방법
TW202146689A (zh) 2020-04-03 2021-12-16 荷蘭商Ａｓｍ Ｉｐ控股公司 阻障層形成方法及半導體裝置的製造方法
TW202145344A (zh) 2020-04-08 2021-12-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 用於選擇性蝕刻氧化矽膜之設備及方法
US11821078B2 (en) 2020-04-15 2023-11-21 Asm Ip Holding B.V. Method for forming precoat film and method for forming silicon-containing film
KR20210132576A (ko) 2020-04-24 2021-11-04 에이에스엠 아이피 홀딩 비.브이. 바나듐 나이트라이드 함유 층을 형성하는 방법 및 이를 포함하는 구조
KR20210132600A (ko) 2020-04-24 2021-11-04 에이에스엠 아이피 홀딩 비.브이. 바나듐, 질소 및 추가 원소를 포함한 층을 증착하기 위한 방법 및 시스템
KR20210132605A (ko) 2020-04-24 2021-11-04 에이에스엠 아이피 홀딩 비.브이. 냉각 가스 공급부를 포함한 수직형 배치 퍼니스 어셈블리
KR20210134869A (ko) 2020-05-01 2021-11-11 에이에스엠 아이피 홀딩 비.브이. Foup 핸들러를 이용한 foup의 빠른 교환
KR20210141379A (ko) 2020-05-13 2021-11-23 에이에스엠 아이피 홀딩 비.브이. 반응기 시스템용 레이저 정렬 고정구
KR20210143653A (ko) 2020-05-19 2021-11-29 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치
KR20210145078A (ko) 2020-05-21 2021-12-01 에이에스엠 아이피 홀딩 비.브이. 다수의 탄소 층을 포함한 구조체 및 이를 형성하고 사용하는 방법
TW202201602A (zh) 2020-05-29 2022-01-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 基板處理方法
CN111863621A (zh) * 2020-06-15 2020-10-30 上海集成电路研发中心有限公司 一种自对准四重图形的制作方法
TW202218133A (zh) 2020-06-24 2022-05-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 形成含矽層之方法
TW202217953A (zh) 2020-06-30 2022-05-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 基板處理方法
KR20220010438A (ko) 2020-07-17 2022-01-25 에이에스엠 아이피 홀딩 비.브이. 포토리소그래피에 사용하기 위한 구조체 및 방법
TW202204662A (zh) 2020-07-20 2022-02-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 用於沉積鉬層之方法及系統
CN112017951B (zh) * 2020-08-07 2022-03-04 福建省晋华集成电路有限公司 图案布局的形成方法
KR20220027026A (ko) 2020-08-26 2022-03-07 에이에스엠 아이피 홀딩 비.브이. 금속 실리콘 산화물 및 금속 실리콘 산질화물 층을 형성하기 위한 방법 및 시스템
USD990534S1 (en) 2020-09-11 2023-06-27 Asm Ip Holding B.V. Weighted lift pin
USD1012873S1 (en) 2020-09-24 2024-01-30 Asm Ip Holding B.V. Electrode for semiconductor processing apparatus
TW202229613A (zh) 2020-10-14 2022-08-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 於階梯式結構上沉積材料的方法
TW202217037A (zh) 2020-10-22 2022-05-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 沉積釩金屬的方法、結構、裝置及沉積總成
TW202223136A (zh) 2020-10-28 2022-06-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 用於在基板上形成層之方法、及半導體處理系統
KR102527983B1 (ko) * 2020-11-04 2023-05-03 엠에이치디 주식회사 반도체 장치의 미세 패턴 형성방법
KR20220076343A (ko) 2020-11-30 2022-06-08 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치의 반응 챔버 내에 배열되도록 구성된 인젝터
CN114639631A (zh) 2020-12-16 2022-06-17 Asm Ip私人控股有限公司 跳动和摆动测量固定装置
TW202231903A (zh) 2020-12-22 2022-08-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 過渡金屬沉積方法、過渡金屬層、用於沉積過渡金屬於基板上的沉積總成
USD980814S1 (en) 2021-05-11 2023-03-14 Asm Ip Holding B.V. Gas distributor for substrate processing apparatus
USD980813S1 (en) 2021-05-11 2023-03-14 Asm Ip Holding B.V. Gas flow control plate for substrate processing apparatus
USD981973S1 (en) 2021-05-11 2023-03-28 Asm Ip Holding B.V. Reactor wall for substrate processing apparatus
USD990441S1 (en) 2021-09-07 2023-06-27 Asm Ip Holding B.V. Gas flow control plate

Family Cites Families (195)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5748237Y2 (zh) 1978-12-28 1982-10-22
US4234362A (en) 1978-11-03 1980-11-18 International Business Machines Corporation Method for forming an insulator between layers of conductive material
JPS5748237A (en) * 1980-09-05 1982-03-19 Nec Corp Manufacture of 2n doubling pattern
US4508579A (en) 1981-03-30 1985-04-02 International Business Machines Corporation Lateral device structures using self-aligned fabrication techniques
US4432132A (en) 1981-12-07 1984-02-21 Bell Telephone Laboratories, Incorporated Formation of sidewall oxide layers by reactive oxygen ion etching to define submicron features
US4419809A (en) 1981-12-30 1983-12-13 International Business Machines Corporation Fabrication process of sub-micrometer channel length MOSFETs
DE3242113A1 (de) 1982-11-13 1984-05-24 Ibm Deutschland Gmbh, 7000 Stuttgart Verfahren zur herstellung einer duennen dielektrischen isolation in einem siliciumhalbleiterkoerper
US4716131A (en) 1983-11-28 1987-12-29 Nec Corporation Method of manufacturing semiconductor device having polycrystalline silicon layer with metal silicide film
US4570325A (en) 1983-12-16 1986-02-18 Kabushiki Kaisha Toshiba Manufacturing a field oxide region for a semiconductor device
JPH0645431B2 (ja) 1984-11-30 1994-06-15 株式会社日立製作所 エスカレ−タ−
US4648937A (en) 1985-10-30 1987-03-10 International Business Machines Corporation Method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer
GB8528967D0 (en) 1985-11-25 1986-01-02 Plessey Co Plc Semiconductor device manufacture
DE3682395D1 (de) 1986-03-27 1991-12-12 Ibm Verfahren zur herstellung von seitenstrukturen.
US5514885A (en) 1986-10-09 1996-05-07 Myrick; James J. SOI methods and apparatus
JPS6435916U (zh) 1987-08-28 1989-03-03
US4838991A (en) 1987-10-30 1989-06-13 International Business Machines Corporation Process for defining organic sidewall structures
US4776922A (en) 1987-10-30 1988-10-11 International Business Machines Corporation Formation of variable-width sidewall structures
DD280851A1 (de) * 1989-03-27 1990-07-18 Dresden Forschzentr Mikroelek Verfahren zur herstellung von graben-speicherzellen
US5328810A (en) 1990-05-07 1994-07-12 Micron Technology, Inc. Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process
US5013680A (en) 1990-07-18 1991-05-07 Micron Technology, Inc. Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography
US5053105A (en) 1990-07-19 1991-10-01 Micron Technology, Inc. Process for creating an etch mask suitable for deep plasma etches employing self-aligned silicidation of a metal layer masked with a silicon dioxide template
US5047117A (en) 1990-09-26 1991-09-10 Micron Technology, Inc. Method of forming a narrow self-aligned, annular opening in a masking layer
DE4034612A1 (de) 1990-10-31 1992-05-07 Huels Chemische Werke Ag Verfahren zur herstellung von methacryloxy- oder acryloxygruppen enthaltenden organosilanen
IT1243919B (it) 1990-11-20 1994-06-28 Cons Ric Microelettronica Procedimento per l'ottenimento di solchi submicrometrici planarizzati in circuiti integrati realizzati con tecnologia ulsi
JPH05343370A (ja) * 1992-06-10 1993-12-24 Toshiba Corp 微細パタ−ンの形成方法
US5330879A (en) 1992-07-16 1994-07-19 Micron Technology, Inc. Method for fabrication of close-tolerance lines and sharp emission tips on a semiconductor wafer
DE4236609A1 (de) 1992-10-29 1994-05-05 Siemens Ag Verfahren zur Erzeugung einer Struktur in der Oberfläche eines Substrats
US5407785A (en) 1992-12-18 1995-04-18 Vlsi Technology, Inc. Method for generating dense lines on a semiconductor wafer using phase-shifting and multiple exposures
US5470661A (en) 1993-01-07 1995-11-28 International Business Machines Corporation Diamond-like carbon films from a hydrocarbon helium plasma
US6042998A (en) 1993-09-30 2000-03-28 The University Of New Mexico Method and apparatus for extending spatial frequencies in photolithography images
KR970007173B1 (ko) 1994-07-14 1997-05-03 현대전자산업 주식회사 미세패턴 형성방법
JPH0855920A (ja) 1994-08-15 1996-02-27 Toshiba Corp 半導体装置の製造方法
JPH0855908A (ja) 1994-08-17 1996-02-27 Toshiba Corp 半導体装置
US5600153A (en) 1994-10-07 1997-02-04 Micron Technology, Inc. Conductive polysilicon lines and thin film transistors
TW366367B (en) 1995-01-26 1999-08-11 Ibm Sputter deposition of hydrogenated amorphous carbon film
US5628917A (en) * 1995-02-03 1997-05-13 Cornell Research Foundation, Inc. Masking process for fabricating ultra-high aspect ratio, wafer-free micro-opto-electromechanical structures
US5795830A (en) 1995-06-06 1998-08-18 International Business Machines Corporation Reducing pitch with continuously adjustable line and space dimensions
KR100190757B1 (ko) 1995-06-30 1999-06-01 김영환 모스 전계 효과 트랜지스터 형성방법
JP3393286B2 (ja) 1995-09-08 2003-04-07 ソニー株式会社 パターンの形成方法
US5789320A (en) 1996-04-23 1998-08-04 International Business Machines Corporation Plating of noble metal electrodes for DRAM and FRAM
TW329539B (en) 1996-07-05 1998-04-11 Mitsubishi Electric Corp The semiconductor device and its manufacturing method
JP3164026B2 (ja) 1996-08-21 2001-05-08 日本電気株式会社 半導体装置及びその製造方法
US5989998A (en) * 1996-08-29 1999-11-23 Matsushita Electric Industrial Co., Ltd. Method of forming interlayer insulating film
US6395613B1 (en) 2000-08-30 2002-05-28 Micron Technology, Inc. Semiconductor processing methods of forming a plurality of capacitors on a substrate, bit line contacts and method of forming bit line contacts
US5998256A (en) 1996-11-01 1999-12-07 Micron Technology, Inc. Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry
US5895740A (en) 1996-11-13 1999-04-20 Vanguard International Semiconductor Corp. Method of forming contact holes of reduced dimensions by using in-situ formed polymeric sidewall spacers
KR100231134B1 (ko) 1997-06-14 1999-11-15 문정환 반도체장치의 배선 형성 방법
US6063688A (en) 1997-09-29 2000-05-16 Intel Corporation Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition
KR100247862B1 (ko) 1997-12-11 2000-03-15 윤종용 반도체 장치 및 그 제조방법
US6143476A (en) 1997-12-12 2000-11-07 Applied Materials Inc Method for high temperature etching of patterned layers using an organic mask stack
US6291334B1 (en) 1997-12-19 2001-09-18 Applied Materials, Inc. Etch stop layer for dual damascene process
US6004862A (en) 1998-01-20 1999-12-21 Advanced Micro Devices, Inc. Core array and periphery isolation technique
JP2975917B2 (ja) 1998-02-06 1999-11-10 株式会社半導体プロセス研究所 半導体装置の製造方法及び半導体装置の製造装置
US5933725A (en) 1998-05-27 1999-08-03 Vanguard International Semiconductor Corporation Word line resistance reduction method and design for high density memory with relaxed metal pitch
US6020255A (en) 1998-07-13 2000-02-01 Taiwan Semiconductor Manufacturing Company Dual damascene interconnect process with borderless contact
US6245662B1 (en) 1998-07-23 2001-06-12 Applied Materials, Inc. Method of producing an interconnect structure for an integrated circuit
US6071789A (en) 1998-11-10 2000-06-06 Vanguard International Semiconductor Corporation Method for simultaneously fabricating a DRAM capacitor and metal interconnections
US6204187B1 (en) 1999-01-06 2001-03-20 Infineon Technologies North America, Corp. Contact and deep trench patterning
US6211044B1 (en) 1999-04-12 2001-04-03 Advanced Micro Devices Process for fabricating a semiconductor device component using a selective silicidation reaction
JP2000307084A (ja) 1999-04-23 2000-11-02 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6110837A (en) 1999-04-28 2000-08-29 Worldwide Semiconductor Manufacturing Corp. Method for forming a hard mask of half critical dimension
US6136662A (en) 1999-05-13 2000-10-24 Lsi Logic Corporation Semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same
JP2000357736A (ja) 1999-06-15 2000-12-26 Toshiba Corp 半導体装置及びその製造方法
JP2001077196A (ja) 1999-09-08 2001-03-23 Sony Corp 半導体装置の製造方法
JP2001110782A (ja) 1999-10-12 2001-04-20 Oki Electric Ind Co Ltd 半導体装置の製造方法
US6362057B1 (en) 1999-10-26 2002-03-26 Motorola, Inc. Method for forming a semiconductor device
US6582891B1 (en) 1999-12-02 2003-06-24 Axcelis Technologies, Inc. Process for reducing edge roughness in patterned photoresist
KR100311050B1 (ko) 1999-12-14 2001-11-05 윤종용 커패시터의 전극 제조 방법
US6573030B1 (en) 2000-02-17 2003-06-03 Applied Materials, Inc. Method for depositing an amorphous carbon layer
US6967140B2 (en) 2000-03-01 2005-11-22 Intel Corporation Quantum wire gate device and method of making same
US6297554B1 (en) 2000-03-10 2001-10-02 United Microelectronics Corp. Dual damascene interconnect structure with reduced parasitic capacitance
US6423474B1 (en) 2000-03-21 2002-07-23 Micron Technology, Inc. Use of DARC and BARC in flash memory processing
JP3805603B2 (ja) 2000-05-29 2006-08-02 富士通株式会社 半導体装置及びその製造方法
JP2002194547A (ja) 2000-06-08 2002-07-10 Applied Materials Inc アモルファスカーボン層の堆積方法
US6632741B1 (en) 2000-07-19 2003-10-14 International Business Machines Corporation Self-trimming method on looped patterns
US6455372B1 (en) 2000-08-14 2002-09-24 Micron Technology, Inc. Nucleation for improved flash erase characteristics
US6348380B1 (en) 2000-08-25 2002-02-19 Micron Technology, Inc. Use of dilute steam ambient for improvement of flash devices
SE517275C2 (sv) 2000-09-20 2002-05-21 Obducat Ab Sätt vid våtetsning av ett substrat
US6335257B1 (en) * 2000-09-29 2002-01-01 Vanguard International Semiconductor Corporation Method of making pillar-type structure on semiconductor substrate
US6667237B1 (en) 2000-10-12 2003-12-23 Vram Technologies, Llc Method and apparatus for patterning fine dimensions
US6534243B1 (en) 2000-10-23 2003-03-18 Advanced Micro Devices, Inc. Chemical feature doubling process
US6926843B2 (en) 2000-11-30 2005-08-09 International Business Machines Corporation Etching of hard masks
US6664028B2 (en) 2000-12-04 2003-12-16 United Microelectronics Corp. Method of forming opening in wafer layer
JP3406302B2 (ja) 2001-01-16 2003-05-12 株式会社半導体先端テクノロジーズ 微細パターンの形成方法、半導体装置の製造方法および半導体装置
US6475867B1 (en) 2001-04-02 2002-11-05 Advanced Micro Devices, Inc. Method of forming integrated circuit features by oxidation of titanium hard mask
US6740594B2 (en) 2001-05-31 2004-05-25 Infineon Technologies Ag Method for removing carbon-containing polysilane from a semiconductor without stripping
US6960806B2 (en) 2001-06-21 2005-11-01 International Business Machines Corporation Double gated vertical transistor with different first and second gate materials
US6522584B1 (en) 2001-08-02 2003-02-18 Micron Technology, Inc. Programming methods for multi-level flash EEPROMs
US6744094B2 (en) 2001-08-24 2004-06-01 Micron Technology Inc. Floating gate transistor with horizontal gate layers stacked next to vertical body
TW497138B (en) 2001-08-28 2002-08-01 Winbond Electronics Corp Method for improving consistency of critical dimension
DE10142590A1 (de) 2001-08-31 2003-04-03 Infineon Technologies Ag Verfahren zur Seitenwandverstärkung von Resiststrukturen und zur Herstellung von Strukturen mit reduzierter Strukturgröße
US7045383B2 (en) 2001-09-19 2006-05-16 BAE Systems Information and Ovonyx, Inc Method for making tapered opening for programmable resistance memory element
JP2003133437A (ja) 2001-10-24 2003-05-09 Hitachi Ltd 半導体装置の製造方法および半導体装置
US7226853B2 (en) 2001-12-26 2007-06-05 Applied Materials, Inc. Method of forming a dual damascene structure utilizing a three layer hard mask structure
TW576864B (en) 2001-12-28 2004-02-21 Toshiba Corp Method for manufacturing a light-emitting device
US6638441B2 (en) 2002-01-07 2003-10-28 Macronix International Co., Ltd. Method for pitch reduction
DE10207131B4 (de) 2002-02-20 2007-12-20 Infineon Technologies Ag Verfahren zur Bildung einer Hartmaske in einer Schicht auf einer flachen Scheibe
US6620715B1 (en) 2002-03-29 2003-09-16 Cypress Semiconductor Corp. Method for forming sub-critical dimension structures in an integrated circuit
US6759180B2 (en) 2002-04-23 2004-07-06 Hewlett-Packard Development Company, L.P. Method of fabricating sub-lithographic sized line and space patterns for nano-imprinting lithography
US20030207584A1 (en) 2002-05-01 2003-11-06 Swaminathan Sivakumar Patterning tighter and looser pitch geometries
US6951709B2 (en) 2002-05-03 2005-10-04 Micron Technology, Inc. Method of fabricating a semiconductor multilevel interconnect structure
US6602779B1 (en) 2002-05-13 2003-08-05 Taiwan Semiconductor Manufacturing Co., Ltd Method for forming low dielectric constant damascene structure while employing carbon doped silicon oxide planarizing stop layer
US6703312B2 (en) 2002-05-17 2004-03-09 International Business Machines Corporation Method of forming active devices of different gatelengths using lithographic printed gate images of same length
US6818141B1 (en) 2002-06-10 2004-11-16 Advanced Micro Devices, Inc. Application of the CVD bilayer ARC as a hard mask for definition of the subresolution trench features between polysilicon wordlines
US6734107B2 (en) 2002-06-12 2004-05-11 Macronix International Co., Ltd. Pitch reduction in semiconductor fabrication
US6559017B1 (en) 2002-06-13 2003-05-06 Advanced Micro Devices, Inc. Method of using amorphous carbon as spacer material in a disposable spacer process
KR100476924B1 (ko) 2002-06-14 2005-03-17 삼성전자주식회사 반도체 장치의 미세 패턴 형성 방법
US6924191B2 (en) 2002-06-20 2005-08-02 Applied Materials, Inc. Method for fabricating a gate structure of a field effect transistor
AU2003280498A1 (en) 2002-06-27 2004-01-19 Advanced Micro Devices, Inc. Method of defining the dimensions of circuit elements by using spacer deposition techniques
US6500756B1 (en) 2002-06-28 2002-12-31 Advanced Micro Devices, Inc. Method of forming sub-lithographic spaces between polysilicon lines
US6835663B2 (en) 2002-06-28 2004-12-28 Infineon Technologies Ag Hardmask of amorphous carbon-hydrogen (a-C:H) layers with tunable etch resistivity
US6689695B1 (en) 2002-06-28 2004-02-10 Taiwan Semiconductor Manufacturing Company Multi-purpose composite mask for dual damascene patterning
US20040018738A1 (en) 2002-07-22 2004-01-29 Wei Liu Method for fabricating a notch gate structure of a field effect transistor
US6913871B2 (en) 2002-07-23 2005-07-05 Intel Corporation Fabricating sub-resolution structures in planar lightwave devices
US6673684B1 (en) 2002-07-31 2004-01-06 Advanced Micro Devices, Inc. Use of diamond as a hard mask material
US6764949B2 (en) 2002-07-31 2004-07-20 Advanced Micro Devices, Inc. Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication
US6800930B2 (en) 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
US6939808B2 (en) 2002-08-02 2005-09-06 Applied Materials, Inc. Undoped and fluorinated amorphous carbon film as pattern mask for metal etch
KR100480610B1 (ko) 2002-08-09 2005-03-31 삼성전자주식회사 실리콘 산화막을 이용한 미세 패턴 형성방법
US6566280B1 (en) 2002-08-26 2003-05-20 Intel Corporation Forming polymer features on a substrate
US6794699B2 (en) 2002-08-29 2004-09-21 Micron Technology Inc Annular gate and technique for fabricating an annular gate
US7205598B2 (en) 2002-08-29 2007-04-17 Micron Technology, Inc. Random access memory device utilizing a vertically oriented select transistor
US6756284B2 (en) 2002-09-18 2004-06-29 Silicon Storage Technology, Inc. Method for forming a sublithographic opening in a semiconductor process
US6706571B1 (en) 2002-10-22 2004-03-16 Advanced Micro Devices, Inc. Method for forming multiple structures in a semiconductor device
JP4034164B2 (ja) 2002-10-28 2008-01-16 富士通株式会社 微細パターンの作製方法及び半導体装置の製造方法
US6888755B2 (en) 2002-10-28 2005-05-03 Sandisk Corporation Flash memory cell arrays having dual control gates per memory cell charge storage element
US7119020B2 (en) 2002-12-04 2006-10-10 Matsushita Electric Industrial Co., Ltd. Method for fabricating semiconductor device
US6686245B1 (en) 2002-12-20 2004-02-03 Motorola, Inc. Vertical MOSFET with asymmetric gate structure
US6916594B2 (en) 2002-12-30 2005-07-12 Hynix Semiconductor Inc. Overcoating composition for photoresist and method for forming photoresist pattern using the same
US7084076B2 (en) 2003-02-27 2006-08-01 Samsung Electronics, Co., Ltd. Method for forming silicon dioxide film using siloxane
US7015124B1 (en) 2003-04-28 2006-03-21 Advanced Micro Devices, Inc. Use of amorphous carbon for gate patterning
US6773998B1 (en) 2003-05-20 2004-08-10 Advanced Micro Devices, Inc. Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning
JP4578785B2 (ja) 2003-05-21 2010-11-10 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US6835662B1 (en) 2003-07-14 2004-12-28 Advanced Micro Devices, Inc. Partially de-coupled core and periphery gate module process
DE10332725A1 (de) * 2003-07-18 2005-02-24 Forschungszentrum Jülich GmbH Verfahren zur selbstjustierenden Verkleinerung von Strukturen
DE10345455A1 (de) 2003-09-30 2005-05-04 Infineon Technologies Ag Verfahren zum Erzeugen einer Hartmaske und Hartmasken-Anordnung
KR100536801B1 (ko) 2003-10-01 2005-12-14 동부아남반도체 주식회사 반도체 소자 및 그 제조 방법
US6867116B1 (en) 2003-11-10 2005-03-15 Macronix International Co., Ltd. Fabrication method of sub-resolution pitch for integrated circuits
JP2005150333A (ja) 2003-11-14 2005-06-09 Sony Corp 半導体装置の製造方法
KR101002928B1 (ko) 2003-11-29 2010-12-27 주식회사 하이닉스반도체 반도체 소자의 미세 라인 형성방법
KR100554514B1 (ko) 2003-12-26 2006-03-03 삼성전자주식회사 반도체 장치에서 패턴 형성 방법 및 이를 이용한 게이트형성방법.
US6998332B2 (en) 2004-01-08 2006-02-14 International Business Machines Corporation Method of independent P and N gate length control of FET device made by sidewall image transfer technique
US6875703B1 (en) 2004-01-20 2005-04-05 International Business Machines Corporation Method for forming quadruple density sidewall image transfer (SIT) structures
US7372091B2 (en) 2004-01-27 2008-05-13 Micron Technology, Inc. Selective epitaxy vertical integrated circuit components
US7064078B2 (en) 2004-01-30 2006-06-20 Applied Materials Techniques for the use of amorphous carbon (APF) for various etch and litho integration scheme
US8486287B2 (en) 2004-03-19 2013-07-16 The Regents Of The University Of California Methods for fabrication of positional and compositionally controlled nanostructures on substrate
US7098105B2 (en) 2004-05-26 2006-08-29 Micron Technology, Inc. Methods for forming semiconductor structures
US6955961B1 (en) 2004-05-27 2005-10-18 Macronix International Co., Ltd. Method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution
DE102005026228B4 (de) 2004-06-08 2010-04-15 Samsung Electronics Co., Ltd., Suwon Transistor vom GAA-Typ und Verfahren zu dessen Herstellung
US7183205B2 (en) 2004-06-08 2007-02-27 Macronix International Co., Ltd. Method of pitch dimension shrinkage
US7473644B2 (en) 2004-07-01 2009-01-06 Micron Technology, Inc. Method for forming controlled geometry hardmasks including subresolution elements
US7074666B2 (en) 2004-07-28 2006-07-11 International Business Machines Corporation Borderless contact structures
KR100704470B1 (ko) 2004-07-29 2007-04-10 주식회사 하이닉스반도체 비결정성 탄소막을 희생 하드마스크로 이용하는반도체소자 제조 방법
US7151040B2 (en) 2004-08-31 2006-12-19 Micron Technology, Inc. Methods for increasing photo alignment margins
US7175944B2 (en) 2004-08-31 2007-02-13 Micron Technology, Inc. Prevention of photoresist scumming
US7442976B2 (en) 2004-09-01 2008-10-28 Micron Technology, Inc. DRAM cells with vertical transistors
US7910288B2 (en) 2004-09-01 2011-03-22 Micron Technology, Inc. Mask material conversion
US7655387B2 (en) 2004-09-02 2010-02-02 Micron Technology, Inc. Method to align mask patterns
US7115525B2 (en) 2004-09-02 2006-10-03 Micron Technology, Inc. Method for integrated circuit fabrication using pitch multiplication
KR100614651B1 (ko) 2004-10-11 2006-08-22 삼성전자주식회사 회로 패턴의 노광을 위한 장치 및 방법, 사용되는포토마스크 및 그 설계 방법, 그리고 조명계 및 그 구현방법
US7208379B2 (en) 2004-11-29 2007-04-24 Texas Instruments Incorporated Pitch multiplication process
US7298004B2 (en) * 2004-11-30 2007-11-20 Infineon Technologies Ag Charge-trapping memory cell and method for production
KR100596795B1 (ko) 2004-12-16 2006-07-05 주식회사 하이닉스반도체 반도체 소자의 캐패시터 및 그 형성방법
US7183142B2 (en) 2005-01-13 2007-02-27 International Business Machines Corporation FinFETs with long gate length at high density
US7271107B2 (en) 2005-02-03 2007-09-18 Lam Research Corporation Reduction of feature critical dimensions using multiple masks
KR100787352B1 (ko) 2005-02-23 2007-12-18 주식회사 하이닉스반도체 하드마스크용 조성물 및 이를 이용한 반도체 소자의 패턴형성 방법
US7253118B2 (en) 2005-03-15 2007-08-07 Micron Technology, Inc. Pitch reduced patterns relative to photolithography features
US7390746B2 (en) 2005-03-15 2008-06-24 Micron Technology, Inc. Multiple deposition for integration of spacers in pitch multiplication process
US7611944B2 (en) 2005-03-28 2009-11-03 Micron Technology, Inc. Integrated circuit fabrication
KR100640639B1 (ko) 2005-04-19 2006-10-31 삼성전자주식회사 미세콘택을 포함하는 반도체소자 및 그 제조방법
US7429536B2 (en) 2005-05-23 2008-09-30 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7547599B2 (en) 2005-05-26 2009-06-16 Micron Technology, Inc. Multi-state memory cell
US7560390B2 (en) 2005-06-02 2009-07-14 Micron Technology, Inc. Multiple spacer steps for pitch multiplication
US7396781B2 (en) 2005-06-09 2008-07-08 Micron Technology, Inc. Method and apparatus for adjusting feature size and position
JP2006351861A (ja) 2005-06-16 2006-12-28 Toshiba Corp 半導体装置の製造方法
TW200705541A (en) 2005-07-25 2007-02-01 Li Bing Huan Manufacturing method of nano-sticker
US7413981B2 (en) 2005-07-29 2008-08-19 Micron Technology, Inc. Pitch doubled circuit layout
US7291560B2 (en) 2005-08-01 2007-11-06 Infineon Technologies Ag Method of production pitch fractionizations in semiconductor technology
US7816262B2 (en) 2005-08-30 2010-10-19 Micron Technology, Inc. Method and algorithm for random half pitched interconnect layout with constant spacing
US7829262B2 (en) 2005-08-31 2010-11-09 Micron Technology, Inc. Method of forming pitch multipled contacts
US7687342B2 (en) 2005-09-01 2010-03-30 Micron Technology, Inc. Method of manufacturing a memory device
US7759197B2 (en) 2005-09-01 2010-07-20 Micron Technology, Inc. Method of forming isolated features using pitch multiplication
US7393789B2 (en) 2005-09-01 2008-07-01 Micron Technology, Inc. Protective coating for planarization
US7572572B2 (en) 2005-09-01 2009-08-11 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7776744B2 (en) 2005-09-01 2010-08-17 Micron Technology, Inc. Pitch multiplication spacers and methods of forming the same
KR101200938B1 (ko) 2005-09-30 2012-11-13 삼성전자주식회사 반도체 장치의 패턴 형성 방법
US7244638B2 (en) 2005-09-30 2007-07-17 Infineon Technologies Ag Semiconductor memory device and method of production
KR100714305B1 (ko) 2005-12-26 2007-05-02 삼성전자주식회사 자기정렬 이중패턴의 형성방법
KR100672123B1 (ko) 2006-02-02 2007-01-19 주식회사 하이닉스반도체 반도체 소자의 미세 패턴 형성방법
US20070210449A1 (en) 2006-03-07 2007-09-13 Dirk Caspary Memory device and an array of conductive lines and methods of making the same
US7351666B2 (en) 2006-03-17 2008-04-01 International Business Machines Corporation Layout and process to contact sub-lithographic structures
US7537866B2 (en) 2006-05-24 2009-05-26 Synopsys, Inc. Patterning a single integrated circuit layer using multiple masks and multiple masking layers
US7825460B2 (en) 2006-09-06 2010-11-02 International Business Machines Corporation Vertical field effect transistor arrays and methods for fabrication thereof
US20080292991A1 (en) 2007-05-24 2008-11-27 Advanced Micro Devices, Inc. High fidelity multiple resist patterning
US7851135B2 (en) 2007-11-30 2010-12-14 Hynix Semiconductor Inc. Method of forming an etching mask pattern from developed negative and positive photoresist layers

Also Published As

Publication number Publication date
EP1794777A2 (en) 2007-06-13
US20060046200A1 (en) 2006-03-02
US8895232B2 (en) 2014-11-25
JP4822077B2 (ja) 2011-11-24
US20110130006A1 (en) 2011-06-02
KR20070067119A (ko) 2007-06-27
EP1794777B1 (en) 2016-03-30
KR100874196B1 (ko) 2008-12-15
US20130302987A1 (en) 2013-11-14
TW200612473A (en) 2006-04-16
JP2008511991A (ja) 2008-04-17
WO2006028705A3 (en) 2006-04-13
CN101044595A (zh) 2007-09-26
US8486610B2 (en) 2013-07-16
WO2006028705A2 (en) 2006-03-16
US7910288B2 (en) 2011-03-22
WO2006028705B1 (en) 2006-06-01
TWI267904B (en) 2006-12-01

Similar Documents

Publication Publication Date Title
CN100521090C (zh) 掩模材料转化
CN101292327B (zh) 形成间距倍增接点的方法
US7390746B2 (en) Multiple deposition for integration of spacers in pitch multiplication process
US8123968B2 (en) Multiple deposition for integration of spacers in pitch multiplication process
US9048194B2 (en) Method for selectively modifying spacing between pitch multiplied structures
US8865598B2 (en) Method for positioning spacers in pitch multiplication
US8011090B2 (en) Method for forming and planarizing adjacent regions of an integrated circuit
US7572572B2 (en) Methods for forming arrays of small, closely spaced features
KR100921588B1 (ko) 포토리소그래피의 피쳐들에 관련된 감소된 피치를 갖는패턴들
US20060263699A1 (en) Methods for forming arrays of a small, closely spaced features
KR20090073157A (ko) 효율적인 피치 멀티플리케이션 프로세스

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant