CN100521162C - Semiconductor structure of display device and its producing method - Google Patents
Semiconductor structure of display device and its producing method Download PDFInfo
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- CN100521162C CN100521162C CNB2007101021698A CN200710102169A CN100521162C CN 100521162 C CN100521162 C CN 100521162C CN B2007101021698 A CNB2007101021698 A CN B2007101021698A CN 200710102169 A CN200710102169 A CN 200710102169A CN 100521162 C CN100521162 C CN 100521162C
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Abstract
The semiconductor structure of display device includes following parts: substrate possesses thin film transistor (TFT) area and pixel capacitance area; TFT is formed on TFT area of substrate, and the TFT includes grid pole, source pole, and drain pole, channel layer, and dielectric layer of grid pole; being formed on pixel capacitance area of substrate, the pixel capacitance is composed of lower pole formed on dielectric layer on substrate, interlayer dielectric layer formed on lower pole, and upper pole formed on the interlayer dielectric layer; the contact plug passes through the interlayer dielectric layer, and the upper pole through the contact plug is connected to the lower pole electrically; forming the capacitance dielectric layer on the upper pole; being connected to the drain pole, the transparence pole is formed on the capacitance dielectric layer of the upper pole. The pixel capacitance area possesses high capacitor store capacity.
Description
Technical field
The present invention relates to a kind of semiconductor structure of display unit, particularly relate to a kind of semiconductor structure with display unit of high aperture and good electric capacity storage capacity.
Background technology
Make Pixel Dimensions dwindle in order to improve exploration on display resolution ratio, the area that can be used for placing storage capacitance (storage capacitor) in the display in each pixel region also must relatively dwindle, to keep aperture ratio of pixels.Therefore, the manufacturer of Thin Film Transistor-LCD seeks the minimized method of the area that holding capacitor is required all the time.
Improving resolution for the amorphous silicon film transistor LCD, is particular importance.That is to say that when the overall dimensions of pixel dwindled, the area of the largest portion of pixel should be to be used to dispose pixel electrode, and was relative, the elemental area that holding capacitor uses should be reduced to minimum.
Yet, in order to improve the resolution of Thin Film Transistor-LCD, but cause the undersized of holding capacitor and can't store necessary capacitance, therefore cause in the display the pixel flicker, color contrast is not good and the problem of crosstalk (cross-talk), and then the performance that influence display shows.
Therefore, the area that how can increase the capacity of holding capacitor simultaneously and increase pixel electrode (in other words, under the situation that does not influence aperture ratio of pixels, increase the capacity of holding capacitor), be very important problem in the current thin film transistor liquid crystal display (TFT-LCD) manufacturing process.
Summary of the invention
In view of this, the purpose of this invention is to provide a kind of semiconductor structure of display unit, it has the pixel capacitance of high capacitor store capacity.In addition, another object of the present invention provides a kind of pixel capacitance, and this pixel capacitance can further have the semiconductor layer of doping and electrically connect with this pixel electrode, as capacitance electrode, further expands the capacitance stores ability of this pixel capacitance.
Another object of the present invention provides a kind of manufacture method of semiconductor structure of display unit, to obtain the semiconductor structure of display unit of the present invention.
For reaching above-mentioned purpose, the semiconductor structure of display unit of the present invention comprises: substrate has thin film transistor region and pixel capacitance district; Thin-film transistor is formed on this thin film transistor region of this substrate, and wherein this thin-film transistor comprises grid, source electrode, drain electrode, channel layer, gate dielectric, source electrode contact bolt, reaches the drain electrode contact bolt; Pixel capacitance is formed on this pixel capacitance district of this substrate, and this pixel capacitance comprises: bottom electrode is formed on the bottom dielectric layer; Interlayer dielectric layer is formed on this bottom electrode; Top electrode is formed on this interlayer dielectric layer; Contact bolt runs through this interlayer dielectric layer, and this top electrode electrically connects via this contact bolt and this bottom electrode; Capacitance dielectric layer is formed on this top electrode; And transparency electrode, electrically connect with this drain electrode contact bolt, and be formed on the capacitance dielectric layer of this top electrode.
The semiconductor structure of display unit wherein also comprises semiconductor layer as mentioned above, be formed on this substrate, and be positioned at this bottom electrode under.
The semiconductor structure of display unit, wherein semiconductor layer and this drain electrode electric connection as mentioned above.
The semiconductor structure of display unit as mentioned above, wherein this semiconductor layer comprises heavily doped semiconductor layer.
The semiconductor structure of display unit as mentioned above, wherein this interlayer dielectric layer comprises and contains oxygen silicide layer, nitrogenous silicide layer, or its lamination.
The semiconductor structure of display unit as mentioned above, wherein this transparency electrode is indium tin oxide (ITO), indium-zinc oxide (IZO), Zinc-aluminium (AZO), zinc oxide (ZnO), gallium nitrogen, gallium indium nitrogen, cadmium sulfide, zinc sulphide, cadmium selenium or zinc selenide.
The semiconductor structure of display unit as mentioned above, wherein the material of this top electrode and this bottom electrode comprises molybdenum, tungsten, aluminium, titanium, chromium or its alloy.
The semiconductor structure of display unit as mentioned above, wherein this grid and this bottom electrode be same material also
Form with identical manufacturing technology steps.
The semiconductor structure of display unit as mentioned above, wherein this source electrode contact bolt and this drain electrode contact bolt and this same material and form of powering on very with identical manufacturing technology steps.
In addition, pixel capacitance structure of the present invention comprises: semiconductor layer is formed on the substrate; The bottom dielectric layer is formed on this semiconductor layer; Bottom electrode is formed on this bottom dielectric layer; Interlayer dielectric layer is formed on this bottom electrode; First contact bolt runs through this interlayer dielectric layer, and electrically connects this bottom electrode; Top electrode is formed on this interlayer dielectric layer, and electrically connects via this first contact bolt and this bottom electrode; Capacitance dielectric layer is formed on this top electrode; Flatness layer is formed on this capacitance dielectric layer, and has opening to expose this capacitance dielectric layer that is positioned at directly over this top electrode; Transparency electrode is formed on the capacitance dielectric layer of this top electrode; And one second contact bolt, running through this bottom dielectric layer, interlayer dielectric layer, capacitance dielectric layer and flatness layer, this transparency electrode is electrically connected to this semiconductor layer via this second contact bolt.
Aforesaid pixel capacitance structure, wherein this semiconductor layer is heavily doped semiconductor layer.
Aforesaid pixel capacitance structure, wherein this interlayer dielectric layer is for containing oxygen silicide, nitrogenous silicide, or its lamination.
Aforesaid pixel capacitance structure, wherein this capacitance dielectric layer is for containing oxygen silicide, nitrogenous silicide, or its lamination.
Aforesaid pixel capacitance structure, wherein this transparency electrode is indium tin oxide (ITO), indium-zinc oxide (IZO), Zinc-aluminium (AZO), zinc oxide (ZnO), gallium nitrogen, gallium indium nitrogen, cadmium sulfide, zinc sulphide, cadmium selenium or zinc selenide.
Aforesaid pixel capacitance structure, wherein the material of this top electrode and this bottom electrode is molybdenum, tungsten, aluminium, titanium, chromium or its alloy.
Aforesaid pixel capacitance structure, wherein this bottom electrode and top electrode constitute first capacitance electrode.
Aforesaid pixel capacitance structure, wherein this semiconductor layer and this transparency electrode constitute second capacitance electrode.
Moreover the manufacture method of the semiconductor structure of display unit of the present invention can comprise: substrate is provided, and definition has thin film transistor region and pixel capacitance district in this substrate; Form first semiconductor layer in this suprabasil thin film transistor region; Form gate dielectric in this substrate; Form grid on the gate dielectric of this thin film transistor region, and form bottom electrode on the gate dielectric in this pixel capacitance district; This first semiconductor layer is carried out heavy doping technology to form source electrode and drain electrode, and the part that is not doped is defined as channel region; Form interlayer dielectric layer in this substrate; Form first and second contact hole to expose this source electrode and drain electrode respectively, reach and form the 3rd contact hole to expose this bottom electrode; Form source electrode contact bolt and drain electrode contact bolt,, and form top electrode, electrically connect via the 3rd contact hole and this bottom electrode respectively via this first and second contact hole and this source electrode and drain electrode electric connection; Form capacitance dielectric layer and flatness layer successively in this substrate; Graphical this capacitance dielectric layer and flatness layer to be forming the 4th contact hole and run through this capacitance dielectric layer and flatness layer exposes this drain electrode contact bolt, and the formation opening runs through this flatness layer and exposes this and be positioned at capacitance dielectric layer directly over the top electrode; And form pixel electrode and insert the 4th contact hole and this opening, and with this drain electrode contact bolt electric connection.
The manufacture method of aforesaid semiconductor structure, wherein this bottom electrode and top electrode constitute first capacitance electrode.
The manufacture method of aforesaid semiconductor structure wherein forms the step of first semiconductor layer in this suprabasil thin film transistor region, also comprises:
Form second semiconductor layer simultaneously in this suprabasil pixel capacitance district.
The manufacture method of aforesaid semiconductor structure, wherein this second semiconductor layer and this pixel electrode constitute second capacitance electrode.
The manufacture method of aforesaid semiconductor structure after forming this second semiconductor layer, also comprises this second semiconductor layer is carried out heavy doping technology.
The manufacture method of aforesaid semiconductor structure, wherein this first semiconductor layer and this second semiconductor layer electrically connect.
The manufacture method of aforesaid semiconductor structure, wherein this first and second semiconductor layer forms with same material and with identical manufacturing technology steps.
The manufacture method of aforesaid semiconductor structure when this first semiconductor layer is carried out heavy doping technology, is carried out this heavy doping technology to this second semiconductor layer simultaneously.
The manufacture method of aforesaid semiconductor structure also comprises:
This first semiconductor layer is carried out light dope technology to form light doping section.
The manufacture method of aforesaid semiconductor structure wherein comprises that to this heavy doping technology and the light dope technology that this first semiconductor layer carries out the use grid defines heavily doped region and light doping section as mask.
The manufacture method of aforesaid semiconductor structure, wherein the 4th contact hole and this opening carry out photoetching process with photomask and are made for using.
The manufacture method of aforesaid semiconductor structure, the photoetching process that wherein forms the 4th contact hole and this opening are to utilize half tone photomask or grey-tone photo.
The manufacture method of aforesaid semiconductor structure, wherein this grid forms with same material and with identical manufacturing technology steps simultaneously with this bottom electrode.
The manufacture method of aforesaid semiconductor structure, wherein this source electrode contact bolt and this drain electrode contact bolt form with same material and with identical manufacturing technology steps simultaneously with this top electrode.
Because in the present invention, utilize pixel electrode to constitute the pixel capacitance electrode, therefore can under the prerequisite that does not influence display area (pixel electrode area), improve the capacitance stores amount.Moreover therefore this first capacitance electrode and this second capacitance electrode can increase considerably the capacitance stores amount at two local electric capacity that form under the situation that does not reduce the pixel electrode aperture opening ratio.In addition, the present invention is when forming this source electrode and drain electrode, can form simultaneously and have the capacitance electrode of heavily doped semiconductor layer as storage capacitance, compare with unadulterated semiconductor layer, this heavily doped semiconductor layer more can increase considerably the capacitance of electric capacity.
For above-mentioned purpose of the present invention, feature can be become apparent, hereinafter the spy enumerates preferred embodiment, and conjunction with figs. elaborates.
Description of drawings
Fig. 1 a-Fig. 1 i is a series of manufacturing process profile, shows the manufacture method of the described display unit semiconductor structure of a preferred embodiment of the present invention.
Fig. 2 shows the cross-sectional view of the described display unit semiconductor structure of another preferred embodiment of the present invention.
Fig. 3 shows the cross-sectional view of the described display unit semiconductor structure of the another preferred embodiment of the present invention.
Wherein, description of reference numerals is as follows:
10: substrate 12: thin film transistor region
14: 16: the first semiconductor layers in pixel capacitance district
21: source electrode 22: drain electrode
23: light doping section 27: gate dielectric
28: grid 29: bottom electrode
30: 31: the first dielectric layers of interlayer dielectric layer
42: the second contact holes of 41: the first contact holes
Contact hole 44 in 43: the three: the source electrode contact bolt
45: drain electrode contact bolt 46: top electrode
47: contact bolt 50: capacitance dielectric layer
55: flatness layer 55 ': residual flatness layer
56: the flatness layer 60 with second thickness: photomask
62: the first openings of 61: the four contact holes
72: the second openings of 71: the five contact holes
73: the upper surface 80 of capacitance dielectric layer: pixel electrode
T1: 2: the second thickness of first thickness t
Embodiment
See also Fig. 1 a to Fig. 1 i, show a preferred embodiment of the semiconductor structure that meets display unit of the present invention, the flow process profile of its manufacturing process.
At first, please refer to Fig. 1 a, a substrate 10 is provided, the upper surface definition of this substrate has a thin film transistor region 12 and a pixel capacitance district 14.Wherein, this substrate is a transparency carrier, can be glass or plastic material.Be formed with on this substrate 10 one first semiconductor layer 16 in this thin film transistor region 12 and one second semiconductor layer 18 in this pixel capacitance district 14.In a preferred embodiment of the present invention, this first semiconductor layer 16 and this second semiconductor layer 18 all form with same material in same manufacturing technology steps simultaneously, and the material that is fit to for example can be polysilicon or amorphous silicon layer.
Then, please refer to Fig. 1 b, this first semiconductor layer 16 is carried out a heavy doping technology, to form one source pole (heavily doped region) 21, drain electrode (heavily doped region) 22.And, the smooth property covered formation one gate dielectric 27 (being also referred to as the bottom dielectric layer), and form a grid 28 on the gate dielectric 27 of channel region 20, and grid 28 is slightly less than channel region 20, and a conductive layer is on the gate dielectric 27 in this pixel capacitance district 14, as a bottom electrode 29.Afterwards, this first semiconductor layer 16 is carried out a light dope technology, to form a light doping section 23; In addition, when this first semiconductor layer 16 is carried out this heavy doping technology, also can carry out this heavy doping technology to this second semiconductor layer 18 simultaneously, to form a heavily doped semiconductor layer 25.In a preferred embodiment of the present invention, heavy doping technology is carried out photoetching process by using a photomask, with definition source electrode 21 and drain electrode 22 heavily doped zones, light doping section then is to utilize grid 28 to carry out light dope technology as mask, to define light doping section 23 in the both sides of channel region 20.Yet, in another preferred embodiment of the present invention, source electrode 21 can utilize grid 28 to carry out heavy doping technology as mask with drain electrode 22 heavily doped zones, afterwards grid 28 is carried out etching, size with reduction of gate 28, then carry out light dope technology with grid 28 as mask once more, with the light doping section 23 of definition channel region 20 both sides.In this preferred embodiment, this grid 28 is to form simultaneously with same material and in a manufacturing technology steps with this bottom electrode 29, and the material that is fit to can be molybdenum (Mo), tungsten (W), aluminium (Al), titanium (Ti), chromium (Cr) or its alloy, or its lamination.The material of this gate dielectric 27 for example can be dielectric material, silica for example, and its thickness can be 100nm in this preferred embodiment between 50nm～200nm.
Then, please refer to Fig. 1 c, the smooth property covered formation one interlayer dielectric layer 30 is on this substrate 10.In this preferred embodiment, this interlayer dielectric layer 30 can be the composite bed that one first dielectric layer 31 and one second dielectric layer 32 are constituted, wherein, this first dielectric layer 31 for example can be silicon nitride or silica, its thickness is between between the 50nm to 300nm, this second dielectric layer 32 for example can be silica or silicon nitride in addition, and its thickness is between between the 50nm to 300nm.
Then, please refer to Fig. 1 d, this interlayer dielectric layer 30 and this gate dielectric 27 are carried out graphically, run through this interlayer dielectric layer 30 and this gate dielectric 27 to expose this source electrode 21 respectively and to drain 22 to form one first contact hole 41 and one second contact hole 42, also form one the 3rd contact hole 43 in addition simultaneously and run through this interlayer dielectric layer 30 to expose the upper surface of this bottom electrode 29.
Then, please refer to Fig. 1 e, comprehensive formation one conductive layer (not shown) is in this substrate 10, and this first contact hole 41 of backfill, second contact hole 42, and the 3rd contact hole 43.Then, this conductive layer is carried out photoetching and etching step, to form one source pole lead (not shown), one source pole contact bolt 44 and a drain electrode contact bolt 45, the back both respectively via this first and second contact hole 41 and 42 with this source electrode 21 and drain 22 electric connections, and form a top electrode 46 simultaneously, electrically connect via the contact bolt 47 that is positioned at the 3rd contact hole 43 and this bottom electrode 29.Wherein, this bottom electrode 29 constitutes first capacitance electrode with top electrode 46, has one first current potential.The material of this top electrode 46 can be identical or different with this bottom electrode 29, for example can be molybdenum (Mo), tungsten (W), aluminium (Al), titanium (Ti), chromium (Cr) or its alloy, or its lamination.
Then, please refer to Fig. 1 f, form a capacitance dielectric layer 50 and a flatness layer 55 successively comprehensively on this substrate 10.Wherein, the material of this capacitance dielectric layer 50 can be dielectric material, for example silica or silicon nitride, and its thickness can be 100nm in this preferred embodiment between 50nm～200nm.The material of this flatness layer 55 can be organic material, and macromolecular material for example, thickness can be between 2000nm～4000nm, can rotary coating, ink-jet or screen painting mode form.
Then, please refer to Fig. 1 g, use a photomask 60 to come this flatness layer 55 of patterning, to form one the 4th contact hole 61 in reaching one first opening 62 on this drain electrode contact bolt 45 on this top electrode 46.It should be noted that, flatness layer 55 behind this patterning need have different thickness in design, the flatness layer 55 that wherein is positioned at drain electrode contact bolt 45 tops is removed fully to form the 4th contact hole 61, to expose the upper surface of the capacitance dielectric layer 50 that is positioned at drain electrode contact bolt 45 tops; Not graphical flatness layer has one first thickness t 1; And the flatness layer 55 that is formed at these top electrode 46 tops is partly removed the flatness layer 56 that has one second thickness t 2 with residual, constitutes this first opening 62.At this, this first thickness t 1 can be between 2000nm～4000nm, and this second thickness t 2 can be between 200nm～500nm scope.This generation type with flatness layer of different-thickness for example can be a photoetching process of utilizing half tone photomask (halftone mask) or grey-tone photo (Gray-tone mask).
Then, please refer to Fig. 1 h, with the flatness layer 55 of this patterning as etching mask, with anisotropic etching this capacitance dielectric layer 50 and flatness layer 55 are carried out etching, to form one the 5th contact hole 71, run through this capacitance dielectric layer 50 and flatness layer 55 exposing this drain electrode contact bolt 45, and form one second opening 72, run through flatness layer 55 to expose the upper surface 73 that is formed at the capacitance dielectric layer 50 on this top electrode 46.The purpose that formation has the flatness layer 55 of this different-thickness is, when carrying out this non-grade to etching step, can make this have the flatness layer 55 of second thickness t 2 flatness layer of these top electrode 46 tops (that is be positioned at) and be removed fully, and on residual fraction flatness layer 55 ' other capacitance dielectric layers 50 outside the 5th contact hole 71 and second opening 72.
At last, please refer to Fig. 1 i, form a graphical transparency conducting layer on this capacitance dielectric layer 50, and insert in the 5th contact hole 71 and second opening 72, as pixel electrode 80.Wherein, the pixel electrode 80 that is formed in the 5th contact hole 71 electrically connects by this drain electrode contact bolt 45 and this drain electrode 22.It should be noted that the pixel electrode 80 that is formed at this second opening interior 72 constitutes second capacitance electrode with this heavily doped second semiconductor layer 25, has one second current potential.This transparency conducting layer can comprise indium tin oxide (ITO), indium-zinc oxide (IZO), Zinc-aluminium (AZO), zinc oxide (ZnO), gallium nitrogen, gallium indium nitrogen, cadmium sulfide, zinc sulphide, cadmium selenium or zinc selenide.So far, finish the manufacture method of the semiconductor structure of display unit of the present invention.As mentioned above, the present invention can minimumly utilize six road photomasks to finish the semiconductor structure with high capacitor store capacity pixel capacitance.
Still please refer to Fig. 1 i, pixel capacitance of the present invention can comprise that this second semiconductor layer 25 is formed on this substrate 10; This bottom dielectric layer (gate dielectric) 27 is formed on this second semiconductor layer 27; This bottom electrode 29 is formed on this bottom dielectric layer 27; This interlayer dielectric layer 30 is formed on this bottom electrode 29; This contact bolt 47 runs through this interlayer dielectric layer 30, and electrically connects this bottom electrode 29; This top electrode 46 is formed on this interlayer dielectric layer 30, and electrically connects via this contact bolt 47 and this bottom electrode 29; This capacitance dielectric layer 50 is formed on this top electrode 46; This flatness layer 55 is formed on this capacitance dielectric layer 50, and has second opening 72 and expose this capacitance dielectric layer 50 that is positioned at positive 46 tops of this top electrode; This transparency electrode 80 is formed on the capacitance dielectric layer 50 of this top electrode 46; And this transparency electrode 80 is electrically connected to drain electrode 22 and this second semiconductor layer 25 via drain electrode contact bolt 45.
It should be noted that because in the present invention, utilize pixel electrode to constitute a pixel capacitance electrode, therefore can under the prerequisite that does not influence display area (pixel electrode area), improve the capacitance stores amount.Moreover therefore this first capacitance electrode and this second capacitance electrode can increase considerably the capacitance stores amount at two local electric capacity that form under the situation that does not reduce the pixel electrode aperture opening ratio.In addition, the present invention is when forming this source electrode and drain electrode, can form one simultaneously and have the capacitance electrode of heavily doped semiconductor layer as storage capacitance, compare with unadulterated semiconductor layer, this heavily doped semiconductor layer more can increase considerably the capacitance of electric capacity.
According to another preferred embodiment of the present invention, please refer to Fig. 2, this second semiconductor layer also can be and does not carry out heavily doped semiconductor layer 33, because can be via the thickness of adjusting capacitance dielectric layer 50, or selection high dielectric constant materials, can under the prerequisite that does not influence display area (pixel electrode glazed area), improve the capacitance stores amount.In addition, according to other preferred embodiments of the present invention, please refer to Fig. 3, also can only utilize this top electrode 46 to constitute this pixel capacitance with this pixel electrode 80, similarly, because can be via the thickness of adjusting capacitance dielectric layer 50, or select high dielectric constant materials, can under the prerequisite that does not influence display area (pixel electrode glazed area), improve the capacitance stores amount.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those of ordinary skills; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking the scope that claim defined of enclosing.
Claims (15)
1. the manufacture method of the semiconductor structure of a display unit comprises:
Substrate is provided, and definition has thin film transistor region and pixel capacitance district in this substrate;
Form first semiconductor layer in this suprabasil thin film transistor region, second semiconductor layer that formation simultaneously and this first semiconductor layer electrically connect is in this suprabasil pixel capacitance district;
Form gate dielectric in this substrate;
Form grid on the gate dielectric of this thin film transistor region, and form bottom electrode on the gate dielectric in this pixel capacitance district;
This first semiconductor layer is carried out heavy doping technology to form source electrode and drain electrode, and the part that is not doped is defined as channel region;
Form interlayer dielectric layer in this substrate;
Form first and second contact hole to expose this source electrode and drain electrode respectively, reach and form the 3rd contact hole to expose this bottom electrode;
Form source electrode contact bolt and drain electrode contact bolt, respectively via this first and second contact hole and this source electrode and this drain electrode electric connection, and formation top electrode, electrically connect via the 3rd contact hole and this bottom electrode, wherein this source electrode contact bolt and this drain electrode contact bolt form with same material and with identical manufacturing technology steps simultaneously with this top electrode;
Form capacitance dielectric layer and flatness layer successively in this substrate;
Carry out a photoetching process, utilize graphical this capacitance dielectric layer of half tone photomask or grey-tone photo and flatness layer to form the 4th contact hole, run through this capacitance dielectric layer and flatness layer to expose this drain electrode contact bolt, and form opening, run through this flatness layer and be positioned at capacitance dielectric layer directly over the top electrode to expose this; And
Form pixel electrode, insert the 4th contact hole and this opening, and electrically connect with this drain electrode.
2. the manufacture method of semiconductor structure as claimed in claim 1, wherein this bottom electrode and top electrode constitute first capacitance electrode.
3. the manufacture method of semiconductor structure as claimed in claim 1, wherein this second semiconductor layer and this pixel electrode constitute second capacitance electrode.
4. the manufacture method of semiconductor structure as claimed in claim 1 wherein after forming this second semiconductor layer, also comprises this second semiconductor layer is carried out heavy doping technology.
5. the manufacture method of semiconductor structure as claimed in claim 1, wherein this first and second semiconductor layer forms with same material and with identical manufacturing technology steps.
6. the manufacture method of semiconductor structure as claimed in claim 1 wherein when this first semiconductor layer is carried out heavy doping technology, is carried out this heavy doping technology to this second semiconductor layer simultaneously.
7. the manufacture method of semiconductor structure as claimed in claim 1 wherein also comprises:
This first semiconductor layer is carried out light dope technology to form light doping section.
8. the manufacture method of semiconductor structure as claimed in claim 7 wherein comprises that to this heavy doping technology and the light dope technology that this first semiconductor layer carries out the use grid defines heavily doped region and light doping section as mask.
9. the manufacture method of semiconductor structure as claimed in claim 1, wherein this grid forms with same material and with identical manufacturing technology steps simultaneously with this bottom electrode.
10. the semiconductor structure of a display unit comprises at least:
Substrate has thin film transistor region and pixel capacitance district;
Thin-film transistor, source electrode contact bolt and drain electrode contact bolt, be formed on this thin film transistor region of this substrate, this thin-film transistor comprises grid, source electrode, drain electrode, channel layer, reaches gate dielectric, and this source electrode contact bolt and this drain electrode contact bolt electrically connect this source electrode and this drain electrode respectively;
Pixel capacitance is formed on this pixel capacitance district of this substrate, and this pixel capacitance comprises:
Semiconductor layer is formed on this substrate and electrically connects with this drain electrode;
The bottom dielectric layer is formed on this semiconductor layer;
Bottom electrode, be formed on the bottom dielectric layer and be positioned at this semiconductor layer directly over;
Interlayer dielectric layer is formed on this substrate and this bottom electrode;
Top electrode is formed on this interlayer dielectric layer, and this top electrode and this bottom electrode electrically connect, wherein this source electrode contact bolt and this drain electrode contact bolt and this same material and with identical manufacturing technology steps formation of powering on very;
Capacitance dielectric layer is formed on this substrate and this top electrode;
Flatness layer is formed on this capacitance dielectric layer, and has opening to expose this capacitance dielectric layer that is positioned at directly over this top electrode; And
Transparency electrode is formed on the capacitance dielectric layer of this top electrode, and electrically connects with this drain electrode contact bolt.
11. as the semiconductor structure of display unit as described in the claim 10, wherein this semiconductor layer comprises heavily doped semiconductor layer.
12. as the semiconductor structure of display unit as described in the claim 10, wherein this interlayer dielectric layer comprises and contains oxygen silicide layer, nitrogenous silicide layer, or its lamination.
13. as the semiconductor structure of display unit as described in the claim 10, wherein this transparency electrode is indium tin oxide, indium-zinc oxide, Zinc-aluminium, zinc oxide, gallium nitrogen, gallium indium nitrogen, cadmium sulfide, zinc sulphide, cadmium selenium or zinc selenide.
14. as the semiconductor structure of display unit as described in the claim 10, wherein the material of this top electrode and this bottom electrode comprises molybdenum, tungsten, aluminium, titanium, chromium or its alloy.
15. as the semiconductor structure of display unit as described in the claim 10, wherein this grid and this bottom electrode are same material and form with identical manufacturing technology steps.
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| CN103296030B (en) * | 2012-07-25 | 2015-12-09 | 上海天马微电子有限公司 | TFT-LCD array substrate |
| CN104298034B (en) * | 2014-09-22 | 2018-07-17 | 京东方科技集团股份有限公司 | A kind of display panel |
| CN107450245B (en) * | 2017-09-18 | 2020-02-14 | 深圳市华星光电技术有限公司 | Array substrate and display panel |
| US10615184B2 (en) | 2017-11-08 | 2020-04-07 | Shenzhen China Star Optoelectronics Technology Co., Ltd | Array substrate and display panel |
| CN109119440B (en) * | 2018-07-20 | 2020-12-25 | Tcl华星光电技术有限公司 | OLED backboard and manufacturing method thereof |
| CN109256396A (en) * | 2018-09-04 | 2019-01-22 | 京东方科技集团股份有限公司 | A kind of translucent display substrate and transparent display panel |
| KR20200050266A (en) * | 2018-11-01 | 2020-05-11 | 엘지디스플레이 주식회사 | Panel, electronic device and transistor |
| CN111584577A (en) | 2020-05-14 | 2020-08-25 | 深圳市华星光电半导体显示技术有限公司 | Display panel and manufacturing method thereof |
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