CN100524721C - Chip packaging structure - Google Patents

Chip packaging structure Download PDF

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Publication number
CN100524721C
CN100524721C CNB2007100073106A CN200710007310A CN100524721C CN 100524721 C CN100524721 C CN 100524721C CN B2007100073106 A CNB2007100073106 A CN B2007100073106A CN 200710007310 A CN200710007310 A CN 200710007310A CN 100524721 C CN100524721 C CN 100524721C
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CN
China
Prior art keywords
opening
chip
fluting
packaging structure
base plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2007100073106A
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Chinese (zh)
Other versions
CN101226911A (en
Inventor
林鸿村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chipmos Technologies Inc
Original Assignee
Chipmos Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipmos Technologies Inc filed Critical Chipmos Technologies Inc
Priority to CNB2007100073106A priority Critical patent/CN100524721C/en
Publication of CN101226911A publication Critical patent/CN101226911A/en
Application granted granted Critical
Publication of CN100524721C publication Critical patent/CN100524721C/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

Disclosed is a chip package structure, comprising a circuit substrate, a chip, an adhesion coating, a plurality of leading wires and a seal. The circuit substrate is provided with a first surface, a second surface, a slot and a welding shield layer, wherein the welding shield layer is disposed on the first surface, and the welding shield layer is provided with a first opening and a second opening, which respectively expose to a portion of the first surface and are respectively located at the bilateral sides along the length direction of the slot. The chip is disposed on the first surface, and at least covers a portion of the slot, a portion of the first opening and a portion of the second opening. The adhesion coating is disposed between the chip and the circuit substrate, and is located at the bilateral sides of the slot, the first opening and the second opening. The leading wires are connected with the chip and the second surface of the circuit substrate through the slot. The seal coats the chip, the adhesion coating, the leading wires and a portion of the circuit substrate, further, the seal is filled into the slot, the first opening and the second opening. Therefore, compared with the prior art, the chip package structure is provided with relatively fine reliability under the condition of testing reliability.

Description

Chip-packaging structure
Technical field
The invention relates to a kind of semiconductor structure, and particularly relevant for a kind of chip-packaging structure.
Background technology
In semiconductor industry, (integrated circuits, production IC) mainly can be divided into three phases to integrated circuit: the making (IC process) of the design of integrated circuit (IC design), integrated circuit and the encapsulation (IC package) of integrated circuit.
In the making of integrated circuit, chip (chip) is to finish via wafer (wafer) making, formation integrated circuit and cut crystal steps such as (wafer sawing).Wafer has an active face (activesurface), the surface with active element (active device) of its general reference wafer.After the integrated circuit of wafer inside was finished, the active face of wafer also disposed a plurality of weld pads (bonding pad), can outwards be electrically connected at a carrier (ca rrier) via these weld pads so that finally cut formed chip by wafer.Carrier for example is a lead frame (leadframe) or a base plate for packaging (packagesubstrate).The mode that chip can routing engages (wire bonding) or flip chip bonding (flip chip bonding) is connected on the carrier, makes these weld pads of chip can be electrically connected at the contact of carrier, to constitute a chip-packaging structure.
Figure 1A is the profile of existing chip encapsulating structure, and Figure 1B is the vertical view of partial component of the existing chip encapsulating structure of Figure 1A.Please also refer to Figure 1A and Figure 1B, for convenience of explanation, Figure 1B does not show chip 120, and chip 120 is represented by dotted lines.In addition, the circuit base plate 110 of Figure 1B only illustrates the subregion.
Please also refer to Figure 1A and Figure 1B, existing chip encapsulating structure 100 comprises a circuit base plate 110, a chip 120, an adhesion coating 130, many leads 140, a sealing 150 and a plurality of soldered balls 160.Circuit base plate 110 has a first surface 110a, a second surface 110b and a fluting 112, and chip 120 is disposed on the first surface 110a, and the cover part slots 112 at least.In addition, adhesion coating 130 is disposed between chip 120 and the circuit base plate 110, and is positioned at the both sides of fluting 112, and chip 120 is fixed on the circuit base plate 110 via adhesion coating 130.Lead 140 connects the second surface 110b of chip 120 and circuit base plate 110 via fluting 112.Sealing 150 coating chips 120, adhesion coating 130, lead 140 and partial line base board 110, and fluting 112 is also inserted in sealing 150.Soldered ball 160 is disposed on the second surface 110b of chip 130.
Because adhesion coating 130 is different with the material character of sealing 150, therefore work as this kind existing chip encapsulating structure 100 under the situation of reliability test, the regional A among Figure 1B is damaged easily than other zone.
Fig. 2 is the vertical view of the partial component of another kind of existing chip encapsulating structure.Please refer to Fig. 2, for convenience of explanation, Fig. 2 does not show chip 120, and chip 120 is represented by dotted lines.In addition, the circuit base plate 110 of Fig. 2 only illustrates the subregion.
Please refer to Fig. 2, in order to reduce the possibility that is damaged as the regional A among Figure 1B, in this kind existing chip encapsulating structure (shown in Figure 1A), this adhesion coating 130a exposes the circuit base plate 110 of regional A, just so sealing 150 can insert this regional A.Yet in order to make sealing 150 can be easy to flow into this regional A, the thickness of this adhesion coating 130a must increase, to increase the distance of 110 of chip 120 and circuit base plates.In other words, this kind existing chip encapsulating structure has higher material cost.
Summary of the invention
In view of this, the present invention provides a kind of chip-packaging structure for the problems referred to above that solve prior art, and this chip-packaging structure can increase reliability.
The present invention proposes a kind of chip-packaging structure, and it comprises a circuit base plate, a chip, an adhesion coating, many first leads and a sealing.Circuit base plate has a first surface, a second surface, one first fluting and a solder mask, wherein solder mask is disposed on the first surface, and solder mask has one first opening and one second opening, it exposes the part first surface respectively, and lays respectively at the both sides of the length direction of first fluting.Chip configuration is on first surface, and cover part first fluting, part first opening and part second opening at least.Adhesion coating is disposed between chip and the circuit base plate, and is positioned at both sides, the both sides of first opening and the both sides of second opening of first fluting, and chip is fixed on the circuit base plate via adhesion coating.First lead connects the second surface of chip and circuit base plate via first fluting.Sealant covers chip, adhesion coating, first lead and partial line base board, and first fluting, first opening and second opening are also inserted in sealing.
In one embodiment of this invention, first opening is connected with first fluting respectively with second opening.
In one embodiment of this invention, solder mask also has one the 3rd opening, and it exposes the part first surface of the both sides of first fluting and first length direction of slotting.
In one embodiment of this invention, first opening is connected with the 3rd opening respectively with second opening.
In one embodiment of this invention, the shape of first opening and second opening comprises rectangle.
In one embodiment of this invention, the length direction of first opening becomes vertical with the length direction of first fluting, and the length direction of second opening becomes vertical with the length direction of first fluting.
In one embodiment of this invention, the line of first opening and second opening is by the central authorities of first fluting.
In one embodiment of this invention, chip-packaging structure also comprises a plurality of soldered balls, and it is disposed on the second surface.
In one embodiment of this invention, chip-packaging structure also comprises many second leads, and circuit base plate also has a plurality of second flutings, and it lays respectively at the outside of adhesion coating, and wherein second lead connects the second surface of chip and circuit base plate via second fluting.
In one embodiment of this invention, adhesion coating can be B rank glue materials.
Based on above-mentioned, because the present invention will form first opening and second opening in solder mask, so that sealing can be flowed into, therefore compared to prior art, under the situation of reliability test, this kind chip-packaging structure has better reliability degree.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. elaborates, wherein:
Figure 1A is the profile of existing chip encapsulating structure.
Figure 1B is the vertical view of partial component of the existing chip encapsulating structure of Figure 1A.
Fig. 2 is the vertical view for the partial component of another kind of existing chip encapsulating structure.
Fig. 3 A is the profile according to a kind of chip-packaging structure of the first embodiment of the present invention.
Fig. 3 B is the vertical view of partial component of the chip-packaging structure of Fig. 3 A.
Fig. 4 is the vertical view according to the partial component of a kind of chip-packaging structure of the second embodiment of the present invention.
The main element symbol description is as follows among the figure:
100: the existing chip encapsulating structure
110: circuit base plate
120: chip
130,130a: adhesion coating
140: lead
150: sealing
160: soldered ball
110a: first surface
110b: second surface
112: fluting
200: chip-packaging structure
210: circuit base plate
210a: first surface
210b: second surface
212: solder mask
212a: first opening
212b: second opening
212c: the 3rd opening
214a: first fluting
214b: second fluting
220: chip
230: adhesion coating
240a: first lead
240b: second lead
250: sealing
260: soldered ball
Embodiment
First embodiment
Fig. 3 A is the profile according to a kind of chip-packaging structure of the first embodiment of the present invention, and Fig. 3 B is the vertical view of partial component of the chip-packaging structure of Fig. 3 A.Please refer to Fig. 3 A and Fig. 3 B, for convenience of explanation, Fig. 3 B does not show chip 220, and chip 220 is represented by dotted lines.In addition, the circuit base plate 210 of Fig. 3 B only illustrates the subregion.
Please refer to Fig. 3 A and Fig. 3 B, the chip-packaging structure 200 of present embodiment comprises a circuit base plate 210, a chip 220, an adhesion coating 230, many first lead 240a and a sealing 250.Circuit base plate 210 has a first surface 210a, a second surface 210b, one first a fluting 214a and a solder mask 212, and wherein solder mask 212 is disposed on the first surface 210a.In addition, solder mask 212 has one first opening 212a and one second opening 212b, and it exposes part first surface 210a respectively, and lays respectively at the both sides of the length direction of the first fluting 214a.In the present embodiment, the first opening 212a and the second opening 212b lay respectively at the left and right sides of the first fluting 214a.In addition, the first fluting 214a can be rectangle or other shapes.
Please continue with reference to figure 3A and Fig. 3 B, chip 220 is disposed on the first surface 210a, and cover part first fluting 214a, part first opening 212a and the part second opening 212b at least.In addition, adhesion coating 230 is disposed between chip 220 and the circuit base plate 210, and is positioned at both sides, the both sides of the first opening 212a and the both sides of the second opening 212b of the first fluting 214a, and chip 220 is fixed on the circuit base plate 210 via adhesion coating 230.The first lead 240a connects the second surface 210b of chip 220 and circuit base plate 210 via the first fluting 214a.In addition, adhesion coating 230 can be B rank glue materials.
Sealing 250 coating chips 220, adhesion coating 230, the first lead 240a and partial line base board 210, and first fluting 214a, the first opening 212a and the second opening 212b also inserted in sealing 250.In addition, in order to make chip 220 to electrically connect with the external world, chip-packaging structure also can comprise a plurality of soldered balls 260, and it is disposed on the second surface 210b.Moreover, in order to increase the electric connection quantity of chip 220 and circuit base plate 210, chip-packaging structure also can comprise many second lead 240b, and circuit base plate 210 also has a plurality of second fluting 214b, it lays respectively at the outside of adhesion coating 230, and wherein the second lead 240b connects the second surface 210b of chip 220 and circuit base plate 210 via the second fluting 214b.
Because sealing 250 can be inserted the first opening 212a and the second opening 212b, therefore compared to prior art, under reliability test, this chip-packaging structure 200 is difficult for producing damage.In other words, compared to prior art, this kind chip-packaging structure 200 has better reliability degree.In addition, compared to the thicker adhesion coating that prior art adopted, in order to flowing of sealing, the thinner thickness of the adhesion coating 230 of the chip-packaging structure 200 of present embodiment, so the chip-packaging structure 200 of present embodiment has lower material cost.
In the present embodiment, the first opening 212a and the second opening 212b are rectangle, yet in other embodiments, the first opening 212a and the second opening 212b can be circular, oval or other shapes, so that allow sealing 250 insert.In addition, in the present embodiment, insert the first opening 212a and the second opening 212b for the ease of sealing 250, the first opening 212a is connected with the first fluting 214a respectively with the second opening 212b.Yet in other embodiments, the first opening 212a or the second opening 212b can not be connected with the first fluting 214a yet.
In the present embodiment, the length direction of the first opening 212a becomes vertical with the length direction of the first fluting 214a, and the length direction of the second opening 212b becomes vertical with the length direction of the first fluting 214a.Yet in other embodiments, the length direction of the length direction of the first opening 212a or the second opening 212b also can become other angles with the first fluting 214a.In addition, the line of the first opening 212a and the second opening 212b is by the central authorities of the first fluting 214a.Yet in other embodiments, the line of the first opening 212a and the second opening 212b also can be by other zones of the first fluting 214a.
Second embodiment
Fig. 4 is the vertical view according to the partial component of a kind of chip-packaging structure of the second embodiment of the present invention.Please refer to Fig. 4, for convenience of explanation, Fig. 4 does not show chip 220, and chip 220 is represented by dotted lines.In addition, the circuit base plate 210 of Fig. 4 only illustrates the subregion.
Please refer to Fig. 4, present embodiment is similar to first embodiment, its difference is: the solder mask 212 of present embodiment also has one the 3rd opening 212c, and it exposes the slot part first surface 210a of both sides of length direction of 214a of the first fluting 214a and first.In addition, in order to make the sealing 250 easier first opening 212a and the second opening 212b of inserting, the first opening 212a can be to be connected with the 3rd opening 212c respectively with the second opening 212b.In other words, sealing 250 can flow in the first opening 212a and the second opening 212b via first fluting 214a and the 3rd opening 212c.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing various modifications and replacement, so protection scope of the present invention is when with being as the criterion that appending claims was defined.

Claims (10)

1. chip-packaging structure is characterized in that comprising:
One circuit base plate, have a first surface, a second surface, one first fluting and a solder mask, wherein said solder mask is disposed on the described first surface, and described solder mask has one first opening and one second opening, expose the described first surface of part respectively, and lay respectively at the both sides of the length direction of described first fluting;
One chip is disposed on the described first surface, and described first fluting in cover part, described first opening of part and described second opening of part at least;
One adhesion coating is disposed between described chip and the described circuit base plate, and is positioned at both sides, the both sides of described first opening and the both sides of described second opening of described first fluting, and described chip is fixed on the described circuit base plate via described adhesion coating;
Many first leads are via the described second surface of described first fluting described chip of connection and described circuit base plate; And
One sealing coats described chip, described adhesion coating, described first lead and the described circuit base plate of part, and described first fluting, described first opening and described second opening are also inserted in described sealing.
2. chip-packaging structure as claimed in claim 1 is characterized in that, described first opening is connected with described first fluting respectively with described second opening.
3. chip-packaging structure as claimed in claim 1 is characterized in that, described solder mask also has one the 3rd opening, exposes the described first surface of part of the both sides of described first fluting and described first length direction of slotting.
4. chip-packaging structure as claimed in claim 3 is characterized in that, described first opening is connected with described the 3rd opening respectively with described second opening.
5. chip-packaging structure as claimed in claim 1 is characterized in that, the shape of described first opening and described second opening comprises rectangle.
6. chip-packaging structure as claimed in claim 5 is characterized in that, the length direction of described first opening becomes vertical with the length direction of described first fluting, and the length direction of described second opening becomes vertical with the length direction of described first fluting.
7. chip-packaging structure as claimed in claim 1 is characterized in that, the line of described first opening and described second opening is by the central authorities of described first fluting.
8. chip-packaging structure as claimed in claim 1 is characterized in that also comprising a plurality of soldered balls, is disposed on the described second surface.
9. chip-packaging structure as claimed in claim 1, it is characterized in that also comprising many second leads, and described circuit base plate also has a plurality of second flutings, lay respectively at the outside of described adhesion coating, described second lead connects the described second surface of described chip and described circuit base plate via described second fluting.
10. chip-packaging structure as claimed in claim 1 is characterized in that, described adhesion coating comprises B rank glue material.
CNB2007100073106A 2007-01-19 2007-01-19 Chip packaging structure Expired - Fee Related CN100524721C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB2007100073106A CN100524721C (en) 2007-01-19 2007-01-19 Chip packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB2007100073106A CN100524721C (en) 2007-01-19 2007-01-19 Chip packaging structure

Publications (2)

Publication Number Publication Date
CN101226911A CN101226911A (en) 2008-07-23
CN100524721C true CN100524721C (en) 2009-08-05

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Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2007100073106A Expired - Fee Related CN100524721C (en) 2007-01-19 2007-01-19 Chip packaging structure

Country Status (1)

Country Link
CN (1) CN100524721C (en)

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Publication number Publication date
CN101226911A (en) 2008-07-23

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