CN100525107C - Buffer and a data driving circuit using the same - Google Patents
Buffer and a data driving circuit using the same Download PDFInfo
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- CN100525107C CN100525107C CNB2006100583814A CN200610058381A CN100525107C CN 100525107 C CN100525107 C CN 100525107C CN B2006100583814 A CNB2006100583814 A CN B2006100583814A CN 200610058381 A CN200610058381 A CN 200610058381A CN 100525107 C CN100525107 C CN 100525107C
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- 239000000872 buffer Substances 0.000 title claims abstract description 89
- 239000003990 capacitor Substances 0.000 claims abstract description 123
- 230000004044 response Effects 0.000 claims abstract description 11
- 238000005070 sampling Methods 0.000 description 6
- 230000008859 change Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000003139 buffering effect Effects 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009897 systematic effect Effects 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
Abstract
A buffer and organic light emitting display with data driving circuit using the buffer is provided. A buffer comprises a first capacitor for receiving an analog voltage; a first inverter having an input terminal connected to the first capacitor; a second inverter having an input terminal connected to an output terminal of the first inverter through a second capacitor; a third capacitor connected to an output terminal of the second inverter; a first transistor for controlling a current which flows from a first power source to a data line so that the buffer output voltage is supplied to the data line in response to a control signal supplied to the third transistor which is connected between the data line and the first capacitor.
Description
The application requires 2005-27305 number and the interests of 2005-27306 korean patent application in the submission of Korea S Department of Intellectual Property on March 31st, 2005, and it openly is contained in this by reference.
Technical field
The data drive circuit that the present invention relates to a kind of buffer and organic light emitting display and adopt this buffer, specifically, relate to a kind of no matter transistorized threshold voltage how the buffer and the organic light emitting display of output voltage and the data drive circuit that adopts this buffer can both be provided accurately.
Background technology
The all little various flat-panel monitors of weight and volume have been developed than CRT (cathode ray tube).Flat-panel monitor comprises LCD, electric field transmitted display, plasma display and organic light emitting display etc.The organic light emitting display utilization presents image by the compound and luminous Organic Light Emitting Diode in electronics and hole.Organic light emitting display is used to produce data-signal from the input data of external source, and shows the image with expectation brightness by utilizing at least data drive circuit and data wire that the data-signal that produces is offered pixel.
Data drive circuit will be imported data and be converted to the voltage corresponding with the GTG value, and the voltage of conversion is provided to data wire as data-signal by buffer.Each pixel all receive with from the corresponding electric current of the voltage of drive circuit.As a result, the Organic Light Emitting Diode in each pixel comes luminous according to the electric current that self receives, thereby shows predetermined picture.
In above-mentioned data drive circuit, buffer should offer data-signal pixel and do not have pressure drop between the input and output of buffer.Yet traditional buffer provides the data-signal with pressure drop, and this pressure drop is corresponding with transistorized threshold voltage.Thus, it is so much that the voltage of data-signal has reduced transistorized threshold voltage, and result, pixel can not show the image with expectation brightness.
Summary of the invention
Therefore, an aspect of specific embodiment provides a kind of buffer, and this buffer does not produce the output with transistor threshold pressure drop.
An embodiment has buffer, and this buffer comprises: first capacitor, comprise the first capacitor end and the second capacitor end, and this first capacitor is formed at the first capacitor termination and receives aanalogvoltage, and wherein, this aanalogvoltage is the input to buffer; First inverter has the first input end and first output, and first input end is connected to the second capacitor end of first capacitor; Second capacitor has the 3rd capacitor end and the 4th capacitor end, and the 3rd capacitor end is connected to first output of first inverter; Second inverter has second input and second output, and second input is connected to the 4th capacitor end of second capacitor; The 3rd capacitor has the 5th capacitor end and the 6th capacitor end, and the 5th capacitor end is connected to second output of second inverter; The first transistor, be connected to the 6th capacitor end of the 3rd capacitor, this the first transistor is configured to Control current flowing from first power supply to data wire, make buffer voltagc be provided to data wire, wherein, the first transistor voltage that is configured to respond the 3rd capacitor and provides comes Control current; Transistor seconds is connected to the first capacitor end of the data wire and first capacitor.
Another embodiment has data drive circuit, this data drive circuit comprises D-A converter and a plurality of buffer, wherein, the place value that D-A converter is configured to the response data input produces aanalogvoltage, each buffer is configured to provide aanalogvoltage to data wire, each buffer comprises: first capacitor, comprise the first capacitor end and the second capacitor end, this first capacitor is formed at the first capacitor termination and receives aanalogvoltage, wherein, this aanalogvoltage is the input to buffer; First inverter has the first input end and first output, and first input end is connected to the second capacitor end of first capacitor; Second capacitor has the 3rd capacitor end and the 4th capacitor end, and the 3rd capacitor end is connected to first output of first inverter; Second inverter has second input and second output, and second input is connected to the 4th capacitor end of second capacitor; The 3rd capacitor has the 5th capacitor end and the 6th capacitor end, and the 5th capacitor end is connected to second output of second inverter; The first transistor, be connected to the 6th capacitor end of the 3rd capacitor, this first transistor is configured to Control current flowing from first power supply to data wire, makes buffer voltagc be provided to data wire, wherein, the first transistor voltage that is configured to respond the 3rd capacitor and provides comes Control current; Transistor seconds is connected to the first capacitor end of the data wire and first capacitor.
Description of drawings
In conjunction with the accompanying drawings, these of specific embodiment and/or others and advantage will become clear from following description and be easier to and understand, in the accompanying drawings:
Fig. 1 is the schematic diagram that illustrates according to the organic light emitting display of an embodiment;
Fig. 2 is the block diagram that an embodiment of the data drive circuit of describing among Fig. 1 is shown;
Fig. 3 is the block diagram that another embodiment of the data drive circuit of describing among Fig. 1 is shown;
Fig. 4 is the schematic circuit according to the structure of the buffer of an embodiment;
Fig. 5 is the sequential chart that the control signal that is provided to the buffer of describing among Fig. 4 is shown;
Fig. 6 is the sequential chart of magnitude of voltage that the specific node of the buffer of describing among Fig. 4 is shown;
Fig. 7 is the schematic circuit according to the structure of the buffer of another embodiment;
Fig. 8 is the sequential chart that the control signal that is provided to the buffer of describing among Fig. 7 is shown;
Fig. 9 A to Fig. 9 C is the sequential chart that the control signal that is provided to the buffer of describing among Fig. 7 is shown.
To provide following example be for purposes of illustration rather than be intended to limit the scope of the invention.
Embodiment
Hereinafter, certain embodiments is described with reference to the accompanying drawings.When an element was connected to another element, this element not only can be directly connected to another element, can also be connected to another element indirectly by three element.In addition, for clarity, some elements have been omitted.In addition, identical label refers to components identical all the time.
Fig. 1 shows according to organic light emitting display of the present invention.With reference to Fig. 1, comprise according to the organic light emitting display of an embodiment: pixel portion 130 has the pixel 140 that forms arrays with multi-strip scanning line S1～Sn and many data wire D1～Dm; Scanner driver 110 is configured to driven sweep line S1～Sn; Data driver 120 is configured to drive many data wire D1～Dm; Time schedule controller 150 is configured to gated sweep driver 110 and data driver 120.
Pixel portion 130 receives the first power supply ELVDD and second source ELVSS.The first power supply ELVDD and second source ELVSS are provided to each pixel 140.The pixel 140 that receives the first power supply ELVDD and second source ELVSS is come display image corresponding to the data-signal that data drive circuit 129 provides.
Fig. 2 illustrates the block diagram according to the exemplary embodiment of the data drive circuit of describing among Fig. 1.Data drive circuit in this example comprises j (j is a positive integer) the individual passage and the j bar data wire that can connect.With reference to Fig. 2, data drive circuit 129 comprises: shift register 121 is used for sequentially producing sampled signal; Sampling latch part 122 is used for sequentially storing data in response to sampled signal; Keep latch part 123, be used to store data, and the data of storage are offered D-A converter 125 (being called " DAC " hereinafter) from sampling latch part 122; DAC 125, are used for producing aanalogvoltage corresponding to described data; Buffer unit 126 is used for aanalogvoltage is provided to data wire D.
When from time schedule controller 150 reception sources output enable signal SOE, keep latch part 123 to receive data from sampling latch part 122.After having received data, when receiving next source output enable signal SOE from time schedule controller 150, keep latch part 123 that the data of storage are provided to DAC 125.Keep latch part 123 to comprise j maintenance latch that respectively has k position size.
The voltage level of the data before level translator 124 is low, thus the power in the numerical portion of reduction circuit.In certain embodiments, DAC 125 preferably drives with higher digital voltage level.As shown in Figure 3, data drive circuit 129 also can comprise level translator 124, and level translator 124 is keeping between latch part 123 and the DAC 125, to increase from keeping latch part 123 to be provided to the voltage level of the data of DAC 125.
Fig. 4 shows the detailed schematic circuit according to the buffer of exemplary embodiment.Buffer 127 comprises: first inverter (inverter) 127a; The second inverter 127b; The first transistor M1 is connected between data wire Dj and the 3rd power supply VVdd; The transistor seconds M2 and the first capacitor C1 are connected between the DAC 125 and the first inverter 127a; The second capacitor C2 is connected between the first inverter 127a and the second inverter 127b; The 3rd capacitor C3 is connected between the second inverter 127b and the first transistor M1.
The first transistor M1 controls the electric current that flows into the 7th node N7 from the 3rd power supply VVdd in response to the voltage that is provided to the 6th node N6.The aanalogvoltage at node N7 place is reacted according to electric current, and is used as data-signal and offers pixel 140.When the first control signal CS1 is provided, transistor seconds M2 will offer first node N1 from the aanalogvoltage of DAC 125.When the 3rd control signal CS3 is provided, the 3rd transistor M3 conducting, thus the 7th node N7 and first node N1 are electrically connected.So just closed the feedback loop of control N7.When the first control signal CS1 was provided, the 4th transistor M4 offered the 6th node N6 with the voltage of the 3rd power supply VVdd, thereby transistor M1 ends.When the second control signal CS2 was provided, the 5th transistor M5 offered the 7th node N7 (therefore being provided to data wire Dj) with the voltage of the 4th power supply VVss.The first inverter 127a comprises the 8th transistor M8 and the 9th transistor M9 that is connected between the 3rd power supply VVdd and the 4th power supply VVss.Thus, regulate the 8th transistor M8, regulate the 9th transistor M9 by N-MOS by P-MOS.
The end of the gate terminal of the 8th transistor M8 and the 9th transistor M9 and the first capacitor C1 all is connected to Section Point N2, and wherein, Section Point N2 is in response to the voltage that drives and is driven on first node N1.When the first control signal CS1 was provided, the 6th transistor M6 was electrically connected Section Point N2 and the 3rd node N3.The second inverter 127b comprises the tenth transistor M10 and the 11 transistor M11 that is connected between the 3rd power supply VVdd and the 4th power supply VVss.Thus, regulate the tenth transistor M10, regulate the 11 transistor M11 by N-MOS by P-MOS.
The gate terminal of the tenth transistor M10 and the 11 transistor M11 and the end of the second capacitor C2 are connected to the 4th node N4, and are driven in response to the voltage that drives on the 3rd node N3.When the first control signal CS1 was provided, the 7th transistor M7 was electrically connected the 4th node N4 and the 5th node N5.
Fig. 5 is the sequential chart that is illustrated in DAC signal Vga, control signal CS1, CS2 and the CS3 of the buffer that is used for Fig. 4 during driving time section T1, T2, T3, the T4.As shown, in driving time section T1, the first control signal CS1 and the second control signal CS2 are provided.Therefore, in driving time section T1, transistor seconds M2, the 6th transistor M6, the 7th transistor M7, the 4th transistor M4 and the 5th all conductings of transistor M5.Along with transistor M6 conducting, the first inverter 127a will provide voltage to Section Point N2 and the 3rd node N3.The voltage that provides will be the level between the voltage level of the voltage level of the 4th power supply VVss and the 3rd power supply VVdd.Equally, along with transistor M7 conducting, the second inverter 127b will similarly provide voltage to the 4th node N4 and the 5th node N5, and wherein, the voltage that provides will have voltage level on the 4th power supply VVss and the level between the voltage level on the 3rd power supply VVdd.Along with transistor seconds M2 conducting, aanalogvoltage Vga is provided to first node N1 from DAC 125.Therefore, with the voltage at aanalogvoltage Vga and Section Point N2 place between poor corresponding store voltages at the first capacitor C1 two ends.
In addition, be identical all the time because be provided to the voltage of Section Point N2, depend on aanalogvoltage Vga so be stored in the voltage at the first capacitor C1 two ends.Along with the 4th transistor M4 conducting, the voltage of the 3rd power supply VVdd is provided to the 6th node N6, thereby the first transistor M1 ends.In addition, voltage on the 5th node N5 and the difference between the voltage on the 6th node N6 are stored in the 3rd capacitor C3 two ends.
Then, in the second driving time section T2, the first control signal CS1 stops.Therefore, in the second driving time section T2, transistor seconds M2, the 6th transistor M6, the 7th transistor M7 and the 4th transistor M4 end.What note is that at the end of the second driving time section T2, the voltage at first node N1 to the five node N5 places makes that the voltage at the 6th node N6 place is identical with the 3rd source voltage VVdd.Therefore, at the end of the second driving time section T2, the first transistor M1 ends.
In the 3rd driving time section T3, the 3rd control signal CS3 is provided.Therefore, the 3rd transistor M3 conducting in the 3rd driving time section, thus the 7th node N7 is electrically connected to first node N1.Because the 7th node N7 is driven to the 4th power supply VVss by the 5th transistor M5, so in the 3rd driving time section T3, first node N1 will drive from the value Vga of the second driving time section and be VVss.When the voltage of first node N1 is reduced to VVss, because the first capacitor C1 causes the magnitude of voltage at Section Point N2 place similarly to reduce.Because the amount in the pressure drop at first node N1 place depends on aanalogvoltage Vga, so the pressure drop at Section Point N2 place also will similarly be depended on aanalogvoltage Vga.
Because Section Point N2 is the input of the first inverter 127a, so when the voltage at Section Point N2 place reduces, the output of first inverter at the 3rd node N3 place will increase.Owing to the second capacitor C2 makes the voltage at the 4th node N4 place to increase according to the increase of the 3rd node N3 place voltage.Because the 4th node N4 is the input of the second inverter 127b, so when the voltage at the 4th node N4 place increases, will reduce in the output of the second inverter 127b at the 5th node N5 place.Because the 6th node N6 will be capacitively coupled to the 5th node N5, so when the voltage at the 5th node N5 place reduced, the voltage at the 6th node N6 place reduced similarly.
Because the voltage at the 6th node N6 place is the grid voltage of the first transistor M1, so when the 6th voltages at nodes reduced, the first transistor conducting also began conduct current the 7th node N7.Yet, because the 5th still conducting of transistor M5, so the voltage at the 7th node N7 place does not change basically.What note is, at the end of the 3rd driving time section T3, the voltage at first node N1 to the five node N5 places makes the voltage at the 6th node N6 place less than the 3rd supply voltage VVdd.Therefore, at the end of the 3rd driving time section T3, the first transistor M1 conducting.
Then, in the moving time period T4 of 4 wheel driven,, ends control signal CS2 thereby stopping the 5th transistor M5.The voltage at the 7th node N7 place rises according to the electric current that the first transistor M1 provides.Because the 7th voltages at nodes is fed back to the first inverter 127a and the second inverter 127b by the 3rd transistor M3 and the first capacitor C1, thus the voltage at the 6th node N6 place of the input of the first transistor M1 be subjected to the 7th node N7 on the influence of up voltage.The affected form of the 6th voltages at nodes is that the voltage that the 7th node N7 place increases causes the voltage at the 6th node N6 place to rise.The voltage at the 7th node N7 and the 6th node N6 place will continue to rise, and M1 ends up to the first transistor.The voltage that this situation will occur in the 7th node N7 place has risen to the voltage that is enough to make first node N1 to the six node N6 places and has got back to these voltages when the value that the end of the second driving time section T2 has.Recall the end at the second driving time section T2, the voltage at the 6th node N6 place equals the value of power supply VVdd, and therefore the first transistor M1 ends.When the voltage at the 7th node N7 place rises and when therefore the voltage at first node N1 place had risen to the voltage that equals at the first node N1 place of the end of the second driving time section T2, this thing happens once more for the general.Recall the end in the second driving time section, the magnitude of voltage at first node N1 place is aanalogvoltage Vga.Therefore, in the moving time period, buffer will not have transistor threshold voltage to fall with aanalogvoltage Vga driving data lines Dj at 4 wheel driven, thereby relevant pixel 140 will be according to voltage is next luminous accurately.
Fig. 6 is illustrated in the transformation of second, third and 4 wheel driven Section Point N2, the 4th node N4 and the 6th node N6 in the moving time period.As mentioned above, at the end of the second driving time section, the voltage of Section Point N2 has the value that depends on the first inverter 127a, and wherein, the input and output of the first inverter 127a are by the 6th transistor M6 short circuit.Equally, the voltage at the 4th node N4 place has the value that depends on the second inverter 127b, and wherein, the input and output of the second inverter 127b are by the 7th transistor M7 short circuit.Because the 6th node N6 is shorted to power supply VVdd by the 4th transistor M4 in the first driving time section T1, the voltage at the 6th node N6 place has the value that equals power supply VVdd.
In the 3rd driving time section T3, the voltage at Section Point N2, the 4th node N4 and the 6th node N6 place changes according to first group shown in Fig. 6.The voltage at Section Point N2 place has reduced the amount of V1, and V1 is based on aanalogvoltage Vga.The voltage at the 4th node N4 place is based on the increase of the voltage at the 3rd node N3 place and increase, and the increase of the voltage at the 3rd node N3 place is based on the reduction of the voltage at Section Point N2 place and the gain of the first inverter 127a.What note is, the amount that the amount of the voltage increase at the 4th node N4 place reduces greater than the voltage at Section Point N2 place.This is that gain owing to the first inverter 127a causes.The voltage at the 6th node N6 place being based on the reducing of voltage at the 5th node N5 place and reduce, the reducing based on the increase of the voltage at the 4th node N4 place and the gain of the second inverter 127b of the voltage at the 5th node N5 place.What note is that the amount that the voltage at the 6th node N6 place reduces is greater than the amount of the voltage increase at the 4th node N4 place.This is because the gain of the second inverter 127b causes.
In the moving time period T4 of 4 wheel driven, as mentioned above, the Voltage Feedback at the 7th node N7 place is to first node N1.The voltage that rises in the 7th node N7 place causes the voltage at first node N1 place to rise.Because the coupling capacitor between first node and Section Point is so the last up voltage at first node N1 place causes the voltage at Section Point N2 place also to rise.Because the first inverter 127a is so the last up voltage at Section Point N2 place causes the voltage at the 3rd node N3 place to reduce.Because the coupling capacitor between the 3rd node and the 4th node, thus the voltage at the 3rd node N3 place reduce cause the voltage at the 4th node N4 place also to reduce.Because the second inverter 127b, so the voltage increase that reduces to cause the 5th node N5 place of the voltage at the 4th node N4 place.Because the coupling capacitor between the 5th node and the 6th node, so the voltage of the increase at the 5th node N5 place causes the voltage at the 6th node N6 place to increase.As mentioned above, in case the voltage at the 6th node N6 place increases to VVdd, the first transistor just will stop to the 7th node N7 drive current, and therefore the voltage at the 7th node N7 place will stop to rise.As shown in Figure 6, this situation occurs in Section Point, the 4th node and the 6th voltages at nodes and all turns back to these nodes when the magnitude of voltage that the end of the second driving time section has.
Therefore, no matter transistorized threshold voltage how, can be provided to data wire Dj by buffer 127 from the Vga of aanalogvoltage accurately of DAC 125.A favourable aspect of this buffer is that because the accuracy of output, this buffer can be applicable to undoubtedly to have in the high-resolution big display.Therefore, because the gain of two inverters, so the voltage that the grid place of the first transistor presents is the amplification form of aanalogvoltage Vga.This has caused the operation of buffer faster.In certain embodiments, can realize gain with other circuit structure.On the other hand, in certain embodiments, it is optional to gain, and the circuit between first node N1 and the 5th node N5 can be substituted by other single substantially gain circuitry of lead or some.
Fig. 7 shows the detailed schematic circuit according to the structure of the buffer of another exemplary embodiment.The difference of embodiment shown in this embodiment and Fig. 4 is to have added the tenth two-transistor M12 and the 13 transistor M13, the tenth two-transistor M12 is connected between the first inverter 127a and the 3rd power supply VVdd, and the 13 transistor M13 is connected between the second inverter 127b and the 4th power supply VVss.The tenth two-transistor M12 has different conductivity with the 13 transistor M13.That is, the tenth two-transistor M12 is a PMOS transistor and the 13 transistor M13 is a nmos pass transistor.First inverter and second inverter operated with the input and output between VVss and the VVdd can consume too much power.The tenth two-transistor and the 13 transistor only can be worked first inverter and second inverter when buffer uses first inverter and second inverter to change the buffering output level, as described below.
When the 4th control signal CS4 is provided, the tenth two-transistor M12 conducting.The result makes the voltage of tertiary voltage VVdd be provided to the first inverter 127a, thereby the first inverter 127a starts.
When the 5th control signal CS5 is provided, the 13 transistor M13 conducting.The result makes the voltage of the 4th voltage VVss be provided to the second inverter 127b, thereby the second inverter 127b starts.
With reference to Fig. 7 and Fig. 8, the operation of buffer will be explained.As shown in Figure 8, before the first driving time section T1, the first control signal CS1, the second control signal CS2, the 3rd control signal CS3, the 4th control signal CS4 and the 5th control signal CS5 are invalid.What note is, because the first control signal CS1, the 3rd control signal CS3 and the 4th control signal CS4 are used to drive the PMOS transistor, so they are effective when low, because the second control signal CS2 and the 5th control signal CS5 are used for the driving N MOS transistor, so they are effective when being high.From the moving time period T4 of first driving time section T1 to the 4 wheel driven, the 4th control signal CS4 and the 5th control signal CS5 are effective.Therefore, from the incipient stage of the moving time period T4 of first driving time section T1 to the 4 wheel driven, the first inverter 127a and the second inverter 127b work.In these time periods, the first control signal CS1 to the, three control signal CS3 drive in the mode identical with the corresponding signal of reference Fig. 4 discussion.Equally, the operation of buffer is identical with the operation of the buffer of discussing with reference to Fig. 4.Yet, attention be, in the 4th time period T4, in case the voltage at the 6th node N6 place is in VVdd, the first transistor M1 ends, thus first inverter and second inverter do not need work.If their idle words just can be saved the power that they consume.Therefore, after after a while, the 4th control signal CS4 becomes disarmed state at the 4th time period T4, thereby the first inverter 127a does not work.Equally, the 5th control signal CS5 becomes disarmed state, and the second inverter 127b does not work.What note is, it is VVdd at least that this circuit is configured to keep the voltage at the 6th node N6 place when first inverter and second inverter are not worked.
Also can use other control signal drive scheme, such as the drive scheme of describing among Fig. 9 A to Fig. 9 C.Fig. 9 A shows at the 4th control signal CS4 and the 5th control signal CS5 and makes first inverter and the sequential chart of second inverter under the situation that the whole first driving time Duan Zhidi 4 wheel driven was all worked in the moving time period.Equally, Fig. 9 B is illustrated in the 4th control signal CS4 and the 5th control signal CS5 and makes first inverter and second inverter at the first driving time Duan Zhidi 4 wheel driven in the most of the time of moving time period rather than the sequential chart under the situation of working in the All Time.
Fig. 9 C shows the drive scheme of another type.In this scheme, the 4th control signal CS4 and the 5th control signal CS5 work first inverter and second inverter constantly.Yet, select the voltage at the 4th control signal CS4 and the 5th control signal CS5 place, so that limited amount electric current flows into inverter, rather than make the voltage at the 4th control signal CS4 and the 5th control signal CS5 place be substantially equal in the 3rd power source voltage or the 4th power source voltage one.By this way, inverter is operated operation all the time, but with limited current practice to save power.
As mentioned above, no matter transistorized threshold voltage is how, buffer and have utilization and can provide aanalogvoltage accurately according to the organic light emitting display of the data drive circuit of the buffer of exemplary embodiment of the present invention.Because how this buffer can both provide grayscale voltage (gradation voltage) accurately regardless of transistorized threshold voltage,, this buffer has large tracts of land and high-resolution panel so can advantageously driving.In addition, because provide enable voltage to make inverter only when being used to change the buffer output voltage, just work selectively, so can reduce power consumption.
Though above description has been pointed out as being applied to the novel characteristics of the present invention of various embodiment, but the technical staff should be appreciated that, without departing from the scope of the invention, can be to making various combinations, omission, replacement and change on the form of described device or process and the details.Therefore, scope of the present invention is defined by the claims rather than is limited by the description of front.Falling into the implication of claim equivalent and the various variations in the scope comprises within the scope of the claims.
Claims (26)
1, a kind of buffer comprises:
First capacitor comprises the first capacitor end and the second capacitor end, and described first capacitor is formed at the described first capacitor termination and receives aanalogvoltage, and wherein, described aanalogvoltage is the input to described buffer;
First inverter has the first input end and first output, and described first input end is connected to the described second capacitor end of described first capacitor;
Second capacitor has the 3rd capacitor end and the 4th capacitor end, and described the 3rd capacitor end is connected to described first output of described first inverter;
Second inverter has second input and second output, and described second input is connected to described the 4th capacitor end of described second capacitor;
The 3rd capacitor has the 5th capacitor end and the 6th capacitor end, and described the 5th capacitor end is connected to described second output of described second inverter;
The first transistor, be connected to described the 6th capacitor end of described the 3rd capacitor, described the first transistor is configured to Control current flowing from first power supply to data wire, make buffer voltagc be provided to described data wire, wherein, the described the first transistor voltage that is configured to respond described the 3rd capacitor and provides is controlled described electric current;
Transistor seconds is connected to the first capacitor end of described data wire and described first capacitor.
2, buffer as claimed in claim 1, wherein, the value of described buffer voltagc equals the value of described aanalogvoltage input.
3, buffer as claimed in claim 2 wherein, ends when the value that described the first transistor is formed at described buffer voltagc equals the value of described aanalogvoltage input.
4, buffer as claimed in claim 1, wherein, the absolute value of voltage that is provided to described the first transistor from described the 3rd capacitor is greater than the absolute value of described aanalogvoltage input.
5, buffer as claimed in claim 1 also comprises:
The 3rd transistor, be connected to the described first capacitor end of described first capacitor, when described the 3rd transistor is formed at first control signal and is provided to described the 3rd transistor described aanalogvoltage be provided to the described first capacitor end of described first capacitor;
The 4th transistor, be connected to described the 6th capacitor end of described first power supply and described the 3rd capacitor, described the 4th transistor is formed at the voltage that will equal described first supply voltage when described first control signal is provided to described the 4th transistor and is provided to described the 3rd capacitor;
The 5th transistor is connected to described data wire and is connected to second source, and the voltage with described second source when described the 5th transistor is formed at second control signal and is provided to described the 5th transistor is provided to described data wire.
6, buffer as claimed in claim 5, wherein, described first power source voltage is greater than the voltage of described second source.
7, buffer as claimed in claim 5 also comprises:
The 6th transistor is connected to described first output of described first inverter and the described first input end of described first inverter, conducting when described the 6th transistor is formed at described first control signal and is provided to described the 6th transistor;
The 7th transistor is connected to described second output of described second inverter and described second input of described second inverter, conducting when described the 7th transistor is formed at described first control signal and is provided to described the 7th transistor.
8, buffer as claimed in claim 7, wherein, conducting when described transistor seconds is formed at the 3rd control signal and is provided.
9, buffer as claimed in claim 8, wherein, described buffer is configured to receive simultaneously the initial of described first control signal and described second control signal, and receives the end of described first control signal before receiving the end of described second control signal.
10, buffer as claimed in claim 9, wherein, terminal back and the terminal preceding of described second control signal that described buffer is formed at described first control signal receive the initial of described the 3rd control signal, and receive the end of described the 3rd control signal in the terminal back of described second control signal.
11, buffer as claimed in claim 10 also comprises:
The 8th transistor is connected between described first inverter and described first power supply;
The 9th transistor is connected between described second inverter and the described second source.
12, buffer as claimed in claim 11, wherein, described the 8th transistor has different conductivity with described the 9th transistor.
13, buffer as claimed in claim 12, wherein, conducting when described the 8th transistor is formed at the 4th control signal and is provided to described the 8th transistor, wherein, conducting when described the 9th transistor is formed at the 5th control signal and is provided to described the 9th transistor.
14, buffer as claimed in claim 13, wherein, described buffer is configured to, before described second control signal or with described second control signal, synchronously receive the initial of described the 4th control signal and described the 5th control signal, and after described the 3rd control signal initial, receive the end of the 4th control signal and the 5th control signal.
15, buffer as claimed in claim 13, wherein, described buffer is configured to receive at least one the 4th control signal and the 5th control signal that includes in the following voltage: equal described first supply voltage voltage, equal described second source voltage voltage, be configured to provide the voltage of limited non-vanishing electric current to described first inverter or described second inverter.
16, buffer as claimed in claim 13, be configured to receive constantly described the 4th control signal and described the 5th control signal, and respond described the 4th control signal and described the 5th control signal and come the first limited non-vanishing electric current to be provided and to provide the second limited non-vanishing electric current to described second inverter to described first inverter.
17, a kind of data drive circuit comprises:
D-A converter, the place value that is configured to the response data input produces aanalogvoltage;
A plurality of buffers, each buffer all are configured to provide described aanalogvoltage to data wire, and each buffer comprises:
First capacitor comprises the first capacitor end and the second capacitor end, and described first capacitor is formed at the described first capacitor termination and receives aanalogvoltage, and wherein, described aanalogvoltage is the input to described buffer;
First inverter has the first input end and first output, and described first input end is connected to the described second capacitor end of described first capacitor;
Second capacitor has the 3rd capacitor end and the 4th capacitor end, and described the 3rd capacitor end is connected to described first output of described first inverter;
Second inverter has second input and second output, and described second input is connected to described the 4th capacitor end of described second capacitor;
The 3rd capacitor has the 5th capacitor end and the 6th capacitor end, and described the 5th capacitor end is connected to described second output of described second inverter;
The first transistor, be connected to described the 6th capacitor end of described the 3rd capacitor, described the first transistor is configured to Control current flowing from first power supply to data wire, make buffer voltagc be provided to described data wire, wherein, the described the first transistor voltage that is configured to respond described the 3rd capacitor and provides is controlled described electric current;
Transistor seconds is connected to the first capacitor end of described data wire and described first capacitor.
18, data drive circuit as claimed in claim 17, wherein, the value of described buffer voltagc equals the value of described aanalogvoltage input.
19, data drive circuit as claimed in claim 18 wherein, ends when the value that described the first transistor is formed at described buffer voltagc equals the value of described aanalogvoltage input.
20, data drive circuit as claimed in claim 17 also comprises:
The 3rd transistor, be connected to the described first capacitor end of described first capacitor, when described the 3rd transistor is formed at first control signal and is provided to described the 3rd transistor described aanalogvoltage be provided to the described first capacitor end of described first capacitor;
The 4th transistor, be connected to described the 6th capacitor end of described first power supply and described the 3rd capacitor, described the 4th transistor is formed at the voltage that equals described first supply voltage is provided when described first control signal is provided to described the 4th transistor;
The 5th transistor is connected to described data wire and is connected to second source, and the voltage with described second source when described the 5th transistor is formed at second control signal and is provided to described the 5th transistor is provided to described data wire.
21, data drive circuit as claimed in claim 20, wherein, described first power source voltage is greater than the voltage of described second source.
22, the data drive circuit described in claim 20 also comprises:
The 6th transistor is connected to described first output of described first inverter and the described first input end of described first inverter, conducting when described the 6th transistor is formed at described first control signal and is provided to described the 6th transistor;
The 7th transistor is connected to described second output of described second inverter and described second input of described second inverter, conducting when described the 7th transistor is formed at described first control signal and is provided to described the 7th transistor.
23, data drive circuit as claimed in claim 22 also comprises:
The 8th transistor is connected between described first inverter and described first power supply;
The 9th transistor is connected between described second inverter and the described second source.
24, data drive circuit as claimed in claim 23, wherein, described the 8th transistor has different conductivity with described the 9th transistor.
25, data drive circuit as claimed in claim 23, wherein, conducting when described the 8th transistor is formed at the 4th control signal and is provided to described the 8th transistor, wherein, conducting when described the 9th transistor is formed at the 5th control signal and is provided to described the 9th transistor.
26, data drive circuit as claimed in claim 17 also comprises:
Shift register is configured to sequentially produce sampled signal;
The latch part is configured to store described data and the data of storing are provided to D-A converter corresponding to sampled signal.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020050027305 | 2005-03-31 | ||
| KR1020050027306 | 2005-03-31 | ||
| KR1020050027305A KR100629576B1 (en) | 2005-03-31 | 2005-03-31 | Buffer and light emitting display with integrated circuit using the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1841932A CN1841932A (en) | 2006-10-04 |
| CN100525107C true CN100525107C (en) | 2009-08-05 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100583814A Expired - Fee Related CN100525107C (en) | 2005-03-31 | 2006-03-03 | Buffer and a data driving circuit using the same |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR100629576B1 (en) |
| CN (1) | CN100525107C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100916906B1 (en) | 2008-04-25 | 2009-09-09 | 삼성모바일디스플레이주식회사 | Buffer and organic light emitting display using the same |
| JP2011217287A (en) * | 2010-04-01 | 2011-10-27 | Sony Corp | Inverter circuit and display device |
| JP6731238B2 (en) * | 2015-11-27 | 2020-07-29 | ラピスセミコンダクタ株式会社 | Display driver |
-
2005
- 2005-03-31 KR KR1020050027305A patent/KR100629576B1/en not_active IP Right Cessation
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2006
- 2006-03-03 CN CNB2006100583814A patent/CN100525107C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1841932A (en) | 2006-10-04 |
| KR100629576B1 (en) | 2006-09-27 |
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