CN100539155C - Floating gate non-volatile memory - Google Patents
Floating gate non-volatile memory Download PDFInfo
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- CN100539155C CN100539155C CNB2005100697806A CN200510069780A CN100539155C CN 100539155 C CN100539155 C CN 100539155C CN B2005100697806 A CNB2005100697806 A CN B2005100697806A CN 200510069780 A CN200510069780 A CN 200510069780A CN 100539155 C CN100539155 C CN 100539155C
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Abstract
Wherein on single-crystal control region, provide in the nonvolatile memory of floating boom, the electromotive force of writing that is arranged on the floating boom has capacitive couplings with respect to floating boom, perhaps even among the dielectric film on the floating boom and on a part comprise or be attached with electric charge, therefore changed the gate threshold voltage of the floating gate non-volatile memory of measuring from single-crystal control region.In order to address the above problem, the invention provides following method.Provide on floating boom via shadowing insulation film and to cover conducting film.For shadowing insulation film, do not use the dielectric film that forms by following deposition process, the gas atmosphere contact wafer surface of containing the non-equilibrium electric charge particle of for example too much electronics or too much ion in this method, plasma CVD for example, and use wherein directly unsettled deposition process, for example hot CVD, free radical CVD, light assisted CVD or the thermal oxidation on wafer of neutral molecule/atom.
Description
Technical field
The present invention relates to a kind of semiconductor non-volatile memory, relate in particular to a kind of semiconductor non-volatile memory that floating boom wherein is provided on control gate with floating boom.
Background technology
The nonvolatile memory of control gate wherein is provided on the dielectric film that is grown on the floating boom, exists in the problem that the dielectric film of growing on the multi-crystal silicon floating bar has big leakage current and less proof voltage.As the floating gate non-volatile memory that addresses this problem, a kind of structure is disclosed, wherein: form on the semiconductor regions floating boom is provided being clipped in raceway groove in the middle of source region and the drain region via dielectric film; This floating boom extends on the dielectric film that is grown on the single-crystal control region; And this single-crystal control region is as control gate.(with reference to JP57-49148B, Fig. 3).
On the other hand, developed a kind of technology separately, wherein on multi-crystal silicon floating bar, formed dielectric film with less leakage current and good proof voltage; Yet this technology and MOS logic almost do not have common manufacturing step.Therefore, JP57-49148B openly after soon, utilize this floating gate non-volatile memory as the nonvolatile memory that is suitable for being embedded in the MOS logic with single-crystal control region.In this case, in the surface of Semiconductor substrate, form single-crystal control region, as with the semiconductor regions of substrate films of opposite conductivity.
At present, the supply voltage of IC/LSI decreases, and it makes the interior electromotive force control of small voltage scope of floating boom become important.Therefore, following problem has appearred.
That is, (1) electromotive force (under the state that does not contact and separate with floating boom) of being arranged at the interconnection on the floating boom has capacitive couplings with floating boom.As a result, the gate threshold voltage of the floating gate non-volatile memory of measuring from single-crystal control region exists and changes.
(2) even when in the dielectric film on the floating boom and the part on this dielectric film comprises or when being attached with electric charge, also there is variation in the gate threshold voltage of the floating gate non-volatile memory of measuring from single-crystal control region.
When on wafer with direct excitaton source gas discharge such as plasma CVD, during with deposit dielectric film on floating boom, produced the electric charge that is included in this dielectric film.Since wafer or the surface contamination of chip or the discharge of chucking operation, and on dielectric film, produced electric charge.
When the design floating gate non-volatile memory, do not consider the influence of interconnection configuration under a lot of situations.And amount of charge involved or that adhere to can not be predicted.Therefore, be difficult to the gate threshold voltage of precognition from whole floating gate non-volatile memories of single-crystal control region measurement.
Summary of the invention
In view of above situation has been constructed the present invention, and therefore has the purpose that floating gate non-volatile memory is provided.In order to address the above problem, the invention provides on floating boom and cover conducting film as first method via what shadowing insulation film provided, and as second method, for shadowing insulation film, not to form dielectric film by such deposition process, the gas atmosphere that promptly contains the non-equilibrium electric charge particle of for example too much electronics or too much ion in this deposition process contacts with wafer surface, plasma CVD for example, but form dielectric film by the deposition process that neutral molecule/atom wherein directly flies on the wafer, hot CVD for example, free radical CVD (radical CVD), light assisted CVD (photo-assisted CVD).
Notice, we can say, further electronics is being energized under the situation that the result of external electrical shell track examines under a microscope from ground state, this molecule/atom is in thermal decomposition/thermal response or by positively charged/negative electricity immediately before activating under the atomic group state such as optical excitation.Yet, in the present invention, wherein be called term " neutral molecule/atom " with the positive charge and the negative electrical charge state in a basic balance of perusal on wafer surface.
Dependence method 1 has been avoided near the influence of electric potential of the interconnection that gate threshold voltage provides being subjected to, or avoided being subjected to make the back floating boom on the charge affects that contacts of part.
Dependence method 2, the electric charge that is included in the dielectric film on the floating boom by this manufacturing step can be reduced to the level that can not cause the problem of gate threshold voltage substantially.When this influence can be reduced to can not cause the degree of problem substantially on reality is seen the time, this covers conducting film does not need to cover fully floating boom.
And therefore this shadowing insulation film not major decision control gate, can be deposited to the thickness level of the restriction of satisfying withstand voltage and leakage current to the coupling efficiency of floating boom.Therefore, can solve the problem that needs single-crystal control region.
If desired, can provide the preliminary election electromotive force by guide electric screen film, to adjust the gate threshold voltage of measuring from single-crystal control region.
By providing the preliminary election electromotive force, if desired, when writing, can reduce the absolute value of the electromotive force that offers single-crystal control region to covering conducting film.As a result, can reduce the proof voltage that single-crystal control region needs.
Provide the preliminary election electromotive force by guide electric screen film, if desired, when wiping, can reduce the absolute value of the electromotive force that is provided to drain region or source region.As a result, can reduce the proof voltage that drain region or source region need.
Description of drawings
In the accompanying drawings:
Fig. 1 is the vertical view according to the semiconductor device of embodiment 1; With
Fig. 2 is the vertical view according to the semiconductor device of the embodiment 2 that has wherein used the SOI substrate.
Embodiment
Floating gate non-volatile memory of the present invention can be implemented by following structure.That is, floating gate non-volatile memory is made of following: substrate; The raceway groove of first conduction type forms semiconductor regions, and it is provided in the substrate surface area of substrate; Source region and drain region, it forms semiconductor regions by raceway groove and sandwiches and separate each other between them and be provided in the substrate surface area; Be provided at the gate insulating film on the raceway groove formation semiconductor regions; Single-crystal control region, itself and channel formation region territory electricity are isolated and are provided in the substrate surface area; Be provided at the control gate dielectric film on the single-crystal control region; Floating boom, it is provided on the gate insulating film and it extends on the control gate dielectric film to have the capacitive couplings on the electricity with single-crystal control region; Be provided at the shadowing insulation film on the floating boom; With cover conducting film, it is provided on the shadowing insulation film and has capacitive couplings with floating boom.
This shadowing insulation film need be by neutral molecule/atom unsettled (come flying) wherein deposition process directly form comprising on the wafer of floating boom.Especially, use the dielectric film that forms by hot CVD, free radical CVD, catalysis CVD.
At this substrate is under the situation of Semiconductor substrate, and this single-crystal control region can form semiconductor regions with raceway groove and form at interval, as with the zone of substrate surface area films of opposite conductivity.
Constitute by support substrates with the semiconductor layer of support substrates insulation at substrate, and semiconductor layer forms under the situation of substrate surface area, this single-crystal control region separates with forming the raceway groove formation semiconductor regions that has dielectric film therebetween, and single-crystal control region can be p-type or n-type.
If desired, provide the preliminary election electromotive force, therefore when reading, can adjust the gate threshold voltage of measuring from single-crystal control region to covering conducting film.
Can when writing, provide the preliminary election electromotive force that has same-sign with the electrical source voltage of single-crystal control region to covering conducting film.Therefore, when writing, be applied to the shadowing insulation film electric field and reduce, reliability is improved.In addition, can reduce the requirement of the required proof voltage of single-crystal control region.
When wiping, provide and have the symbol identical, have the symbol opposite and have in the preliminary election electromotive force of the symbol opposite one with the electrical source voltage in drain region with the electrical source voltage in source region with the electrical source voltage of single-crystal control region to covering conducting film.Therefore, when wiping, can reduce the absolute value that offers at least one the regional electromotive force in these three zones.Therefore, can reduce this three proof voltages that the zone is required.
Embodiment 1
Fig. 1 is the vertical view/profile according to the embodiment of the invention 1.In the drawings, Reference numeral 100 expression Semiconductor substrate, the substrate surface area of Reference numeral 110 expressions first conduction type, it is known as well structure.The source region of Reference numeral 200 expression films of opposite conductivity; The drain region of 300 expression films of opposite conductivity; And 410 be illustrated in raceway groove and form the gate insulating film that forms on the semiconductor regions.This raceway groove forms semiconductor regions 111 (not shown)s, is formed in the surface of substrate surface area, and this raceway groove forms semiconductor regions between source region 200 and drain region 300 and be positioned under the gate insulating film 410.The single-crystal control region of Reference numeral 500 expression films of opposite conductivity, it is formed in the substrate surface area of first conduction type; 450 expressions are formed at the control gate dielectric film on the single-crystal control region; 600 expression floating booms; 460 the shadowing insulation film that provides on the floating boom is provided; 700 the conducting film that covers that provides on the shadowing insulation film is provided; 470 expressions are provided at first interlayer dielectric that covers on the conducting film.Generally, on first interlayer dielectric, provide multiple level interconnect architecture.
Provide source region and drain region to make it be spaced from each other, the semiconductor regions of raceway groove formation simultaneously is sandwiched in therebetween.Providing single-crystal control region to make itself and source region, drain region and raceway groove form semiconductor regions separates.
On the semiconductor substrate surface between single-crystal control region and source region, drain region and the raceway groove formation semiconductor regions, provide so-called field insulating membrane.Extend on the control gate dielectric film 450 that also further extends on the field insulating membrane on the single-crystal control region at the floating boom 600 that provides on the gate insulating film 410.
Single-crystal control region has the rectification node with respect to Semiconductor substrate.If single-crystal control region is the n-type, each source region and drain region also are the n-types, and substrate surface area is the p-type.In this, single-crystal control region has the opereating specification with respect to the positive potential of substrate surface area.Below, the polarity of voltage is described in view of the situation.In source region and drain region is under the situation of p-type, can be by polarity of voltage is reverse, and on numerical relation, make comparisons with absolute value and carry out following description.
Can inject or inject the write operation that carries out floating gate non-volatile memory by channel hot electron from FN (Fowler-Nordheim) tunnel that raceway groove forms the electronics of semiconductor regions.
By 0V voltage being provided, 4 to 5V voltages being provided and providing 10 to 12V voltages to carry out channel hot electron to the drain region and inject to the source region respectively to single-crystal control region.In this case, the speed that writes is very fast, but the big electric current of 100 μ A levels flows to the drain region from the source region.
Can inject by 0V voltage being provided and providing 14 to 16V voltages to carry out the FN tunnel to source region or drain region respectively to single-crystal control region.In this case, do not have big electric current to flow, but the speed that writes is slower.
Be provided with the array shape under the situation of floating gate non-volatile memory, can applying high voltage (10 to 16V) to the single-crystal control region of memory cell, in some cases to writing of this memory cell be not the expection.To write in order retraining, 4 to 5V voltage to be provided to the source region of memory cell.
Provide electromotive force to carry out wiping of floating gate non-volatile memory by in source region and drain region one or two near 10V.
When writing,, can provide assisted bias (for example, the preliminary election electromotive force is set to 9 to 12V) to covering conducting film in order to reduce the electric field that is applied to shadowing insulation film.As a result, can reduce the voltage (for example, 7 to 12V) of single-crystal control region.The knot proof voltage of single-crystal control region has reduced.Therefore, obtaining bigger actual effect aspect the miniaturization of MOSIC/LSI.
When reading, can to cover conducting film provide measure from single-crystal control region, for gate threshold voltage being adjusted to for example 0 to 0.5V biasing (for example, this preliminary election voltage being set is 0 to 1.5V).
When wiping, provide assisted bias (for example, this preliminary election to be set be biased to-6V), therefore the potential drop that offers source region or drain region can be low to moderate near 8V to covering conducting film.Can be reduced in the knot proof voltage in drain region or source region.Therefore, aspect the MOSIC/LSI miniaturization, obtain bigger actual effect.
For be controlled in the control gate dielectric film defective with and growth rate, the surface impurity concentration of single-crystal control region is set to 10
19Atom/cc or littler magnitude.In this, can form control gate dielectric film and gate insulating film simultaneously by thermal oxidation.When carrying out thermal oxidation under the condition of gate insulating film that with acquisition 80nm thickness is typical thickness, the control gate dielectric film has the thickness near 90nm.
For shadowing insulation film, can use high temperature (about 600 to 700 ℃) hot CVD oxide-film by utilizing silane for example or organosilan and nitrogen oxide to form as source gas.The thickness of about 250nm can be realized proof voltage when writing.
Can be by using local interconnecting material, for example polysilicon and titanium nitride form and cover conducting film.Do not having can to use the first metal layer material under the operable situation of local interconnecting material yet.
Cover conducting film technology afterwards about providing, even by using plasma CVD to be formed for the interlayer dielectric or the plasma nitrided silicon fiml of passivation, in the application that embeds, this does not influence the threshold voltage of floating gate non-volatile memory.
Embodiment 2
Fig. 2 is the partial top view according to embodiments of the invention 2.In embodiment 2, the invention process is on SOI (semiconductor on the insulator) substrate 100, and this substrate is to constitute with the semiconductor layer 103 of this support substrates insulation by support substrates 101 with by the insulating barrier 102 that is called BOX.Semiconductor layer 103 constitutes substrate surface area.Represent to have the zone of identical function with Reference numeral identical among Fig. 1.
In this embodiment, single-crystal control region 500 insulate fully by field insulating membrane 440 and source region 200, drain region 300 and raceway groove formation semiconductor regions 111 (not shown)s.Therefore, single-crystal control region 500 can be the p-type or the n-type.In addition, can operate by the voltage of positive and negative polarity.Therefore, can write and wipe by the electromotive force that applies opposed polarity to single-crystal control region.That is, when under the positive potential that forms semiconductor regions with respect to raceway groove (for example, 14 to 16V) can wipe by having the negative potential identical when writing with the absolute value of positive potential by single-crystal control region.Identical among other viewpoints that relate to biasing and the embodiment 1.To identical among the power supply effect of the preliminary election electromotive force of shield conductive layer and the embodiment 1.
Claims (12)
1. floating gate non-volatile memory comprises:
Substrate;
The raceway groove of first conduction type forms semiconductor regions, is provided in the substrate surface area of substrate;
Source region and drain region, each source region and drain region are provided in the substrate surface area, and described source region and drain region sandwich therebetween and separate each other by raceway groove being formed semiconductor regions;
Be provided at the gate insulating film on the raceway groove formation semiconductor regions;
Single-crystal control region forms the semiconductor regions electricity with raceway groove and isolates and be provided in the substrate surface area;
The control gate dielectric film that on single-crystal control region, provides;
Floating boom, be provided on the gate insulating film and extend on the control gate dielectric film with the single-crystal control region capacitive couplings;
Be provided at the charge balance shadowing insulation film on the floating boom; With
Cover conducting film, be provided on the charge balance shadowing insulation film and with the floating boom capacitive couplings.
2. according to the floating gate non-volatile memory of claim 1, wherein:
Substrate comprises Semiconductor substrate; Single-crystal control region and raceway groove form semiconductor regions and separate, and have the conduction type opposite with substrate surface area.
3. according to the floating gate non-volatile memory of claim 1, wherein:
Substrate comprises support substrates and the semiconductor layer that insulate with support substrates, and described semiconductor layer formation substrate surface area, and raceway groove forms semiconductor regions and is formed in the part semiconductor layer; And wherein single-crystal control region separates by dielectric film and raceway groove formation semiconductor regions.
4. according to the floating gate non-volatile memory of claim 1,, provide the preliminary election electromotive force, to adjust the gate threshold voltage of measuring from single-crystal control region to covering conducting film wherein when floating gate non-volatile memory reads.
5. according to the floating gate non-volatile memory of claim 1,, cover conducting film and accept and offer the preliminary election electromotive force that the electrical source voltage of single-crystal control region has same-sign wherein when floating gate non-volatile memory writes.
6. according to the floating gate non-volatile memory of claim 1, wherein when the floating gate non-volatile semiconductor memory is wiped, cover conducting film accept with the electrical source voltage that offers single-crystal control region have same-sign the preliminary election electromotive force, have and offer the source region the electrical source voltage contrary sign the preliminary election electromotive force and have and offer in the preliminary election electromotive force of electrical source voltage contrary sign in drain region one.
7. according to the floating gate non-volatile memory of claim 1, wherein form the charge balance shadowing insulation film by in charge balance atmosphere, carrying out thermal chemical vapor deposition, free-radical chemistry vapour deposition or light assistant chemical vapor deposition.
8. according to the floating gate non-volatile memory of claim 1, wherein form the charge balance shadowing insulation film by a kind of method in thermal chemical vapor deposition method, free radical CVD (Chemical Vapor Deposition) method, the light assistant chemical vapor deposition method.
9. floating gate non-volatile memory comprises:
Substrate with surf zone;
Raceway groove forms semiconductor regions, is provided in the surf zone of substrate;
Source region and drain region, each source region and drain region are provided in the substrate surface area, and described source region and drain region sandwich therebetween and separate each other by raceway groove being formed semiconductor regions;
Be provided at the gate insulating film on the raceway groove formation semiconductor regions;
Single-crystal control region is provided in the substrate surface area and forms the semiconductor regions electricity with raceway groove to isolate;
The control gate dielectric film that on single-crystal control region, provides;
Floating boom, be provided on the gate insulating film and the control gate dielectric film on with the single-crystal control region capacitive couplings;
Be provided at the charge balance shadowing insulation film on the floating boom, and form by a kind of method in thermal chemical vapor deposition method, free radical CVD (Chemical Vapor Deposition) method and the light assistant chemical vapor deposition method; With
Cover conducting film, be provided on the charge balance shadowing insulation film and with the floating boom capacitive couplings.
10. according to the floating gate non-volatile memory of claim 9, wherein substrate comprises Semiconductor substrate; Single-crystal control region and raceway groove form semiconductor regions and separate, and have the conduction type opposite with substrate surface area.
11. a floating gate non-volatile memory comprises:
Substrate, the semiconductor layer that comprises support substrates and insulate with support substrates;
The raceway groove that is provided in the semiconductor layer forms semiconductor regions;
Source region and drain region, each source region and drain region are provided in the semiconductor layer, and described source region and drain region sandwich therebetween and separate each other by raceway groove being formed semiconductor regions;
Be provided at the gate insulating film on the raceway groove formation semiconductor regions;
Single-crystal control region is provided in the semiconductor layer and with raceway groove and forms semiconductor regions electricity isolation by dielectric film;
The control gate dielectric film that on single-crystal control region, provides;
Floating boom, be provided on the gate insulating film and the control gate dielectric film on with the single-crystal control region capacitive couplings;
Be provided at the charge balance shadowing insulation film on the floating boom; With
Cover conducting film, be provided on the charge balance shadowing insulation film and with the floating boom capacitive couplings.
12. according to the floating gate non-volatile memory of claim 11, wherein the charge balance shadowing insulation film is to form by a kind of method in thermal chemical vapor deposition method, free radical CVD (Chemical Vapor Deposition) method, the light assistant chemical vapor deposition method.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP97328/04 | 2004-03-30 | ||
| JP2004097328 | 2004-03-30 | ||
| JP198841/04 | 2004-07-06 |
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| Publication Number | Publication Date |
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| CN1734770A CN1734770A (en) | 2006-02-15 |
| CN100539155C true CN100539155C (en) | 2009-09-09 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2005100697806A Expired - Fee Related CN100539155C (en) | 2004-03-30 | 2005-03-30 | Floating gate non-volatile memory |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4868632A (en) * | 1987-07-31 | 1989-09-19 | Director General Of Agency Of Industrial Science And Technology | Nonvolatile semiconductor memory |
| US5892258A (en) * | 1996-07-17 | 1999-04-06 | Nec Corporation | Read-only semiconductor memory device |
| US6180456B1 (en) * | 1999-02-17 | 2001-01-30 | International Business Machines Corporation | Triple polysilicon embedded NVRAM cell and method thereof |
| US6255166B1 (en) * | 1999-08-05 | 2001-07-03 | Aalo Lsi Design & Device Technology, Inc. | Nonvolatile memory cell, method of programming the same and nonvolatile memory array |
-
2005
- 2005-03-30 CN CNB2005100697806A patent/CN100539155C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4868632A (en) * | 1987-07-31 | 1989-09-19 | Director General Of Agency Of Industrial Science And Technology | Nonvolatile semiconductor memory |
| US5892258A (en) * | 1996-07-17 | 1999-04-06 | Nec Corporation | Read-only semiconductor memory device |
| US6180456B1 (en) * | 1999-02-17 | 2001-01-30 | International Business Machines Corporation | Triple polysilicon embedded NVRAM cell and method thereof |
| US6255166B1 (en) * | 1999-08-05 | 2001-07-03 | Aalo Lsi Design & Device Technology, Inc. | Nonvolatile memory cell, method of programming the same and nonvolatile memory array |
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| CN1734770A (en) | 2006-02-15 |
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