CN100539425C - Analogue-to-digital converters - Google Patents
Analogue-to-digital converters Download PDFInfo
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- CN100539425C CN100539425C CNB2004800179694A CN200480017969A CN100539425C CN 100539425 C CN100539425 C CN 100539425C CN B2004800179694 A CNB2004800179694 A CN B2004800179694A CN 200480017969 A CN200480017969 A CN 200480017969A CN 100539425 C CN100539425 C CN 100539425C
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Abstract
A kind of system and method that is used to proofread and correct the output distortion of analogue-to-digital converters is disclosed, comprise: estimate this output distortion, the distortion of an estimation is provided, and the output of these analogue-to-digital converters and estimated distortion is combined to compensate this output distortion.The compensating module that is used to proofread and correct the output distortion of analogue-to-digital converters comprises: a calibration module, and it is configured to estimate this output distortion; And a combiner, it is configured to the output of these analogue-to-digital converters and estimated distortion combined, so that compensate this output distortion.
Description
The cross reference of related application
The title that the application requires on June 27th, 2003 to submit to is the U.S. Provisional Patent Application No.60/483 of " ANALOG-TO-DIGITAL CONVERTER (analogue-to-digital converters) ", the priority of 493 (attorney docket No.OPTIP004+), this application is quoted with as a reference at this.
The title that the application requires on July 10th, 2003 to submit to is the U.S. Provisional Patent Application No.60/486 of " ANALOG-TO-DIGITAL CONVERTER (analogue-to-digital converters) ", the priority of 053 (attorney docket No.OPTIP005+), this application is quoted with as a reference at this.
Invention field
The present invention relates in general to a kind of analogue-to-digital converters (ADC).More particularly, distortion correction analogue-to-digital converters (DCADC) and be used for the method for correcting distortion are disclosed.
Background of invention
Analogue-to-digital converters (ADC) are a kind of devices that is used to continuous time signal is mapped to the digital value in sampling time.It is widely used in the electronic system.
Desirable ADC in its output without any error.Sinusoidal input signal by a desirable ADC sampling does not have any harmonic wave at frequency domain.Yet in practice, ADC is not desirable.The mismatch of ADC element and non-linear the introducing make the error of output distortion of ADC.The sinusoidal signal of sampling has harmonic wave at frequency domain, and signal fidelity is lowered.
Can improve the quality of ADC by fine setting ADC, to obtain the transfer characteristic of expectation.Fig. 1 is the block diagram that an explanation is used to improve the system of ADC quality.A digitlization sinusoidal reference signal is sent to one 16 figure place analog-to-digital converter (DAC) 102.This DAC has good transfer characteristic and low noise.Its output is sent to 16 ADC104 to be measured.The sample output of this DAC of this ADC sends to its output a filter 106 of carrying out fast Fourier transform (FFT) simultaneously.If the output of FFT is confirmed as having tangible harmonic distortion, then some assembly of ADC is finely tuned.This trim process changes resistance or the electric capacity of ADC usually, can reduce the harmonic distortion of ADC like this.
About the fine setting technology several problems are arranged.Need take time and test and fine setting ADC, increase manufacturing cost like this.The design of trimming circuit has also increased the complexity of ADC.In addition, circuit is finely tuned so that may influence ADC transfer characteristic conversely other frequency for the transfer characteristic of a frequency adjustment ADC.It is desirable to have a kind of like this technology, it can proofread and correct the distortion among the ADC, does not increase the complexity or the manufacturing cost of circuit simultaneously.If this technology can be proofreaied and correct the distortion on the whole operation frequency spectrum of ADC, this technology will be useful so.
The accompanying drawing summary
The detailed description that the present invention is undertaken by following conjunction with figs. will be easy to be understood, the wherein identical identical element of Reference numeral indication, wherein:
Fig. 1 is the block diagram that one of explanation is used to improve the system of ADC quality.
Fig. 2 A is the block diagram of explanation according to the operation of the analogue-to-digital converters of an embodiment.
Fig. 2 B illustrates a block diagram of distortion correction analogue-to-digital converters according to an embodiment of the invention.
Fig. 3 is block diagram that has the analogue-to-digital converters model of distortion according to an embodiment of the invention of explanation.
Fig. 4 A illustrates the block diagram of the DCADC under training mode according to an embodiment of the invention.
Fig. 4 B is the block diagram of explanation in the steady state operation of the ADC embodiment shown in Fig. 4 A.
Fig. 5 is the block diagram that the DCADC embodiment that a noise signal source trains is used in one of explanation.
Fig. 6 is the block diagram that another distortion correction analogue-to-digital converters embodiment that a low noise digital-analog converter trains is used in one of explanation.
Fig. 7 is that a block diagram that adds another distortion correction analogue-to-digital converters embodiment that the digital-analog convertor of making an uproar trains is used in one of explanation.
Fig. 8 illustrates the block diagram of the steady state configuration of distortion correction analogue-to-digital converters according to an embodiment of the invention.
Fig. 9 A is the block diagram that the details of the digital signal processor that is used in distortion correction analogue-to-digital converters according to an embodiment of the invention is described.
Fig. 9 B has illustrated the details of the linear filter of being showed 900 in Fig. 9 A.
Figure 10 is the block diagram of a multistage according to an embodiment of the invention distortion correction analog to digital receiver of explanation.
Figure 11 is block diagram that comprises the receiver circuit of distortion correction analogue-to-digital converters according to an embodiment of the invention of explanation.
Specifically describe
The present invention can implement in many ways, comprises as a kind of processing, an equipment, a system, composition of matter, a computer-readable medium (for example computer-readable recording medium) or a computer network (wherein program command is sent out by optics or electronic communication link) implementing.In this manual, these implementations or any other form that the present invention taked are called as " technology ".Usually, the sequence of steps of disclosed processing can be changed within the scope of the invention.
Accompanying drawing together with the explanation principle of the invention provides detailed description to one or more embodiment of the invention below.The present invention gets in touch these embodiment and is described, but the invention is not restricted to any embodiment.Scope of the present invention only is defined by claims, and the present invention simultaneously comprises multiple alternative, modification and equivalents.A plurality of specific detail have been set forth in the following description so that thorough understanding of the present invention to be provided.These details are provided for purpose for example, and the present invention can realize according to the claims that do not have these specific detail.For the sake of clarity, technologic material known in the technical field involved in the present invention is not described in detail, in order to avoid unnecessarily fuzzy the present invention.
A kind of improved technology that is used at the output correcting distortion of analogue-to-digital converters is disclosed.In certain embodiments, distortion correction analogue-to-digital converters (DCADC) use a calibration module, and this calibration module is trained the distortion that compensates in the output of traditional ADC.In certain embodiments, this calibration module carries out modeling for highest significant position (MSB) to the interference effect of least significant bit (LSB).This calibration module can use a random noise generator, a conventional digital-analog converter (DAC) or one to add the DAC that makes an uproar and train.In certain embodiments, this calibration module comprises a non-linear, digital signal processor (DSP), and it comprises linear filter and nonlinear elements.Described DCADC can comprise several ADC levels and several calibration module.In certain embodiments, described DCADC can be used to proofread and correct the distortion in the entire circuit.Described technology is applied to polytype ADC architecture, comprises pipeline system structure, foldable structure and sigma-delta structures.
Fig. 2 A is the block diagram of description according to the operation of the analogue-to-digital converters of an embodiment.ADC 200 has the output of N position, and N is an integer here.The carry-out bit of each quantification of this ADC is defined as m
j, here j ∈ 0,1 ..., N-1} and m
j∈ 0,1}.What be input to ADC 200 is analog signal 204, and it can be represented as follows:
X=m
N-12
N-1+ m
N-22
N-2...+m
12
1+ m
02
0+ u (equation 1)
Here u is the signal value that is lower than minimum ADC quantization level.
The output of a desirable ADC can be represented as:
y
i=m
N-12
N-1+ m
N-22
N-2...+m
12
1+ m
02
0(equation 2)
In practice, ADC output has some distortions.Its output can be counted as the combination of two components: a desirable output component 206 and a distortion component 208.These two components are combined, to provide actual output 210.As here using, described combination refers to carries out subtraction, addition or any other suitable computing to two or more signals.
Fig. 2 B illustrates a block diagram of distortion correction analogue-to-digital converters according to an embodiment of the invention.This DCADC comprises an ADC 250 and a calibration module 254, and this ADC comprises that one is the digitizer of digital signal with analog signal conversion.Each assembly of this DCADC can be implemented with single integrated circuit, discrete assembly or any other suitable scheme.The output of ADC 250 comprises a desirable output component 260 and a distortion output component 262.Calibration module 254 is used to produce a signal that this distortion output component is carried out modeling.Combiner 266 deducts the output of this calibration module from the output of ADC, thereby output is approximately the output signal 268 of desirable output.
Described distortion output component can be by following modeling:
Y=m
N-1k
N-12
N-1+ m
N-2k
N-22
N-2...+m
1k
12
1+ m
0k
02
0(equation 3)
Here k
jBe one and equal 1 constant ideally, but when distortion exists, can depart from 1 with certain quantification deviation.
For example, if k
N-1If=1.001 and m
N-1=1, m then
N-1k
N-12
N-1One is 2 to the contribution that quantizes
N-1+ 0.0012
N-1, here 2
N-1Be desired carry-out bit, the while 0.0012
N-1Be distortion; If m
N-1=0, then this is to not contribution of distortion.Identical analysis can be applied to any m
j
Other equation also can be used to more complicated forms of distortion is carried out modeling.In certain embodiments, described output also comprises one-component u, and its expression is as the distortion of the function of the cross-term of position, and is as follows:
U=m
N-1q
N-1m
N-2q
N-22
N-2+ m
N-2q
N-2m
N-3q
N-32
N-3(equation 4)
For the identical quantification error deviation in highest significant position (MSB) and least significant bit (LSB), more the position of high-order is bigger than the position of low order more to the contribution of distortion.Get back to equation 3, at one wherein among the ADC of N=8, k
1And k
N-1Be 0.001, the contribution to distortion is for 0.0012 of position 1 accordingly
1With for 0.0012 of position 7
7Therefore, in practice, the output distortion of most of ADC comes from its more quantification deviation of the position of high-order.In addition, more the contribution of the position of high-order is more remarkable on how much compared with the contribution of the position of low order more.Therefore, DCADC need not to proofread and correct an error relevant with the position of low order more and just can obtain good performance.
Fig. 3 is block diagram that has the analogue-to-digital converters model of distortion according to an embodiment of the invention of explanation.Signal 300 is that it is represented as X to the analog input of a N position ADC
nThe ideal output of this ADC is divided into two components, signal 302 and 304.Component 3 02 comprises the highest significant position of k position.Component 3 04 comprises the least significant bit of (N-k) position.Combiner 305 composite signals 302 and 304 are exported a desirable ADC signal 306.For the influence of approximate distortion, only operate by 312 pairs of highest significant positions of distortion model.The output of this distortion model (signal 308) is distortion component.Desirable output 306 and distortion component 308 are combined to produce actual output, and promptly signal 310.
In certain embodiments, the actual output of an ADC can be represented as follows:
W=m
N-12
N-1+ m
N-22
N-2...+m
12
1+ m
02
0+ f (m
N-1, m
N-2, m
N-3, m
N-4) (equation 5)
Here, f (m
N-1, m
N-2, m
N-3, m
N-4) be the transfer function of distortion model.In certain embodiments, it be more high-order the position nonlinear function.Should be noted that a distortion that is caused by the position of low order more is left in the basket, the quantity of the position of the more high-order of selecting for this nonlinear function depends on specific implementation simultaneously, and can change for other embodiment.Replacedly, w can be represented as:
W=y+f (m
j) (equation 6)
Here y is desirable ADC output, f (m simultaneously
j) be a nonlinear function of carry-out bit.
Quantization error can be represented as actual output and the input between poor:
ε=w-x=f (m
N-1, m
N-2, m
N-3, m
N-4)-u (equation 7)
In certain embodiments, DCADC comprises a calibration module, and this calibration module is trained the nonlinear distortion component f (m to ADC
N-1, m
N-2, m
N-3, m
N-4) carry out modeling.The output of ADC can be corrected by deduct described nonlinear distortion component from its actual output.Fig. 4 A illustrates the block diagram of the DCADC under training mode according to an embodiment of the invention.In this embodiment, this calibration module comprises a digital signal processor (DSP) 422.Signal 400 is the analog input signals to ADC 420.The output of this ADC comprises a desirable output signal 404 and a distortion component 406. Signal 404 and 406 is combined to form the actual output 408 of this ADC.Signal 408 is sent to DSP 422, and it exports an estimated distortion signal 414.DSP 422 is suitable for improving its distortion estimator by the difference that minimizes between this distortion estimator and the output distortion.
Fig. 4 B is the block diagram of explanation in the steady state operation of the ADC embodiment shown in Fig. 4 A.Under stable state, the adaptation path of this DSP disconnects.DSP uses its configuration that obtains during training managing to come distortion is carried out modeling and exported a distorted signal 460.This distorted signal is deducted from the output (signal 456) of ADC.Resulting signal 458 is process error correction, and has much smaller distortion compared with signal 456.
In practice, possibly can't obtain desirable training signal.Several methods of desirable training signal that do not need come into question.These methods have been utilized such principle: for desirable ADC, incoherent analog input signal causes incoherent quantification carry-out bit.Following Example has illustrated this principle.
The hypothetical universe distortion is less relatively, and then amount distortion can be represented with LSB.Make that nonlinear distortion is as follows:
F (m
N-1, m
N-2, m
N-3, m
N-4)=m
N-12
1+ m
N-22
0(equation 7)
The actual output of DSP can be represented as follows:
W=m
N-12
N-1+ m
N-22
N-2...+(m
1+ m
N-1) 2
1+ (m
0+ m
N-2) 2
0(equation 8)
Position N-1 and 1 is because they all have component common m
N-1Thereby be correlated with; Position N-2 and 0 is because they all have component common m
N-2Thereby be correlated with.
In this example, calibration module is trained to export an analog distortion signal (m who is deducted from w
N-1) 2
1+ (m
N-2) 2
0Resulting signal is a calibrated output that is approximately equal to desirable ADC output.
In order correctly to train calibration module, the training input signal of ADC preferably at random, equally distributed and incoherent.Fig. 5 is the block diagram that the DCADC embodiment that a noise signal source trains is used in one of explanation.Evenly noise signal source 500 provides one at random and incoherent analog signal 516.This even noise signal source can use a thermal noise source or any other suitable element to realize.Signal 516 is sent to ADC 502.If ADC 502 is desirable, its output will be the position of stochastic independence.Yet in practice, ADC is not desirable, and its carry-out bit is not incoherent fully.In this embodiment, the output w of ADC 502 is with identical at the w shown in the equation 8.The output signal 506 of this ADC comprises two MSB, and can be represented as follows:
y
MSB=m
N-12
N-1+ m
N-22
N-2(equation 9)
The output signal 510 of this ADC comprises two LSB and the distortion component that is associated with MSB.It can be represented as:
y
LSBE=(m
12
1+ m
02
0)+(m
N-12
1+ m
N-22
0) (equation 10)
Modeling is carried out in the distortion of 504 couples of ADC that are associated with MSB of DSP.Its output signal 508 is deducted from signal 510.Resulting adaptation signal 512 is approximately undistorted LSB.In other words, each in signal 512 is approximate random; Any correlation in signal mainly is because the model of this DSP and the difference between the actual distortion function cause.Signal 512 be fed back to this DSP in case its operation is carried out adaptive, thereby any interference of filtering between each MSB and each LSB.Some wherein correlation be that described DSP is a nonlinear filter among the non-linear embodiment.The details of non-linear DSP will come into question in Fig. 9 A and 9B.
Fig. 6 is the block diagram that another distortion correction analogue-to-digital converters embodiment that a low noise digital-analog converter trains is used in one of explanation.ADC 602 has the linearity of N position.DAC 600 is low noise K position DAC, and K is preferably less than N here.DAC600 preferably has the linearity that is better than the N position.This DAC provides an input signal 614 to ADC.In this embodiment, the output w of ADC 602 identical with shown in the equation 8.The output signal 606 of this ADC comprises two MSB, and can be expressed as equation 9.
Because DAC 600 has the position still less than ADC 602, if therefore this ADC is desirable, then each LSB of this ADC will be zero.When distortion existed, each LSB comprised the component from each MSB.The output signal 610 of this ADC can be expressed as:
y
LSBE=m
N-12
1+ m
N-22
0(equation 11)
DSP 604 outputs 608 of convergence so that an offseting signal 610 to be provided.Resulting adaptation signal 612 is fed back to this DSP to be used for that its output is adjusted to more closely matched signal 610.Use a low noise DAC to provide training signal to allow this DSP to restrain quickly.
Fig. 7 is that a block diagram that adds another distortion correction analogue-to-digital converters embodiment that the digital-analog convertor of making an uproar trains is used in one of explanation.This circuit is similar to Fig. 6's, but DAC 700 can be one nonideal, add the K position DAC that makes an uproar, K is preferably less than N here.Dissimilar imperfect DAC can be used, for example dynamic element coupling (DEM) DAC.The output signal 706 of ADC 702 comprises two MSB, and can be represented as equation 9.The output signal 710 of this ADC comprises MSB component and noise.It can be represented as:
y
LSBE=m
N-12
1+ m
N-22
0+ u (equation 12)
DSP 704 outputs 708 of convergence so that an offseting signal 710 to be provided.Resulting adaptation signal 712 is fed back to this DSP to be used for that its output is adjusted to more closely matched signal 710.Restrain than slower with a DSP who adds the DAC training of making an uproar, so but more cheap often more cost is effective than low noise DAC usually owing to add the DAC that makes an uproar with the DSP of a low noise DAC training.
It should be noted, use the training signal in Fig. 5-7 to cover the entire spectrum of ADC usually, thereby obtain distortion correction for each frequency of operation of this ADC.
Fig. 8 illustrates the block diagram of the steady state configuration of distortion correction analogue-to-digital converters according to an embodiment of the invention.In case its calibration module is restrained, this DCADC just finishes its cycle of training and enters steady state operation.During steady state operation, the adaptation feedback path of described DSP disconnects.Analog input signal 800 is sent to an ADC 802 to be converted into digital signal.The output signal 806 of this ADC comprises MSB, and the output signal 810 of this ADC comprises the LSB that is with distortion simultaneously.Signal 806 is sent to DSP 804, and this DSP utilizes its coefficient that obtains during cycle of training to duplicate distortion and produces an output signal 806.Signal 806 is deducted from signal 810, thereby obtains being approximately the signal 812 of the desirable more low order carry-out bit of this ADC.This configuration can be applied in the steady state operation of DCADC usually, is included in those operations shown in Fig. 5-7.
The distortion of ADC often is non-linear.The nonlinear effect of using conventional art to compensate ADC is the task of a difficulty.The title of submitting on February 21st, 2003 is the U.S. Patent application No.10/372 of the Batruni of " NONLINEAR FILTER (nonlinear filter) ", 638 (attorney docket No.OPTIP001) and the title of submitting on April 18th, 2003 are the U.S. Patent application No.10/418 of the Batruni of " NONLINEAR INVERSION (non-linear paraphase) ", (quote these patents with for referencial use at this) among 944 (the attorney docket No.OPTIP002), Batruni has described and has been used to use linear element structure nonlinear filter and is used for the improved technology of adaptive this nonlinear filter with the transfer characteristic of acquisition expectation.These technology greatly reduce the complexity that is associated with compensation of nonlinear effects, can be applied to simultaneously in the design and configuration of DCADC.Fig. 9 A-9B has illustrated some in these technology.
Fig. 9 A is the block diagram that the details of the digital signal processor that uses in distortion correction analogue-to-digital converters according to an embodiment of the invention is described.An input vector X is sent to one group of linear feedforward filter (900,902,904 and 906).Each filter output quilt and several coefficient (b
0, β
1, β
2And β
3) combined, handle by one group of nonlinear processor then.In this embodiment, these nonlinear processors are implemented as absolute value operators (908,910 and 912).The result of these absolute value operation is multiplied by coefficient C
1, C
2And C
3, and be combined to form an output signal 914.The transfer characteristic of this DSP can be represented as follows:
Y=ax+b+c
1| α
1X+ β
1|+c
2| α
2X+ β
2|+c
2| α
2X+ β
2|+c
3| α
3X+ β
3| (equation 13)
At training period, adaptive its transfer function of described DSP, this is by regulating its coefficient and using such as the back-propagating characteristic of the technology of lowest mean square (LMS) algorithm and derivative to come better the distortion component of signal 916 is carried out modeling.
Fig. 9 B has illustrated the details of the linear filter of being showed 900 in Fig. 9 A.Use a multiplier 950, with a factor a
0Come the described input vector X of convergent-divergent.This input also is sent to a plurality of delay-level (952-964).The signal that comes convergent-divergent to be delayed with factor a1-a7 respectively.Scaled signal is combined by a combiner 966.
Figure 10 is the block diagram of a multistage according to an embodiment of the invention distortion correction analog to digital receiver of explanation.Its input is a noise source 1000.Four k position ADC (ADC 1) are used to produce the output with ADC of 4k position.In this embodiment, k is 5.Several DSP be coupled to each ADC level with the position of offsetting high-order more to the interference effect of the position of low order more.In case more the influence of the position of high-order is removed from the position of low order more, identical processing is just stood in resulting position: the influence of promptly removing them from the position of low order more.ADC1 produces the position A of high-order, and it is represented as m
192
19+ m
182
18+ m
172
17+ m
162
16+ m
152
15The position of high-order is sent to DSP 1, and it is trained to the interference effect of the position of removing high-order from the position of the more low order that is produced by ADC 1004.Resulting signal 1002 through distortion correction is represented as n
142
14+ n
132
13+ n
122
12+ n
112
11+ n
102
10
The output of ADC 1 also is sent to DSP 2 and DSP 3, so that from the position of the more low order that produces by ADC 3 and ADC 4, remove the influence of disturbing respectively, thus picked up signal 1004 and 1006.Any interference effect that is sent to also that DSP 4 and DSP 5 remove further that it may have through the signal 1002 of distortion correction to the position of the more low order that produces by each DSP.Similarly, signal 1008 is sent to DSP 6, and this DSP is trained to and removes any interference that is present in the signal 1010.Signal 1008 and 1012 through distortion correction is represented as n respectively
92
9+ n
82
8+ n
72
7+ n
62
6+ n
52
5And n
42
4+ n
32
3+ n
22
2+ n
12
1+ n
02
0
It should be noted and depend on specific implementation in the quantity of each ADC level meta, the quantity of level and the quantity of employed DSP.Identical general architecture can be modified to ADC level and the DSP that uses varying number.
Calibration module in a DCADC also can be used to proofread and correct the distortion in the entire circuit that comprises this DCADC.A receiver circuit example is discussed for purposes of illustration, but is should be noted that this DCADC also can be used to proofread and correct the distortion in transmitter circuitry or any other proper circuit.
Figure 11 is block diagram that comprises the receiver circuit of distortion correction analogue-to-digital converters according to an embodiment of the invention of explanation.This receiver circuit comprises automatic gain control (AGC) 1104, buffers 1102 and a DCADC 1100.There are several signal sources to can be used for training this circuit, comprise a DEM DAC 1108, a traditional low noise DAC 1110 and a random noise generator 1112.Switch 1106 is selected in these signal sources during training managing.Calibration module among the DCADC 1100 not only is suitable for proofreading and correct the distortion among this ADC self, also is suitable for proofreading and correct the distortion of being introduced by described AGC and buffer.In case training is finished, switch 1106 just is connected to interface 1114, and this circuit operation is in its steady-state mode simultaneously, and wherein the distortion in the entire circuit is proofreaied and correct by the calibration module of this DCADC.
A kind of improved technology that is used to proofread and correct output distortion is disclosed.Several use calibration modules come the embodiment of compensating distortion to come into question.This technology provides low distortion output and has not had significantly to increase the manufacturing cost of ADC on a wide spectrum.
Though described in detail aforementioned summary of the invention, clearly can put into practice specific change and modification within the scope of the appended claims for the purpose of being convenient to understand.Should be noted that processing of the present invention and equipment can have multiple replacement implementation.Therefore, top embodiment should be counted as illustrative and be nonrestrictive, and the invention is not restricted to details given here, but can make amendment to it within the scope of the appended claims.
Claims (23)
1. method of proofreading and correct the output distortion of analogue-to-digital converters comprises:
Estimate this output distortion;
The distortion of an estimation is provided;
The output of these analogue-to-digital converters and estimated distortion is combined, so that compensate this output distortion, and
Train a calibration module.
2. as the method for the output distortion of analogue-to-digital converters of correction of citation in claim 1, wherein said output distortion comprises the output distortion of described analogue-to-digital converters.
3. as the method for the output distortion of analogue-to-digital converters of correction of citation in claim 1, wherein said output distortion comprises the output distortion of a circuit, and this circuit comprises described analogue-to-digital converters.
4. as the method for the output distortion of analogue-to-digital converters of correction of citation in claim 1, wherein train a calibration module to comprise and train a calibration module adaptively.
5. as the method for the output distortion of analogue-to-digital converters of correction of citation in claim 1, wherein this calibration module comprises a digital signal processor.
6. as the method for the output distortion of analogue-to-digital converters of correction of citation in claim 1, wherein this calibration module comprises a nonlinear filter.
7. the method for the output distortion of analogue-to-digital converters of correction of citation as in claim 1, wherein this calibration module comprises a nonlinear filter, and this nonlinear filter comprises at least one linear filter that is coupled with at least one non-linear element.
8. the method for the output distortion of analogue-to-digital converters of correction of citation as in claim 1, wherein:
This calibration module comprises a nonlinear filter;
This nonlinear filter comprises at least one linear filter with a non-linear element coupling; And
This nonlinear filter comprises each delay-level.
9. as the method for the output distortion of analogue-to-digital converters of correction of citation in claim 1, wherein train this calibration module to comprise an analog signal is applied to these analogue-to-digital converters and this Analog signals'digital version is applied to this calibration module.
10. as the method for the output distortion of analogue-to-digital converters of correction of citation in claim 1, wherein train this calibration module to comprise first signal is applied to these analogue-to-digital converters and secondary signal is applied to this calibration module.
11., wherein train this calibration module to comprise that an error adaptation signal of feedback is so that adaptive this calibration module as the method for the output distortion of analogue-to-digital converters of correction of citation in claim 1.
12., wherein train this calibration module to comprise error adaptation signal of feedback so that use a kind of lowest mean square technology to come adaptive this calibration module as the method for the output distortion of analogue-to-digital converters of correction of citation in claim 1.
13. as the method for the output distortion of analogue-to-digital converters of correction of citation in claim 1, wherein:
This calibration module comprises a nonlinear filter; And
Training this calibration module to comprise is applied to a signal this calibration module and feeds back an error adaptation signal so that a coefficient of adaptive this nonlinear filter.
14. as the method for the output distortion of analogue-to-digital converters of correction of citation in claim 1, wherein said training comprises:
Select a highest significant position output of these analogue-to-digital converters;
Selected highest significant position output is applied to this calibration module;
And adaptive this calibration module.
15. as the method for the output distortion of analogue-to-digital converters of correction of citation in claim 1, wherein said training comprises:
Select a highest significant position output of these analogue-to-digital converters;
Selected highest significant position output is applied to this calibration module; And
Adaptive this calibration module is to reduce the interference of selected highest significant position output to a least significant bit output of these analogue-to-digital converters.
16., wherein train a calibration module to comprise and use an even noise source to train a calibration module as the method for the output distortion of analogue-to-digital converters of correction of citation in claim 1.
17., wherein train a calibration module to comprise and use a digital-analog convertor to train a calibration module as the method for the output distortion of analogue-to-digital converters of correction of citation in claim 1.
18. as the method for the output distortion of analogue-to-digital converters of correction of citation in claim 1, wherein train a calibration module to comprise and use a digital-analog convertor to train a calibration module, wherein this digital-analog convertor comprises than these analogue-to-digital converters carry-out bit still less.
19., wherein train a calibration module to comprise and use a dynamic element coupling digital-analog convertor to train a calibration module as the method for the output distortion of analogue-to-digital converters of correction of citation in claim 1.
20. distortion correction analogue-to-digital converters comprise:
First analogue-to-digital converters, it is configured to provide first output;
Second analogue-to-digital converters, it is configured to provide second output with first output distortion;
Be coupled to first calibration module of these first analogue-to-digital converters, it is trained to estimates this first output distortion and first distortion estimator is provided; And
First combiner, be used for this second output with this first distortion estimator combined so that compensate this first output distortion and first signal through error correction be provided.
21. the distortion correction analogue-to-digital converters as citation in claim 20 further comprise:
The 3rd analogue-to-digital converters, it is configured to provide the 3rd output with second output distortion;
Be coupled to second calibration module of these first analogue-to-digital converters, it is configured to estimate this second output distortion and second distortion estimator is provided; And
Second combiner, be used for the 3rd output with this second distortion estimator combined so that compensate this second output distortion and second signal through distortion correction be provided.
22. the distortion correction analogue-to-digital converters as citation in claim 20 further comprise:
Be coupled to the 3rd calibration module of this first combiner, its be configured to estimate from described first the signal through error correction obtain second through a distortion component of the signal of distortion correction and the 3rd distortion estimator is provided;
The 3rd combiner, be used for this second combined through the signal and the 3rd estimated signal of distortion correction so that the 3rd signal through distortion correction is provided.
23. a method of proofreading and correct the output distortion of analogue-to-digital converters comprises:
Determine the estimated distortion in the least significant bit from a highest significant position; And
The output of these analogue-to-digital converters and estimated distortion is combined, so that compensate this output distortion;
Wherein saidly determine that the value that is independent of this least significant bit carries out.
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| US48349303P | 2003-06-27 | 2003-06-27 | |
| US60/483,493 | 2003-06-27 | ||
| US60/486,053 | 2003-07-10 | ||
| US60/641,332 | 2003-08-14 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008042202A2 (en) * | 2006-09-29 | 2008-04-10 | Optichron, Inc. | Adaptive self-linearization |
| CN101729069B (en) * | 2008-10-27 | 2011-12-28 | 承景科技股份有限公司 | Successive approximation type analog-to-digital converter with binary fault tolerant mechanism |
| EP2894788B1 (en) * | 2012-09-07 | 2017-04-12 | Asahi Kasei Microdevices Corporation | Sample hold circuit, a/d converter, calibration method of the sample hold circuit, and circuit |
| US10382048B2 (en) * | 2015-05-28 | 2019-08-13 | Analog Devices, Inc. | Calibration of analog-to-digital converter devices |
| KR102642577B1 (en) * | 2016-12-12 | 2024-02-29 | 엘지디스플레이 주식회사 | Driver Integrated Circuit For External Compensation And Display Device Including The Same And Data Calibration Method of The Display Device |
| US10541699B1 (en) * | 2018-10-11 | 2020-01-21 | Nxp B.V. | Signal processing and conversion |
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| US5182558A (en) * | 1991-10-25 | 1993-01-26 | Halliburton Geophysical Services, Inc. | System for generating correction signals for use in forming low distortion analog signals |
| US6411233B1 (en) * | 2000-06-06 | 2002-06-25 | Marvell International Ltd | Method and apparatus for direct RAM analog-to-digital converter calibration |
| US6449569B1 (en) * | 1998-12-11 | 2002-09-10 | Cirrus Logic, Inc. | Calibration and compensation of delta sigma ADC's and DAC's by correlating noise signals |
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| US5182558A (en) * | 1991-10-25 | 1993-01-26 | Halliburton Geophysical Services, Inc. | System for generating correction signals for use in forming low distortion analog signals |
| US6449569B1 (en) * | 1998-12-11 | 2002-09-10 | Cirrus Logic, Inc. | Calibration and compensation of delta sigma ADC's and DAC's by correlating noise signals |
| US6411233B1 (en) * | 2000-06-06 | 2002-06-25 | Marvell International Ltd | Method and apparatus for direct RAM analog-to-digital converter calibration |
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