CN100544411C - Infrared focal plane array self-adapted digitalization method and circuit thereof - Google Patents

Abstract

The invention discloses a kind of infrared focal plane array self-adapted digitalization method and circuit thereof.The analog signal that the focal plane array output of this method changes with scene, this analog signal is through entering the A/D chip of adjustable input range after the filtering, and fpga chip is monitored the digitlization output of A/D chip at any time, and this output is judged; According to the result who judges series arrangement D/A chip is reconfigured, to provide different bias voltage to the A/D chip, adjust the input range of the analog signal of A/D chip, therefore just adjusted the digital output area of A/D chip, finish the self-adapted digitalization of focal plane array.The digit of A/D device of the present invention is occupied to greatest extent, has got rid of the blind element interference simultaneously, and the details resolution of image is greatly improved; Manually behind the setting threshold Δ, this threshold value Δ had very big range of application when both having guaranteed the practical application of infrared focal plane array self-adapted digitalization method, and image is unlikely when having guaranteed this method work simultaneously frequently flashes.

Description

Infrared focal plane array self-adapted digitalization method and circuit thereof

One technical field

The invention belongs to the thermal infrared imager its technical, particularly a kind of high-performance infrared focal plane array drives self-adapted digitalization method and circuit thereof.

Two background technologies

Infrared focal plane array (IRFPA) detector national defence and civilian in bringing into play enormous function, the lifting of infrared focal plane array complete machine performance also is the emphasis and the difficult point of current research, in order further to improve the performance of IRFPA, except improving constantly the development level of device, to improve the performance of probe unit and reading circuit, design high-caliber image processing board, also need to design corresponding high-performance drive circuit outside the high-efficient algorithm, make the IRFPA device be in optimum Working, to greatest extent the performance of the existing focal plane array of performance.

The infrared focal plane array seeker operate as normal needs digital drive signals, analog bias voltage signal, other control signals and stable focal plane temperature.Current common practices to the infrared focal plane array drive circuit is: the programmable logic device on the drive circuit board provides digital drive signals and other control signals of infrared focal plane array seeker need of work, and the analog bias voltage signal that the digital signal that provides serial D/A chip to need provides infrared focal plane array seeker to need by serial D/A chip, the temperature stabilization control chip is stablized the temperature (SuxiaXing of focal plane, Chengyi Huang, Benkang Chang, etal.The miniaturized design for drive circuits of320 * 240 uncooled infrared focal plane array[A] .Proc.SPIE, Vol.5204.).The analog signal of infrared focal plane array seeker operate as normal output is through entering the A/D device after the filtering, the digital signal of output offers the successive image disposable plates and uses.Wherein the general fashion that the digitlization of focal plane array simulation output is adopted is the i.e. fixing input range of the input analog channel of AD device of scope of fixedly AD device bias voltage, and its analog input scope is made as the maximum magnitude of the simulation output of infrared focal plane array seeker, to guarantee to bring into play to greatest extent the performance (Lai Rui of detector, Zhou Ming, Liu Shangqian. a kind of new infrared focus plane drive circuit system design able to programme [J]. laser is with outer, 2004,4 (34): 272-274.).

Yet during the focal plane array operate as normal, temperature peaks peak value in the visual field is often to change, conventional method according to the fixing input range of A/D input channel of the maximum output area of focal plane, just caused along with the input analog channel scope of the A/D of effective simulation output area of the variation focal plane of scene and setting and inconsistent, the huge waste that has directly caused digitlization output high-order portion, this waste has also just caused details resolution low of image, has influenced picture quality greatly.

In addition, also having method is to carry out histogram equalization or the like method on image processing board, though these software algorithms have changed image detail, but these details are to carry out under the situation of sacrificing other gray scales, the amplification but not whole tonal range can both stretch, this must be restricted in actual applications.

Three summary of the invention

The object of the present invention is to provide a kind of digital scope that utilizes the A/D device on the drive circuit to greatest extent, and the method and the circuit of the infrared focal plane array self-adapted digitalization of the details resolution of raising image.

The technical solution that realizes the object of the invention is: a kind of infrared focal plane array self-adapted digitalization method may further comprise the steps:

(1) provides the bias condition of focus planardetector need of work when the analog bias voltage signal, digital drive signals provides gain, integration, the synchronous digital signal of focal plane array detector, when the temperature stabilization control system is stablized the temperature of focal plane, the analog signal that focal plane array output changes with the visual field variations in temperature;

(2) this analog signal input A/D device after useless interference signal is eliminated in filtering carries out analog signal digital, the analog input scope of this A/D device is controlled by two bias voltages, promptly this A/D device is imported the FPGA device with the detection signal that overflows of digital signal and A/D device, this FPGA device is controlled series arrangement D/A chip simultaneously, the difference of control signal makes series arrangement D/A chip produce different voltage, this voltage is connected on the bias voltage of A/D device, in order to the analog signal input range of control A/D chip;

Wherein, the course of work of FPGA device is: this FPGA device detects the digital signal of A/D device at any time and overflows detection signal, and to digital signal with overflow detection signal analysis, calculate, with the result of analytical calculation is that the simulation output of focal plane array detector and the input range of A/D device are done contrast, if the simulation output area of focal plane array detector surpasses the input range of A/D device, then by adjusting the input range that digital signal that the FPGA device offers series arrangement D/A chip changes the bias voltage of A/D device and then transfers big A/D device; If the simulation output area of focal plane array detector is less than the input range of A/D device, the digital signal that FPGA then resets series arrangement D/A chip equally changes the bias voltage of A/D device and then to reset the analog signal input range of turning the A/D device down, like this through of at any time monitoring, the analytical calculation of FPGA device to the digitlization output of A/D device, and the revertive control A/D device by series arrangement D/A chip, finish the self-adapted digitalization of focal plane array.

In the infrared focal plane array self-adapted digitalization method of the present invention, when the simulation output area of focal plane array detector surpasses or less than the input range of A/D device, then fpga chip is according to the manual preset threshold Δ in outside, reset the input range of A/D device, guarantee that the maximum of analog signal input range of A/D device of current setting and minimum value are respectively than the big threshold value Δ of maximum m and the little threshold value Δ of minimum value n of the simulation output area of the current focal plane array that calculates, the simulation output area that is current focal plane array is [m, n], then the analog signal input range of A/D device need be made as [m+ Δ, n-Δ]; The analog signal input range adjustment of this A/D device is to change by the digital signal that the FPGA device offers series arrangement D/A chip to finish.

A kind of circuit of realizing above-mentioned infrared focal plane array self-adapted digitalization method, be included in and add digital drive signals, focal plane array detector under analog bias voltage signal and the temperature stabilization control system signal controlling, this focal plane array detector, the analog signal filter, the A/D chip is connected successively with the on-site programmable gate array FPGA chip, the digital signal output interface is set on this fpga chip, described fpga chip connects a series arrangement D/A chip, this series arrangement D/A chip is connected with the A/D chip, and promptly the serial digital signal of this fpga chip output makes series arrangement D/A chip produce the analog signal input range that two bias voltages are adjusted the A/D chip.

The present invention compared with prior art, its remarkable advantage is: the digit of (1) A/D device is occupied to greatest extent, has solved the problem of the high-order waste of numerical portion, has got rid of the blind element interference simultaneously, the details resolution of image is greatly improved; (2) behind the manual setting threshold Δ, this threshold value Δ had very big range of application when both having guaranteed the practical application of infrared focal plane array self-adapted digitalization method, and image is unlikely when having guaranteed simultaneously this method work again frequently flashes.

Below in conjunction with accompanying drawing the present invention is described in further detail.

Four description of drawings

Accompanying drawing is an infrared focal plane array self-adapted digitalization circuit structure diagram of the present invention.

Five embodiments

In conjunction with the accompanying drawings, infrared focal plane array self-adapted digitalization circuit of the present invention, be included in and add digital drive signals, focal plane array detector under analog bias voltage signal and the temperature stabilization control system signal controlling, this focal plane array detector, the analog signal filter, the A/D chip is connected successively with the on-site programmable gate array FPGA chip, the digital signal output interface is set on this fpga chip, described fpga chip connects a series arrangement D/A chip, this series arrangement D/A chip is connected with the A/D chip, and promptly the serial digital signal of this fpga chip output makes series arrangement D/A chip produce the analog signal input range that two bias voltages are adjusted the A/D chip.Above-mentioned infrared focal plane array self-adapted digitalization circuit is a digital scope of realizing utilizing to greatest extent the A/D device on the drive circuit through the following steps, and the details resolution of raising image, that is:

(1) provides the bias condition of focus planardetector need of work when the analog bias voltage signal, digital drive signals provides gain, integration, the synchronous digital signal of focal plane array detector, when the temperature stabilization control system is stablized the temperature of focal plane, the analog signal that focal plane array output changes with the visual field variations in temperature;

(2) this analog signal input A/D device after useless interference signal is eliminated in filtering carries out analog signal digital, and the analog input scope of this A/D device is controlled by two bias voltages;

(3) this A/D device is imported the FPGA device with the detection signal that overflows of digitized analog signal and A/D device, this FPGA device is controlled series arrangement D/A chip simultaneously, the difference of control signal makes series arrangement D/A chip produce different voltage, this voltage is connected on the bias voltage of A/D device, in order to the analog signal input range of control A/D chip;

(4) this FPGA device detects the digital signal of A/D device at any time and overflows detection signal, and to digital signal with overflow detection signal analysis, calculate, with the result of analytical calculation is that the simulation output of focal plane array detector and the input range of A/D device are done contrast, if the simulation output area of focal plane array detector surpasses the input range of A/D device, then transfer the input range of big A/D device by adjusting digital signal that the FPGA device offers series arrangement D/A chip; If the simulation output area of focal plane array detector is less than the input range of A/D device, FPGA then resets the digital signal of series arrangement D/A chip equally to reset the analog signal input range of turning the A/D device down, like this through of at any time monitoring, the analytical calculation of FPGA device to the digitlization output of A/D device, and the revertive control A/D device by series arrangement D/A chip, finish the self-adapted digitalization of focal plane array.Wherein, when the simulation output area of focal plane array detector surpasses or less than the input range of A/D device, then fpga chip is according to the manual preset threshold Δ in outside, reset the input range of A/D device, guarantee that the maximum of analog signal input range of A/D device of current setting and minimum value are respectively than the big threshold value Δ of maximum m and the little threshold value Δ of minimum value n of the simulation output area of the current focal plane array that calculates, the simulation output area that is current focal plane array is [m, n], then the analog signal input range of A/D device need be made as [m+ Δ, n-Δ]; The analog signal input range of this A/D device is to finish by the digital signal that the FPGA device offers series arrangement D/A chip.

Be example with the A/D chip AD9240 of ADI company and HgTeCd scanning of materials type 576 * 6 refrigeration detectors of domestic certain production of units below, specifically describe the infrared focal plane array self-adapted digitalization method.

This A/D chip can be regulated the input range of input channel:

V _CORE＝VINA-VINB (VINA，VINA∈[0，5]) (1)

-VREF≤V _CORE≤VREF (VREF∈[0，5]) (2)

Wherein: V _CORE: the core voltage of AD9240;

VINA, two analog input channels of VINB:AD9240;

The reference voltage of VREF:AD9240.

Table 1 AD9240 data output format

Table1 AD9240?data?output?format

According to (1), (2) and table 1 can obtain following formula:

$(\mathrm{VINA}-\mathrm{VINB}+\mathrm{VREF})\×\frac{2^{14}}{2\mathrm{VREF}}=\mathrm{CODE}---\left(3\right)$

Wherein: CODE represents 14 position digital signals of AD9240 output.

With VINB, VREF is as biasing voltage signal, and VINA receives the analog signal output of focal plane array, and VINA and CODE just can be tried to achieve mutually by formula (3) like this.

According to table 1, the maximum input range of AD9240 is determined by following formula:

VINB-VREF＝VINA _admin (4)

VINB+VREF＝VINA _admax (5)

Wherein: VINA _AdminExpression passage A the minimum voltage of receptible analog input signal;

VINA _AdmaxExpression passage A the maximum voltage of receptible analog input signal.

Used focal plane array detector is 6 grades of TDI, and the picture format that forms during operate as normal is 768 * 576, and its analog end output (SORTIE) dynamically output area is 0～5V, and promptly 0≤VINA '≤5 (wherein

The simulation output of expression focal plane array), link to each other with the first passage VINA of AD9240 after process filtering of detector output and the signal processing, according to formula (4) (5), can set the digital signal output area of AD9240 by serial D/A chip setting VINB and VREF.

The a certain moment t of 576 * 6 focal plane array work, focal plane array to the scope of the simulation output that scene in its visual field produces is $[m,n]\⋐\left[\mathrm{0,5}\right]$

Here m=min (pix1, pix2 ..., pix (768 * 576)), (6)

Represent minimum pixel voltage in a frame 576 * 768 images;

n＝max(pix1，pix2，...，pix(768×576)) (7)

Represent maximum pixel voltage in a frame 768 * 576 images;

The every frame of fpga chip all detects 14 position digital signals and the spill over OTR of AD9240.Ideally its course of work is divided into two kinds of situations:

1, focal plane array simulation output area exceeds the analog signal range that AD9240 can receive:

FPGA detects that the OTR signal is arranged in the two field picture is at 1 o'clock, according to table 1 as can be known focal plane array simulation output area surpass the analog signal range that AD9240 can receive, set VINB by series arrangement D/A chip immediately, VREF is 2.5V, according to formula (1), (2) maximum input (VINA) scope that can draw current AD9240 is [0,5] V, and this has guaranteed focal plane array output

The maximum input range that can not surpass AD9240.At this time according to the derivation of formula (3)

${\mathrm{VINA}}_{\min }={\mathrm{CODE}}_{\min }\×\frac{2\mathrm{VREF}}{2^{14}}+\mathrm{VINB}-\mathrm{VREF}---\left(8\right)$

${\mathrm{VINA}}_{\max }={\mathrm{CODE}}_{\max }\×\frac{2\mathrm{VREF}}{2^{14}}+\mathrm{VINB}-\mathrm{VREF}---\left(9\right)$

Wherein: CODE _Min, VINA _MinThe digital signal of representing minimum pixel voltage correspondence in the two field picture, analog signal;

CODE _Max, VINA _MaxThe digital signal of representing maximum pixel voltage correspondence in the two field picture, analog signal.

FPGA monitors next frame image C ODE subsequently _MinAnd CODE max, and according to formula (8), (9) calculate VINA _Min, VINA _Max, according to formula (4), (5) calculate suitable VINB, and VREF also puts on this biasing voltage signal on the AD9240 chip, finishes the self-adapted digitalization of focal plane array simulation output.

2, focal plane array simulation output area does not exceed the analog signal range that AD9240 can receive:

If detecting the OTR signal and be 0 is the input range that input range does not surpass the AD9240 that sets at present, then this moment, FPGA only monitored every two field picture CODE _MinAnd CODE _Max, and according to formula (8), (9) calculate VINA _Min, VINA _MaxAccording to formula (4), (5) calculate suitable VINB, and VREF also puts on this biasing voltage signal on the AD9240 chip, finish the self-adapted digitalization of focal plane array simulation output.

According to above-mentioned principle, the focal plane array column drive circuit can be with the bias voltage of the adjustment AD9240 of the Different Dynamic of scene temperature peaks peak value, and then " the full width of cloth " the as far as possible output after the assurance AD9240 digitlization, finish focal plane array self adaptation output based on scene.

According to the focal plane array self-adapted digitalization output that can finish on the above theory of algorithm based on scene, yet in fact said method is revised real being incorporated in the real system of ability because following several reasons must be passed through.Because there is blind element focal plane array in itself, blind element comprises dead pixel and overheated pixel, wherein, dead pixel refers to 1/10 the pixel of pixel responsiveness less than the average response rate, overheated pixel refers to the pixel of pixel noise voltage greater than 10 times of average noise voltages, if therefore these dead pixels and overheated pixel are not removed in the self-adapted digitalization process, the VINA of the analog signal of focal plane array output _Min, VINA _MaxWith being occupied by dead pixel and overheated pixel respectively and not changing, can not really reach the purpose of self-adapted digitalization with the real variations in temperature of scene.According to GB the definition and the scaling method of blind element are demarcated 576 * 6 selected focal plane arrays, rejected these blind element signals.The method of rejecting is: FPGA ignores digitlization output and the OTR signal demarcated to the pixel of blind element when digital signal that detects AD9240 and OTR signal, formula (8) like this, and (9) will be corrected, CODE wherein _Min(CODE _Max) will be interpreted as having removed the digital signal of minimum (maximum) pixel voltage correspondence in the two field picture pixel of blind element respectively.Thus, blind element disturbs and will be removed.

Simultaneously, consider that the temperature peaks peak value in the focal plane array visual field is often to change, if carrying out the numeral that will occur focal plane array probably fully according to the method described above exports at any time all in the self adaptation adjustment, cause focal plane array output image integral body frequently to flash and normally to observe image, at this moment need to set the threshold value that the AD9240 bias voltage is adjusted, promptly be not the bias voltage of just adjusting AD9240 when the temperature peaks peak value is vicissitudinous slightly in the visual field, but when surpassing a certain preset threshold Δ, just adjust.FPGA monitors digitlization output and the OTR signal of AD9240 equally at any time, when first kind of situation (get rid of blind element and disturb back OTR signal for high) when occurring, still carried out according to above-mentioned algorithm, just need be to formula (4), and (5) value is revised again.That is, according to formula (8), (9) calculate VINA _Min, VINA _MaxBe not directly to give formula (4) afterwards, (5) calculate but with formula (4), (5) are modified to following formula:

$\mathrm{VINB}-\mathrm{VREF}=\left\{\begin{array}{cc}{\mathrm{VINA}}_{\min }-\mathrm{\&Delta;}& ({\mathrm{VINA}}_{\min }-\mathrm{\&Delta;}\&GreaterEqual;0)\\ 0& ({\mathrm{VINA}}_{\min }-\mathrm{\&Delta;}<0)\end{array}\right.---\left(10\right)$

$\mathrm{VINB}+\mathrm{VREF}=\left\{\begin{array}{cc}{\mathrm{VINA}}_{\max }+\mathrm{\&Delta;}& ({\mathrm{VINA}}_{\max }+\mathrm{\&Delta;}\&le;5)\\ 5& ({\mathrm{VINA}}_{\max }+\mathrm{\&Delta;}>5)\end{array}\right.---\left(11\right)$

Wherein: Δ is a preset threshold.

Can guarantee like this input range of AD9240 is adjusted to

,

For having got rid of the output area of the focal plane array that blind element disturbs.

And when second kind of situation (get rid of blind element disturb back OTR be 0) when occurring, illustrate that the scope of focal plane array output does not surpass the maximum input range of AD9240, yet need prevent the maximum input range of the scope of focal plane array output equally much smaller than the AD9240 that sets, to this same setting threshold Δ, FPGA monitoring this moment CODE _Min, CODE _Max, and according to formula (8), (9) calculate the minimum signal of current analog signal And peak signal

If

$\mathrm{VINB}-\mathrm{VREF}<{\mathrm{VINA}}_{\min }^{\&prime;}-2\mathrm{\&Delta;}---\left(12\right)$

Perhaps

$\mathrm{VINB}+\mathrm{VREF}>{\mathrm{VINA}}_{\max }^{\&prime;}+2\mathrm{\&Delta;}---\left(13\right)$

Then explanation, $[{\mathrm{VINA}}_{\min }^{\&prime;},{\mathrm{VINA}}_{\max }^{\&prime;}]\&Subset;[{\mathrm{VINA}}_{\min }+\mathrm{\&Delta;},{\mathrm{VINA}}_{\max }-\mathrm{\&Delta;}],$ FPGA resets two bias voltages of AD9240, and the threshold value of consideration needs, promptly, according to formula (8), (9), (10), (11) calculate, otherwise FPGA does not change the input range of the input channel of AD9240, and this had both guaranteed focal plane self-adapted digitalization output within the specific limits, had prevented too frequent the beating of output image simultaneously again.Because the threshold value Δ is different with the difference of scene objects, therefore do not fix it, but manually control by FPGA with a control button, this has guaranteed just that also focal plane array can adapt to different scenes, make it self-adapted digitalization after range of application be not affected.

Claims (3)

1, a kind of infrared focal plane array self-adapted digitalization method may further comprise the steps:

(1) provides the bias condition of focus planardetector need of work when the analog bias voltage signal, digital drive signals provides gain, integration, the synchronous digital signal of focal plane array detector, when the temperature stabilization control system is stablized the temperature of focal plane, the analog signal that focal plane array output changes with the visual field variations in temperature;

(2) this analog signal input A/D device after useless interference signal is eliminated in filtering carries out analog signal digital, the analog input scope of this A/D device is controlled by two bias voltages, promptly this A/D device is imported the FPGA device with the detection signal that overflows of digital signal and A/D device, this FPGA device is controlled series arrangement D/A chip simultaneously, the difference of control signal makes series arrangement D/A chip produce different voltage, this voltage is connected on the bias voltage of A/D device, in order to the analog signal input range of control A/D chip;

Wherein, the course of work of FPGA device is: this FPGA device detects the digital signal of A/D device at any time and overflows detection signal, and to digital signal with overflow detection signal analysis, calculate, with the result of analytical calculation is that the simulation output of focal plane array detector and the input range of A/D device are done contrast, if the simulation output area of focal plane array detector surpasses the input range of A/D device, then by adjusting the input range that digital signal that the FPGA device offers series arrangement D/A chip changes the bias voltage of A/D device and then transfers big A/D device; If the simulation output area of focal plane array detector is less than the input range of A/D device, the digital signal that FPGA then resets series arrangement D/A chip equally changes the bias voltage of A/D device and then to reset the analog signal input range of turning the A/D device down, like this through of at any time monitoring, the analytical calculation of FPGA device to the digitlization output of A/D device, and the revertive control A/D device by series arrangement D/A chip, finish the self-adapted digitalization of focal plane array.

2, infrared focal plane array self-adapted digitalization method according to claim 1, it is characterized in that: when the simulation output area of focal plane array detector surpasses or less than the input range of A/D device, then fpga chip is according to the manual preset threshold Δ in outside, reset the input range of A/D device, guarantee that the maximum of analog signal input range of A/D device of current setting and minimum value are respectively than the big threshold value Δ of maximum m and the little threshold value Δ of minimum value n of the simulation output area of the current focal plane array that calculates, the simulation output area that is current focal plane array is [m, n], then the analog signal input range of A/D device need be made as [m+ Δ, n-Δ]; The analog signal input range adjustment of this A/D device is to change by the digital signal that the FPGA device offers series arrangement D/A chip to finish.

3, a kind of circuit of realizing the described infrared focal plane array self-adapted digitalization method of claim 1, be included in and add digital drive signals, focal plane array detector under analog bias voltage signal and the temperature stabilization control system signal controlling, this focal plane array detector, the analog signal filter, the A/D chip is connected successively with the on-site programmable gate array FPGA chip, the digital signal output interface is set on this fpga chip, it is characterized in that: fpga chip connects a series arrangement D/A chip, this series arrangement D/A chip is connected with the A/D chip, and promptly the serial digital signal of this fpga chip output makes series arrangement D/A chip produce the analog signal input range that two bias voltages are adjusted the A/D chip.