CN100547779C - 用于半导体和电子子系统封装的芯片载体衬底和印刷电路板上的硬波图案设计 - Google Patents

用于半导体和电子子系统封装的芯片载体衬底和印刷电路板上的硬波图案设计 Download PDF

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CN100547779C
CN100547779C CNB2006800119781A CN200680011978A CN100547779C CN 100547779 C CN100547779 C CN 100547779C CN B2006800119781 A CNB2006800119781 A CN B2006800119781A CN 200680011978 A CN200680011978 A CN 200680011978A CN 100547779 C CN100547779 C CN 100547779C
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pattern
substrate
etching
contact finger
hard ripple
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CN101238576A (zh
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肯·简明·王
赫姆·塔基阿尔
奇门·余
邱锦泰
廖智清
陈汉孝
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SanDisk Technologies LLC
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SanDisk Corp
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Abstract

在半导体小片封装中衬底的第一侧上形成硬波图案。所述硬波图案与形成在所述衬底的第二侧上的接触指对准并覆在其上面。当在模制过程期间包装所述衬底和小片时，所述硬波图案有效地减少所述小片的变形和所述小片上的应力，因此实质上减轻小片断裂。

Description

用于半导体和电子子系统封装的芯片载体衬底和印刷电路板上的硬波图案设计
技术领域
本发明的实施例涉及形成芯片载体衬底以减轻芯片断裂的方法，以及借此形成的芯片载体。
背景技术
对便携式消费电子设备的需求的迅猛增长驱动了对高容量存储装置的需要。例如快闪存储卡的非易失性半导体存储器装置正变得广泛用于满足对数字信息存储和交换的不断增长的需求。由于此种存储器装置的便携性、通用性和坚固的设计连同其高度可靠性和大容量，使得此种存储器装置理想地用于各种电子装置，其中包含(例如)数码相机、数字音乐播放器、视频游戏控制台、PDA和蜂窝式电话。
虽然已知各种封装配置，但快闪存储卡一般可制造为封装系统(SiP)或多芯片模块(MCM)，其中多个小片安装在衬底上。所述衬底一般可包含坚硬的基底，所述基底的一侧或两侧上蚀刻有传导层。在小片与传导层之间形成电连接，且传导层提供电引线结构以便将小片集成到电子系统中。一旦在小片与衬底之间作出电连接，随后通常在模制化合物中包装所述组合件以提供保护性封装。
鉴于小形状因数要求以及快闪存储卡需要可移除且不永久地附接到印刷电路板的事实，此种卡通常由接触式栅格阵列(land grid array，LGA)封装构建。在LGA封装中，半导体小片电连接到形成在封装下表面上的暴露的接触指。通过使接触指与印刷电路板上的互补电衬垫压力接触，而实现与主机印刷电路板上的其它电子组件的外部电连接。LGA封装对于快闪存储卡是理想的，因为其与引脚栅格阵列(pin grid array，PGA)和球状栅格阵列(ball grid array，BGA)封装相比具有较小的轮廓和较低的电感。
图1中展示常规LGA封装的横截面。一个或一个以上小片20经由小片附接件24安装在衬底22上。衬底22一般由硬核26形成，例如由聚酰亚胺叠层形成。可使用已知的光刻和蚀刻过程以理想的电引线图案将薄膜铜层28形成在所述核心上，其中所述电引线图案包含用于接触指的暴露表面。接触指30可由沉积在铜层28上的金层形成，以提供所述封装与主机PCB的电连接。小片可经由线接合32电连接到衬底。穿过衬底形成通孔(未图示)以允许小片穿过衬底电连接到接触指30。接着，可用阻焊层34涂覆所述衬底并使得接触指30保持为暴露，以便隔离和保护形成在衬底上的电引线图案。第4,684,184号、第5,199,889号和第5,232,372号美国专利中揭示了典型LGA封装的进一步实例，所述专利的全文以引用的形式并入本文中。
现在参看图2，当在衬底上形成小片之后，将组合件封装在模制化合物40内以保护组合件。在模制过程期间，模制机可输出通常为约0.8吨的注射力以将模制化合物驱动到模腔中。对于占据面积为约4.5mm乘2.5mm的小片，这个注射力可导致对小片的约1.2kgf/mm2的向下压力。
LGA封装的底表面通常是不平坦的。如图1和图2所示，指状物30凹入在封装内，在阻焊层34所界定的平面上方。阻焊层的齐平位置导致在下表面阻焊层下方的位置处，在衬底上存在抵着模制化合物的力向上推的相等且相对的力。然而，由于接触指不与阻焊层的下表面齐平，所以在接触指下方的位置处没有相等且相对的力。这导致在小片内部在位于接触指上的小片中的位置处积累应力。
过去，在LGA封装中，半导体小片更能够承受模制过程期间产生的应力。然而，芯片规模的封装(CSP)和始终朝着较小形状因数封装的驱动力需要小片非常薄。目前已知在半导体制造过程期间采用晶片背面研磨使小片变薄到约8密耳到20密耳的范围。在这些厚度下，小片通常无法承受模制过程期间产生的应力，且小片会在模制压力下变形(如图2中的虚线所示)。
小片在接触指上的变形可导致小片折断(称为小片断裂)，例如图2所示的小片断裂50。在模制过程的应力下发生的小片断裂一般将导致必须丢弃封装。这个问题发生在半导体制造和封装过程的结尾，因此是一个特别浪费且麻烦的问题。
芯片载体衬底先前并未解决小片断裂的问题。衬底顶侧上位于衬底底侧上的接触指上方的区域一般包含铜层28，其例如被蚀刻成网眼图案如现有技术图3所示。还已知在接触指上方提供固态均匀的铜层，如现有技术图4所示。然而，由于热膨胀系数的差异，在封装成型期间的升温过程期间，衬底上的固态均匀的铜层会导致翘曲及其它问题。此外，通过较薄的半导体小片，在使用图3和图4所示的图案中的任一者的模制过程期间以无法接受的高比率发生小片断裂。
发明内容
本发明的一个实施例涉及一种强化的半导体小片封装。所述半导体小片封装由以下各物形成：安装于衬底上的一个或一个以上半导体小片，以及用于囊封所述一个或一个以上半导体小片和衬底的模制化合物。所述衬底包含第一和第二传导层，其中的一者或两者中形成有电传导图案。传导层中的第一者上的传导图案的一部分形成为接触指，以用于将小片封装电连接到外部组件。第二传导层包含一图案(本文称为硬波图案)，用于减少一个或一个以上小片上原本会在模制过程期间因接触指而导致的变形和应力。
在本发明的实施例中，在衬底的第一表面中形成硬波图案以与形成在衬底的相对表面上的接触指对准并位于其上方。硬波图案可包含蚀刻部分和包围蚀刻部分的未蚀刻部分。对于每个接触指可存在一个蚀刻部分，且每个蚀刻部分具有大约与衬底的相对表面中的其相应的接触指相同的大小。
在本发明的实施例中，蚀刻部分中的每一者均可具有四个不同区段，所述区段一起形成椭圆的一部分，所述椭圆在顶部和底部处被截断，且在其顶部与底部之间的中间处分离。包围蚀刻部分的未蚀刻部分可大体上为矩形形状且不受蚀刻。硬波图案的蚀刻和未蚀刻部分的形状可在替代实施例中变化。
通过一个或一个以上小片在安装于衬底上时位于一些或全部接触指上方，根据本发明实施例的硬波图案有效地减少个别小片上的变形和应力，因此实质上减轻小片断裂。此外，可在衬底上在与导电图案相同的时间且在相同的过程中形成硬波图案的蚀刻部分。因此，可无需任何额外的处理步骤或任何额外的制造成本而实现本发明提供的优点。
附图说明
图1是在LGA封装中安装在衬底上的小片的现有技术横截面图。
图2是封装的小片和衬底的现有技术横截面图，其中小片已在模制过程期间因压力而断裂。
图3是形成在常规芯片载体衬底的上表面上的未蚀刻铜层的现有技术俯视图。
图4是形成在常规芯片载体衬底的上表面上的网眼图案铜层的现有技术俯视图。
图5是芯片载体衬底的俯视图，穿过顶表面看到底表面上的接触指(用虚影展示底表面上的接触指)。
图6是芯片载体衬底的俯视图，所述顶表面包含根据本发明实施例的硬波图案。
图7是穿过图6中的线7-7的横截面图。
图8是穿过图6中的线8-8的横截面图。
图9是根据本发明实施例的硬波图案的一部分的放大俯视图。
图10-13是芯片载体衬底的俯视图，所述顶表面包含根据本发明替代实施例的硬波图案。
图14是芯片载体衬底的一部分的放大俯视图，所述顶表面包含图13所示的硬波图案。
图15是芯片载体衬底的俯视图，所述顶表面包含根据本发明实施例的传导图案和硬波图案。
图16是根据本发明实施例包含小片和具有硬波图案的芯片载体衬底的半导体封装的横截面侧视图。
图17是根据本发明在衬底上形成硬波图案的过程的流程图。
图18是说明根据本发明的芯片载体衬底的制造过程的流程图。
具体实施方式
现在将参看图5到图18描述本发明的实施例，所述图涉及强化的半导体封装。应了解，可用许多不同形式实施本发明，且不应理解为限制于本文阐述的实施例。而是提供这些实施例以使得本揭示内容将是彻底和全面的，且将把本发明完全传达给所属领域的技术人员。实际上，本发明意欲涵盖这些实施例的替代、修改和均等物，其包含在所附权利要求书所界定的本发明的范围和精神内。此外，在以下对本发明的详细描述中陈述了许多具体细节，以便提供对本发明的透彻理解。然而，所属领域的普通技术人员将明白，可在没有这类具体细节的情况下实践本发明。
图5和图6是芯片载体衬底100的一部分的俯视图，且图7和图8是穿过垂直于衬底100的顶表面和底表面的不同平面的横截面图。如图7和图8中所看到，衬底100可具有顶表面102和底表面104。衬底100可由核心106形成，并具有形成在核心顶表面上的顶部传导层108和形成在核心底表面上的底部传导层110。核心可为介电材料，例如环氧玻璃树脂(如BT树脂)且可具有约40微米(μm)到200μm的厚度，但在替代实施例中，核心的厚度可在所述范围之外变化。在替代实施例中，核心可为陶瓷或有机的。
传导层108和110可由铜或其它低电阻电导体形成，且可如下文阐释经图案化。层108和110可具有约10μm到24μm的厚度，但是在替代实施例中，层108和110的厚度可在所述范围之外变化。一旦经图案化，顶部和底部传导层便可如此项技术中已知的与阻焊层112叠层，且可如此项技术中已知的在底部传导层110的多个部分上形成一个或一个以上金层来界定接触指114。可从Kinsus Interconnect Technology Corp.，Santa Clara，CA购得包含可根据本发明进行图案化的传导层的衬底。
在本发明的实施例中，衬底100可经图案化和配置以用于LGA半导体封装。应了解，下文解释的衬底100和硬波图案可用于其它类型的半导体封装，其中包含(例如)BGA封装。
图5、7和8进一步展示安装在衬底100的顶表面102上的两个堆叠的半导体小片116(在图5的俯视图中以虚影展示，且为清晰起见在图6的俯视图中省略)。本发明的实施例可替代地包含单个小片，且本发明的实施例可替代地包含3个与8个之间或更多的以SiP、MCM或其它类型的布置堆叠的小片。一个或一个以上小片可具有范围在8密耳到20密耳之间的厚度，但在替代实施例中，一个或一个以上小片可比8密耳薄和比20密耳厚。虽然对于本发明并不非关键，但一个或一个以上小片116可为快闪存储器芯片(NOR/NAND)、SRAM或DDT和/或例如ASIC等控制器芯片。还涵盖其它硅芯片。
可使用已知的小片附接化合物118在已知的粘合或易熔小片接合工艺中将一个或一个以上小片116安装在衬底100的顶表面102上。举例来说，小片附接化合物可为例如含有传导填料以进行导电的各种聚合体粘合剂中的任一者。举例来说，此种小片附接化合物由Semiconductor Packaging Materials，Inc.of Armonk，N.Y制造。一个或一个以上小片116可在已知的线接合工艺中通过线接合120电连接到衬底100的传导层108、110。
虽然从芯片载体衬底的顶表面无法看到，但图5以虚影展示形成在衬底100的底表面104上的接触指114的位置的俯视图。提供接触指114以在使接触指114抵着主机印刷电路板的接触垫压力接触时，建立以已知方式与主机印刷电路板(未图示)或另一电子组件的接触垫的电连接。虽然展示了四个接触指114，但应了解，在芯片载体衬底100的替代配置中可存在多于或少于四个指状物。在实施例中，可能存在八个接触指。
可以已知方式且如下文阐释在衬底的上和/或下表面102、104上形成导电图案的其它部分，以在一个或一个以上小片116、接触指114和/或其它安装在衬底100表面上的电子组件之间建立电连接。在实施例中，除了硬波图案和接触指之外，在衬底100的一个或两个表面上可存在导电图案208(图15)。在顶表面102和底表面104两者上均包含传导图案的实施例中，可提供通孔(未图示)以在衬底100的顶表面与底表面之间传输电信号。
如背景技术部分中所指示，对于较薄的小片，在模制过程期间施加的压力通常以机械方式将小片压到发生小片断裂的点上。为了防止在模制过程期间发生小片断裂，本发明在衬底上采用蚀刻图案，其在本文被称为硬波图案或“RWP”。在图6中的衬底100的顶表面102的视图中展示硬波图案130的实施例。在本发明的实施例中，在顶表面102上形成硬波图案130，以便与形成在衬底100的相对表面上的接触指114对准并位于其上方。硬波图案130包含蚀刻部分132-138和包围蚀刻部分132-138的未蚀刻部分140。在所展示的衬底100的配置中存在四个接触指114，且相应地，硬波图案130具有四个相应的RWP蚀刻部分，一个RWP蚀刻部分对应于一个接触指。在存在或多或少的接触指的配置中，本发明的实施例相应地包含或多或少的RWP蚀刻部分。在包含八个接触指的实施例中，可能存在八个相应的RWP蚀刻部分。然而，应了解，在本发明的替代实施例中，可能存在比接触指多或少的RWP蚀刻部分。
可在上表面102上在与导电图案208相同的时间且在相同的过程中形成硬波图案130的RWP蚀刻部分。因此，可在没有任何额外处理步骤或任何额外制造成本的情况下实现本发明提供的优点。然而应了解，在替代实施例中，硬波图案可由已知的电镀材料形成为层108和/或110中的一者上的单独层。存在许多用于形成RWP蚀刻部分的已知过程。参看图14的流程图解释用于在衬底100上形成RWP蚀刻部分以及导电图案208的一个过程。在步骤150中清洗传导层108和110的表面。接着，在步骤152中在层108和110的表面上施加光阻膜。接着，在步骤154中在光阻膜上放置含有导电图案和硬波图案的轮廓的图案掩膜。暴露(步骤156)和显影(步骤158)光阻膜以从传导层上待蚀刻的区域中移除光阻。接下来，在步骤160中使用例如氯化铁等蚀刻剂蚀刻掉暴露区域，以在核心上界定传导和硬波图案。接下来，在步骤162中移除光阻，并在步骤164中施加阻焊层。
在本发明的实施例中，RWP蚀刻部分132-138中每一者的总宽度大约等于每个接触指114的宽度，且总长度大约等于每个接触指114的长度。每个RWP蚀刻部分132-138包含四个不同部分，所述部分一起形成椭圆的一部分，其中所述椭圆在顶部和底部处被截断，并且在其顶部与底部之间的中间处分离。假设平行于接触指的长度的长度L(图9)，RWP蚀刻部分的四个不同部分中每一者的长度L可大约为接触指的长度的三分之一。
RWP蚀刻部分的每个部分的宽度W可为约50μm。应了解，在替代实施例中，长度L和宽度W可为小于或大于上文陈述的值的值。
图9是单个RWP蚀刻部分(例如RWP蚀刻部分132)的放大视图。在实施例中，
RWP蚀刻部分132-138中每一者可具有彼此相同的大小和配置，但应了解，在替代实施例中，RWP蚀刻部分132-138的大小可彼此不同。图9展示RWP蚀刻部分132和两个虚影的矩形。较小的矩形(矩形170)是接触指114的大小，RWP蚀刻部分132在其上方位于衬底上，如下文参看图12所阐释。较大的矩形(矩形172)是具有由RWP蚀刻部分132的外边缘界定的椭圆(以虚影展示)的总宽度和长度的矩形(即，如果RWP蚀刻部分132的顶部和底部部分未被截断，则其将形成具有矩形172的宽度和长度的椭圆)。在本发明的实施例中，矩形170和172具有相同宽度。也就是说，RWP蚀刻部分132的宽度与接触指114的宽度相同。在本发明的实施例中，矩形172的大小范围可为从大约与矩形170的大小相同到长度为约4.9mm且宽度约为1.65mm的矩形。应了解，在替代实施例中，矩形172的大小可略大于或小于上述范围。
在本发明的实施例中，围绕RWP蚀刻部分132-138中每一者的RWP未蚀刻部分140大体上具有矩形形状且未被蚀刻。在第一实施例中，由RWP未蚀刻部分140界定的矩形大小可如同恰好将每个RWP蚀刻部分一起包围起来的矩形一样小。在第二实施例中，RWP未蚀刻部分140可在第一方向上延伸到传导层108的左边缘，在第二方向上延伸到传导层108的右边缘，在第三方向上延伸到传导层的邻近RWP蚀刻部分的顶边缘，并在第四方向上向下延伸到恰好形成在衬底100的顶表面102上的电路图案上方的边界。在进一步的替代实施例中，蚀刻部分的大小范围可在上述第一实施例与第二实施例之间的任何位置。在衬底顶表面上没有电路的实施例中，RWP未蚀刻部分可向下延伸到传导层108的底边缘。
应了解，在替代实施例中，RWP未蚀刻部分140的形状可不同于矩形。举例来说，其可为卵形、椭圆形、圆形或某一其它包围RWP蚀刻部分的不规则形状。
也应了解，RWP蚀刻图案可与图6、9和10中所示的部分椭圆形状不同。举例来说，图10展示RWP蚀刻图案174-180具有直的边缘，每个图案174-180的长度和宽度位于接触指114上方且具有与接触指114大约相同的形状。RWP蚀刻图案可替代地大体上具有矩形形状，例如图11所示的RWP蚀刻图案182-188。不蚀刻图11所示的RWP蚀刻图案182-188的中心。应了解，在替代实施例中，可蚀刻RWP蚀刻图案182-188的中心。图12中展示进一步的实施例，其中RWP蚀刻图案190-196中的每一者具有在三角形形状中朝彼此倾斜的顶部和底部长度。倾斜的长度可在其顶部和底部处集中在一起，或者可彼此分离(如图所示)。图13和图14的放大视图中展示又进一步的实施例。RWP蚀刻图案198-204展示为包含在RWP蚀刻图案的长度方向的部分之间延伸的横向散热蚀刻206。在实施例中可使用散热蚀刻来减少由于层108与核心106的不同热膨胀系数产生的衬底的层内的机械应力。横跨RWP蚀刻图案长度的散热蚀刻206的数目和宽度可在替代实施例中变化。散热蚀刻206可用于上述实施例中的任一者。应了解，在替代实施例中，RWP蚀刻图案可具有其它形状。
图15是包含根据本发明实施例的传导图案208和硬波图案130的芯片载体衬底100的俯视图。位于衬底100底表面上的接触指114也用虚影展示。如图所示，RWP蚀刻部分中的每一者与各自的接触指114对准并驻留在其上。应了解，接触指114可形成在衬底上的其它位置处，且硬波图案相应地移动以位于指状物上方。
通过一个或一个以上小片在安装于衬底上时位于一些或全部接触指上方，根据本发明实施例的硬波图案有效地减少个别小片上的变形和应力，因此实质上减轻小片断裂。
此外，虽然根据本发明实施例的硬波图案描述为位于衬底的相对侧上的接触指上，以减少至少部分安装于接触指和硬波图案上的半导体小片上的机械应力，但应了解，可在传导图案的其它部分上使用硬波图案，以减少衬底100上的其它组件上的机械应力。在此种实施例中，可在传导图案的一部分的相对侧上，以与上述传导图案的所述部分对准且与其互补的形状形成硬波图案，以便经由硬波图案和传导图案的所述部分减少安装于衬底上的组件上的机械应力。
图16是完成的半导体小片封装210的横截面侧视图，其中具有硬波图案的衬底100和小片116被包装在模制化合物212内。参看图18的流程图阐释用于形成完成的小片封装210的过程。衬底100作为较大面板开始，其在制造之后被分成个别衬底，在步骤220中，将所述面板钻孔以提供参考孔，通过所述参考孔界定个别衬底的位置。接着，如上文所阐释，在步骤222中在面板的个别表面上形成传导图案和硬波图案。接着，在步骤224中在自动光学检查(AOI)中检查经图案化的面板。一旦经过检查，便在步骤226中向面板施加阻焊层。
在施加了阻焊层之后，完成接触指。在步骤228中，例如通过薄膜沉积在衬底底表面上的传导层的某些暴露表面上施加软金层。由于接触指因与外部电连接接触而将经受磨损，所以可在步骤230中例如通过电镀施加硬金层。应了解，在替代实施例中可施加单个金层。接着，在步骤232中，用刳刨机将面板分成个别衬底。接着，在自动化步骤(步骤234)和最终视觉检查(步骤236)中检查和测试个别衬底以检验电操作，并检验污染、刮擦和变色。接着，在步骤238中将通过检查的衬底发送通过小片附接过程，并接着在步骤240中在已知的注射模制过程中封装衬底和小片，以形成JEDEC标准(或其它标准)的封装。应了解，在替代实施例中，可通过其它过程形成包含硬波图案的小片封装210。
已为了说明和描述目的而提供了以上对本发明的详细描述。其并不期望是详尽的或将本发明局限于所揭示的精确形式。按照以上教示，许多修改和更改都是可以的。选择所描述的实施例以便最佳地解释本发明的原理及其实践应用，借此使所属领域的技术人员能够在各种实施例中且使用适合所预期的特定用途的各种修改来最佳地利用本发明。希望本发明的范围由随附权利要求书界定。

Claims (12)

1.一种在衬底的第一表面上形成电连接器的第一图案，所述衬底能够支撑半导体小片并电连接到所述半导体小片，所述衬底的第二表面与所述第一表面相对且包含第二图案，所述第一图案包括：
蚀刻部分；
围绕所述蚀刻部分的未蚀刻部分，所述第一图案用以减少在模制过程期间由所述第二图案在所述半导体小片上产生的机械应力；
其中位于所述衬底的所述第一表面上的所述第一图案的蚀刻部分与所述第二图案的一部分对准并覆在其上面；
其中所述第二图案的所述部分是用于形成外部电连接的接触指；以及
其中所述第一图案的所述蚀刻部分形成椭圆的一部分，所述椭圆的宽度等于所述接触指的宽度，且所述椭圆的长度大于或等于所述接触指的长度。
2.根据权利要求1所述的第一图案，其中所述椭圆的所述部分的宽度等于所述接触指的宽度，且所述椭圆的所述部分的长度等于所述接触指的长度。
3.一种在衬底的第一表面上形成电连接器的第一图案，所述衬底能够支撑半导体小片并电连接到所述半导体小片，所述衬底的第二表面与所述第一表面相对且包含第二图案，所述第一图案包括：
蚀刻部分；
围绕所述蚀刻部分的未蚀刻部分，所述第一图案用以减少在模制过程期间由所述第二图案在所述半导体小片上产生的机械应力；
其中位于所述衬底的所述第一表面上的所述第一图案的蚀刻部分与所述第二图案的一部分对准并覆在其上面；
其中所述第二图案的所述部分是用于形成外部电连接的接触指；以及
其中所述第一图案的所述蚀刻部分包含沿着所述蚀刻部分的长度对准的一对蚀刻区段，以及在所述对蚀刻区段之间横向延伸的横向蚀刻区段。
4.一种形成在衬底的第一表面中的硬波图案，所述衬底能够支撑半导体小片并电连接到所述半导体小片，所述衬底的第二表面与所述第一表面相对且包含一个或一个以上接触指以用于形成一个或一个以上外部电连接，所述硬波图案包括：
位于所述第一表面上的一个或一个以上蚀刻部分，所述一个或一个以上蚀刻部分中的一蚀刻部分形成覆在所述第二表面上的一个或一个以上接触指中的一接触指上面的椭圆的部分，所述椭圆的宽度等于所述接触指的宽度，且所述椭圆的长度大于或等于所述接触指的长度；以及
围绕所述一个或一个以上蚀刻部分的未蚀刻部分，所述硬波图案能够减少在模制过程期间由所述接触指在所述半导体小片上产生的机械应力。
5.根据权利要求4所述的硬波图案，所述衬底包含：
核心，其具有第一表面和与所述第一表面相对的第二表面；
第一传导层，其形成在所述核心的所述第一表面上，所述第一图案形成在所述第一传导层中；以及
第二传导层，其形成在所述核心的所述第二表面上，所述一个或一个以上接触指形成在所述第二传导层中。
6.根据权利要求4所述的硬波图案，其中所述硬波图案形成在所述衬底的铜层中。
7.根据权利要求4所述的硬波图案，其中所述硬波图案的所述未蚀刻部分具有矩形形状。
8.一种形成在衬底的第一表面中的硬波图案，所述衬底能够支撑半导体小片并电连接到所述半导体小片，所述衬底的第二表面与所述第一表面相对且包含一个或一个以上接触指以用于形成一个或一个以上外部电连接，所述硬波图案包括：
位于所述第一表面上的一个或一个以上蚀刻部分，所述一个或一个以上蚀刻部分中的一蚀刻部分形成覆在所述第二表面上的一个或一个以上接触指中的一接触指上面的椭圆的部分，所述椭圆的宽度等于所述接触指的宽度，且所述椭圆的长度大于或等于所述接触指的长度；以及
围绕所述一个或一个以上蚀刻部分的未蚀刻部分，所述硬波图案能够减少在模制过程期间由所述接触指在所述半导体小片上产生的机械应力；
所述椭圆的所述部分的宽度等于所述接触指的宽度，且所述椭圆的所述部分的长度等于所述接触指的长度。
9.一种形成在衬底的第一表面中的硬波图案，所述衬底能够支撑半导体小片并电连接到所述半导体小片，所述衬底的第二表面与所述第一表面相对且包含一个或一个以上接触指以用于形成一个或一个以上外部电连接，所述硬波图案包括：
位于所述第一表面上的一个或一个以上蚀刻部分，所述一个或一个以上蚀刻部分中的一蚀刻部分包含沿着所述蚀刻部分的长度对准的一对蚀刻区段，以及在所述对蚀刻区段之间横向延伸的横向蚀刻区段，且覆在所述第二表面上的所述一个或一个以上接触指中的一接触指上面；以及
围绕所述一个或一个以上蚀刻部分的未蚀刻部分，所述硬波图案能够减少在模制过程期间由所述接触指在所述半导体小片上产生的机械应力。
10.根据权利要求9所述的硬波图案，所述衬底包含：
核心，其具有第一表面和与所述第一表面相对的第二表面；
第一传导层，其形成在所述核心的所述第一表面上，所述第一图案形成在所述第一传导层中；以及
第二传导层，其形成在所述核心的所述第二表面上，所述一个或一个以上接触指形成在所述第二传导层中。
11.根据权利要求9所述的硬波图案，其中所述硬波图案形成在所述衬底的铜层中。
12.根据权利要求9所述的硬波图案，其中所述硬波图案的所述未蚀刻部分具有矩形形状。
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EP1869704A1 (en) 2007-12-26
JP2008537336A (ja) 2008-09-11
US8878368B2 (en) 2014-11-04
KR100934269B1 (ko) 2009-12-28
US20150054177A1 (en) 2015-02-26
US20060231943A1 (en) 2006-10-19
US20080054445A1 (en) 2008-03-06
TW200644206A (en) 2006-12-16
US7355283B2 (en) 2008-04-08
US8487441B2 (en) 2013-07-16
US20130299959A1 (en) 2013-11-14
KR20080024463A (ko) 2008-03-18
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US9230919B2 (en) 2016-01-05

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