CN100559506C - Flash memory section and method for erasing flash memory cluster - Google Patents
Flash memory section and method for erasing flash memory cluster Download PDFInfo
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- CN100559506C CN100559506C CNB200610103931XA CN200610103931A CN100559506C CN 100559506 C CN100559506 C CN 100559506C CN B200610103931X A CNB200610103931X A CN B200610103931XA CN 200610103931 A CN200610103931 A CN 200610103931A CN 100559506 C CN100559506 C CN 100559506C
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Abstract
A kind of method for erasing flash memory cluster comprises the following steps: that (a) applies erase pulses to first subclass of a flash memory cluster.(b) above-mentioned first subclass is carried out soft sequencing affirmation or strict soft sequencing affirmation.(c) repeating step (a) with (b) up to first pre-conditioned be true.(d) second subclass of above-mentioned memory cluster is carried out the affirmation of erasing.(e) repeating step (a) to (d) up to second pre-conditioned be true.At last, (f) mode of using slow sequencing and applying erase pulses is repaired the bit line leakage phenomenon that the three subsetss of above-mentioned memory cluster close.
Description
Technical field
The invention relates to fast flash memory bank, and particularly about a kind of flash memory section erasing method and a kind of method for erasing flash memory cluster (METHOD FOR ERASING A FLASH MEMORY SECTORAND METHOD FOR ERASING A FLASH MEMORY GROUP).
Background technology
When erasing (erase) fast-flash memory body unit (flash memory cell) each time, always might reduce the critical voltage (threshold voltage) of this mnemon.What is called excessively erase (over-erase) be meant the situation that bit line leakage current (bit lineleakage) takes place in the fast-flash memory body unit.If the mnemon of excessively having erased is accepted once to erase again, deep layer excessively erase (deep over-erase) may take place.Can't repair because deep layer is excessively erased, should avoid as far as possible.
Fig. 1 is the process flow diagram of traditional flash memory cluster (flash memory group) erasing method.Flash memory cluster is the set that a plurality of flash memory sections (flash memory sector) are formed.In step 110, a memory cluster is applied erase pulses (ERS pulse, just erase pulse) all memory districts with this memory cluster of erasing simultaneously.In step 120 this memory cluster is carried out the affirmation (ERSV:erase verification) of erasing then.If all mnemons are all by the affirmation of erasing, the flow process of Fig. 1 so far finishes.Otherwise flow process can be got back to step 110, and this memory cluster is applied erase pulses again one time.Step 110 to 120 loop can repeat to all mnemons all by till the affirmation of erasing.
Above-mentioned erase to be confirmed to be each address is carried out one by one, therefore need address counters (address counter) to write down present affirmation address.Fig. 2 is fast flash memory bank wafer address counter 201 wherein and the synoptic diagram of memory district 211-214.The memory cluster of Fig. 2 uses the erasing method of Fig. 1.Suppose to erase and confirm from remembering first address in district 211.The problem of classic method is that as long as there is any one mnemon to fail by the affirmation of erasing, whole memory cluster all will be accepted erase pulses again, then must carry out the affirmation of erasing for a time again from first address.The result is exactly, and the mnemon that is positioned at high address end may be erased too many time and be caused deep layer excessively to erase.In the example of Fig. 2, memory district 214 most probable generation deep layers are excessively erased.
The solution of the problems referred to above is for each memory district arranges an address counter, as shown in Figure 3.The fast flash memory bank wafer of Fig. 3 has four memory district 311-314 and four corresponding address counter 301-304.Each address counter 301-304 stores the affirmation address of corresponding memory district 311-314.In Fig. 3,, just need not be erased again if there is the memory district to be erased the back by the affirmation of erasing.This method can reduce the risk that deep layer is excessively erased.Yet owing to need extra address counter, the fast flash memory bank wafer of Fig. 3 can take the area bigger than the wafer of Fig. 2.
Another avoids method that deep layer excessively erases as shown in Figure 4.Fig. 4 is the process flow diagram of another traditional flash memory cluster erasing method.At first apply erase pulses at step 410 pair memory cluster.Carry out soft sequencing at step 420 pair memory cluster then and confirm whether (SPGMV:soft programverification) has bit line leakage current to check.If there is the memory district to fail to confirm by the soft sequencing of step 420, represent that there is bit line leakage current in this memory district, must carry out soft sequencing (SPGM:soft program) to repair leakage phenomenon to this memory district in step 430.Memory district through soft sequencing can confirm once in step 420 again.Step 420 and 430 loop can repeat to this memory district always repair fully till.After all memory districts all pass through the soft sequencing affirmation of step 420, carry out the affirmation (ERSV) of erasing at step 440 pair whole memory cluster.If this memory cluster is by the above-mentioned affirmation of erasing, flow process so far finishes.Otherwise flow process can be got back to step 410 memory cluster of erasing again a time.This method can be repaired earlier before applying the erase pulses of another time the memory district of leakage current, so can avoid deep layer excessively to erase.Yet may all leak electricity each time in some memory district, all need each time to repair.This situation can be wasted a lot of times.
Summary of the invention
The objective of the invention is is providing a kind of flash memory section erasing method, is applicable to the uneven memory district of erasing, and can avoids deep layer excessively to erase.So-called inhomogeneous memory district is exactly the memory district that leakage current occurs and fail to confirm by erasing after erasing.This method is quicker than classic method, and its main cause is all to carry out the affirmation of once erasing after applying erase pulses each time.This method second reason fast is the conservative program of erasing that this method is used, its step comprises bit line that slow sequencing (SLPGM:slow program) and slow sequencing affirmation (SLPGMV:slow programverification) are leaked electricity with reparation, and the execution frequency of above-mentioned two steps is far below the corresponding step in the classic method.
Another object of the present invention provides a kind of method for erasing flash memory cluster, can avoid deep layer excessively to erase, the fast classic method of crossing of speed, and because only with an address counter, so more save chip area than classic method.This method be applicable to memory cluster erase and remember the district erase.Because only need handle part memory district, the time that this method is carried out soft sequencing after also can saving and erasing in the soft sequencing stage.In addition, this method is divided into a plurality of kinds with fast-flash memory, and each uses different programs to be handled.
For reaching above-mentioned and other purpose, the present invention proposes a kind of flash memory section erasing method, it is characterized in that comprising the following steps: that (a) carries out soft sequencing affirmation at least one memory district of fast flash memory bank.(b) wherein as if above-mentioned at least one memory district, there is the memory district to fail to confirm by soft sequencing, then (b1) carries out slow sequencing to this memory district, (b2) this memory district being carried out slow sequencing confirms, (b3) if this memory district fail to confirm by slow sequencing, then once again execution in step (b1) to (b3).(c) above-mentioned at least one memory district is carried out the affirmation of erasing, and, then this memory district is applied erase pulses, get back to step (a) then (d) if above-mentioned at least one memory district wherein, has the memory district to fail by the affirmation of erasing.
From another viewpoint, the present invention proposes a kind of method for erasing flash memory cluster in addition, comprises the following steps.(a) first subclass to a flash memory cluster applies first erase pulses.(b) this first subclass being carried out the first soft sequencing confirms or strict soft sequencing affirmation (TSPGMV:tight softprogram verification).(c) repeating step (a) with (b) up to first pre-conditioned be true.(d) second subclass of this memory cluster is carried out first affirmation of erasing.(e) repeating step (a) to (d) up to second pre-conditioned be true.(f) three subsetss to this memory cluster close the execution second soft sequencing affirmation.(g) a memory district fails to confirm by the second soft sequencing if these three subsetss close wherein, then (g1) carries out slow sequencing to this memory district, (g2) this memory district being carried out slow sequencing confirms, (g3) if this memory district fail to confirm by slow sequencing, then once again execution in step (g1) to (g3).(h) these three subsetss are closed carry out second affirmation of erasing, and (i) if these three subsetss close wherein a memory district fails by second affirmation of erasing, then this is remembered to distinguish and apply second erase pulses, get back to step (f) then.
Above-mentioned method for erasing flash memory cluster is the different conditions of distinguishing the memory district with banner A, B, C in one embodiment.Banner A fails by the first soft sequencing is confirmed or strict soft sequencing is confirmed memory district in order to sign, banner B is the memory district of erasing and confirming by first in order to indicate, and banner C is in order to indicate existing banner A and to fail the memory district of erasing and confirming by first.In this embodiment, the first above-mentioned subclass is no banner A and do not have all memory districts of banner B in the memory cluster for this reason, second subclass is no banner B and do not have all memory districts of banner C in the memory cluster for this reason, and three subsetss are combined into all memory districts that this memory cluster acceptance of the bid is shown with banner C.
Aforesaid method for erasing flash memory cluster has two kinds of main variations.In first kind of variation, what step (b) was carried out is that the first soft sequencing is confirmed.Step (b) more comprises if first subclass wherein has the memory district to fail to confirm by the first soft sequencing in addition, then indicates this memory district with banner A.And above-mentioned first is pre-conditioned for having applied first erase pulses of a preset times, or each memory district of this memory cluster has indicated banner A or banner B all.
In second kind of variation of this method, step (b) uses default initial word group line voltage (wordline voltage) to carry out strict soft sequencing affirmation.Step (b) more comprises if first subclass wherein has memory district to fail to confirm by the soft sequencing of strictness in addition, and strict soft sequencing then indicates this memory district with banner A when confirming that employed word group line voltage is 0V.And step (d) comprises that more then strict soft sequencing that this memory is distinguished confirms that employed word group line voltage reduces by a preset value if second subclass wherein has memory district to fail by first affirmation of erasing.
In addition, in one embodiment of the invention, above-mentioned first pre-conditioned be that first subclass wherein has the memory district to fail to confirm by the soft sequencing of strictness.
In another embodiment of the present invention, above-mentioned first pre-conditioned be that first subclass wherein has the memory district to fail to confirm by the soft sequencing of strictness, or the first above-mentioned erase pulses has been applied in a preset times.
In one embodiment of the invention, a common ground of above-mentioned two kinds of variations is that step (d) more comprises: if second subclass wherein has memory district by first affirmation of erasing, then indicate this memory with banner B and distinguish; And, fail then to indicate this memory and distinguish if indicate arbitrary memory district that banner A is arranged with banner C by first affirmation of erasing.
In same embodiment, another common ground of above-mentioned two kinds of variations is that each memory district of the second pre-conditioned memory cluster has for this reason all indicated banner B or banner C.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment of the present invention cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is the process flow diagram of traditional flash memory cluster erasing method.
Fig. 2 is the address counter of a fast flash memory bank wafer and the synoptic diagram in memory district.
Fig. 3 is the address counter of a traditional flash memory chip and the synoptic diagram in memory district.
Fig. 4 is the process flow diagram of another traditional flash memory cluster erasing method.
Fig. 5 is the method for erasing flash memory cluster process flow diagram that is pursuant to one embodiment of the invention.
Fig. 6 is the conservative program flow diagram of erasing that is pursuant to one embodiment of the invention.
Fig. 7 is the another kind of method for erasing flash memory cluster process flow diagram that is pursuant to one embodiment of the invention.
110-120: flow chart step
201,301-304: address counter
211-214,311-314: flash memory section
410-440,510-570,610-650,730-750: flow chart step
Embodiment
As described below, preferred embodiment use banner of the present invention indicates the memory district of bit line leakage current, and the memory district by erasing and confirming.Therefore following embodiment can avoid deep layer excessively to erase, and by omitting unnecessary and often harmful erase pulses to improve efficient.Another factor that improves efficient of the present invention is that following embodiment uses than the soft faster sequencing affirmation of the affirmation of erasing, to reduce the not good frequency of utilization of erasing and confirming of efficient.
Fig. 5 is the method for erasing flash memory cluster process flow diagram that is pursuant to one embodiment of the invention.Flow process is from step 510.At first, this memory cluster is carried out the affirmation (ERSV) of erasing.If whole memory cluster is all by the affirmation of erasing, flow process so far finishes.Otherwise flow process enters step 520, and all memory districts that do not indicate banner A in the middle of this memory cluster and do not indicate banner B are applied erase pulses.In the present embodiment, banner A is the memory district that is used for indicating electric leakage.Banner B is used for indicating erasing, and the memory district by erasing and confirming.Also has banner C in addition, in order to indicate inhomogeneous memory district.So-called inhomogeneous memory district is meant the electric leakage of bit line takes place, and still fails the memory district that confirms by erasing.The memory district that has indicated banner A or B can skips steps 520, because the memory district of having leaked electricity should do not erased again, and does not need to accept to erase by the memory district that confirms of erasing again.The memory district that sign has a banner C also can skips steps 520, because shown in the step of back, indicates the inevitable banner A that indicate in the memory district that banner C is arranged.
Follow in step 530, in the middle of memory cluster, indicate banner A to be arranged and indicate the soft sequencing of all memory district execution that banner B is arranged and confirm (SPGMV).If have the memory district to fail to confirm, just indicate this memory district with banner A by the soft sequencing of step 530.Above-mentioned soft sequencing is confirmed to be to be used in and applies after the erase pulses, checks the memory district whether electric leakage is arranged.Owing to indicate memory district skips steps 520 all that banner A or B are arranged, there is the memory district of banner A or B also can skips steps 530.
Next, step 540 control is by step 520 and 530 loops that constituted.The erase pulses that above-mentioned loop can repeat to step 520 always has been applied in till the preset times, or each the memory district that always repeats in the memory cluster has all indicated till banner A or the B.
Through after the above-mentioned loop, in step 550 pair memory cluster, do not indicate banner B to be arranged and do not indicate the memory district that banner C is arranged and carry out the affirmation (ERSV) of erasing.If the erase affirmation of memory district by step 550 arranged, then indicate this memory district with banner B.In addition, if having memory district to indicate banner A and fail affirmations of erasing by step 550, then indicate this memory and distinguish with banner C.Before this, there has been the memory district of banner B can skips steps 550, because they are by the last time affirmation of erasing.The memory district that has indicated banner C also can skips steps 550, and they just can not erased again because indicated the back by banner C.
Next, step 560 is controlled by step 520 to 550 second condition loop forming.Till step 520 can repeat to each memory district in the memory cluster and all represents to have banner B or C to 550.To shown in 560, step 530 can be found out the memory district of electric leakage as step 520, and indicates with banner A, then in step 520 to 560 loop, just can not erased again in the memory district of electric leakage.Present embodiment is exactly to avoid deep layer excessively to erase whereby.In addition, it is that unit carries out that soft sequencing is confirmed to be with the bit line, and to be confirmed to be with mnemon (memory cell) be that unit carries out and erase, and therefore soft sequencing affirmation meeting is confirmed upward many soon than erasing.Erasing of step 550 is confirmed to be execution after the erase pulses of a succession of preset times, all carrying out the affirmation of once erasing unlike classic method after each erase pulses.By using soft sequencing to confirm in step 530, and reduce the execution frequency of erasing and confirming in step 550, the execution efficient of present embodiment can be far above classic method.Therefore present embodiment also only needs an address counter.
Next, be shown with the inhomogeneous memory district execution conservative erase (details aftermentioned) of banner C in step 570 pair memory cluster acceptance of the bid.If do not indicate the memory district of banner C, directly skips steps 570, and the flow process of present embodiment also so far finishes.So-called conservative erasing is a kind of method of the inhomogeneous memory district of can erasing safely, and the mode that its characteristic is to use slow sequencing (SLPGM) and applies erase pulses is repaired the bit line leakage phenomenon in inhomogeneous memory district.Conservative detailed process of erasing is illustrated in Fig. 6.
Fig. 6 is the conservative process flow diagram of erasing that is pursuant to one embodiment of the invention.Flow process is from step 610.At first carry out soft sequencing and confirm (SPGMV) in step 610 pair inhomogeneous memory district.For the memory district that confirms by above-mentioned soft sequencing, flow process can enter step 640.For the memory district that fails to confirm by above-mentioned soft sequencing, flow process can enter step 620, and these inhomogeneous memory districts are carried out slow sequencing (SLPGM).Slowly sequencing is more remarkable than soft sequencing for the raising effect of the critical voltage of flash memory cell.Therefore be difficult for electric leakage after bearing erase pulses through the mnemon of slow sequencing.That is to say, more can not look like classic method, must repair identical memory district repeatedly after the erase pulses each time.So conservative erasing can be faster than classic method.
Slowly after the sequencing, carry out slow sequencing in step 630 pair inhomogeneous memory district and confirm (SLPGMV).If there is the memory district to fail to confirm that by slow sequencing flow process can be got back to step 620, this loop can repeat to this memory district always to be ended by confirming as of step 630, and flow process enters step 640 then.In the present embodiment, the slow sequencing of the slow sequencing of step 620 and step 630 confirms all to use word group line (WL:word line) voltage of about 1V.
In step 640, inhomogeneous memory district is carried out the affirmation of erasing.For the memory district by the above-mentioned affirmation of erasing, flow process so far finishes.For the memory district that fails to erase and confirm by above-mentioned, flow process can enter step 650, and these memory districts are applied erase pulses.Flow process enters step 610 then, these memory districts is carried out the soft sequencing of another time confirm to check whether bit line leakage current is arranged.Whole conservative loop of erasing can circulate always, all affirmations of erasing by step 640 up to all memory districts.
In the present embodiment, slowly the word group line voltage of sequencing use is preferable with 1V, suffers long-term sequencing because work as flash memory cell, and its critical voltage can converge to convergence word group line voltage.Therefore after slow sequencing, the critical voltage that connects all flash memory cells of this word group line all can converge near 1V.The voltage of 1V is ideal value, because just in time between the critical voltage (0V) of confirming required critical voltage (3V) by erasing and taking place excessively to erase.This also is that conservative erasing need do not carried out slow sequencing to repair the reason of the mnemon of excessively erasing after each erase pulses, so can save the running time.So slowly sequencing is better than using the soft sequencing of 0V word group line voltage.
Fig. 7 is another method for erasing flash memory cluster that is pursuant to another embodiment of the present invention.The difference of Fig. 7 and Fig. 5 is to change the step 530 of Fig. 5 the step 730 of Fig. 7 into to 750 to 550.The part of difference only is described for simplicity.
After the erase pulses of step 520, no banner A and the memory district that do not have a banner B carry out strict soft sequencing and confirm (TSPGMV) in step 730 pair memory cluster.The soft sequencing of primary strictness confirms to use the initial word group line voltage of about 3V.If when the word group line voltage that strict soft sequencing is confirmed has dropped to about 0V, also have the memory district to fail to confirm, just indicate this memory and distinguish with banner A by above-mentioned strict soft sequencing.When word group line drop arrived 0V, strict soft sequencing was confirmed to be equal to soft sequencing and is confirmed (SPGMV).
Next, step 740 is controlled the condition loop of being made up of step 520 and 730.This loop can repeat memory district and fail to confirm by the soft sequencing of strictness, or the erase pulses of carrying out step 520 has been applied in till the preset times.Step 730 to be used strict soft sequencing to confirm and not to be used soft sequencing to be confirmed to be in order raising the efficiency.By the fast corresponding loop of Fig. 5 excessively of loop that step 520 to 740 is formed, stricter because strict soft sequencing is confirmed to confirm than general soft sequencing, use higher word group line voltage.So a memory district fails to confirm by the soft sequencing of strictness, can confirm faster generation by soft sequencing than failing.Comprise that the condition of preset times is because the critical voltage of mnemon may have only very slight decline after bearing erase pulses among the above-mentioned time figure.The restriction of this preset times can avoid loop to repeat too many time, even becomes infinite loop.The slight problem that descends of critical voltage if need not to worry, the restriction that can remove this preset times.So step 520 and 730 can repeat to remember always and distinguish till the strict soft sequencing affirmation of failing by step 730.
Through after the above-mentioned loop, no banner B and the memory district execution of not having the banner C affirmation of erasing in step 750 pair memory cluster.The main difference of the step 550 of the step 750 of Fig. 7 and Fig. 5 is if there is memory to distinguish the affirmation of erasing of failing by step 750, and when the strict soft sequencing of step 730 execution was confirmed, the word group line voltage of this memory district use can reduce about 0.5V next time.Owing to fail to be shown with mnemon by the confirmation form of erasing and fully do not erased, the strict soft sequencing of next time carrying out is confirmed to use lower word group line voltage, gives more erasing of deep layer of this mnemon.Note that among the step 730 3V of initial word group line voltage and all visual application demand of 0.5V of successively decreasing one by one and adjust.
The initial word group line voltage of suggestion use 3V is confirmed in above-mentioned strict soft sequencing, but does not limit 3V.Initial word group line voltage is according to deciding by the condition of confirming of erasing.For example in the present embodiment, the condition of passing through of the affirmation of erasing all is lower than 3V for the critical voltage of all flash memory cells.Confirm for the strict soft sequencing of using 3V word group line voltage,, just can not confirm by this strict soft sequencing if there is the critical voltage of any mnemon to be lower than 3V.That is to say that the critical voltage of some or all mnemon is lower than 3V.Even therefore above-mentioned mnemon fails to confirm by the soft sequencing of strictness, still might be by the affirmation of erasing.Confirming to be arranged in strict soft sequencing so erase confirms to carry out to judge whether mnemon fully erases afterwards.If by the affirmation of erasing, just do not need follow-up erase pulses at this, can save time.Otherwise if fail by the affirmation of erasing, expression still has the mnemon critical voltage that is higher than 3V, need apply erase pulses again.In the circulation next time of loop, the word group line voltage that strict soft sequencing is confirmed can be reduced to about 2.5V.If fail to confirm by this strict soft sequencing, represent that the critical voltage of some mnemon is lower than 2.5V, and critical voltage that might all mnemons is lower than 3V entirely, therefore can carry out the affirmation of erasing once again.The word group line drop of confirming when the soft sequencing of strictness arrives about 0V, fails this moment to confirm that by the soft sequencing of strictness expression has taken place excessively to erase.Word group line voltage is that the strict soft sequencing of 0V is confirmed to be equal to general soft sequencing affirmation, should not reduce word group line voltage this moment again.Above-mentioned memory district of excessively having erased may need conservative erasing to avoid deep layer excessively to erase.
Affirmation program previously discussed, for example soft sequencing are confirmed to confirm with strict soft sequencing, all are the known techniques of this technical field.More particularly, in the field of fast flash memory bank, all affirmation programs all are that the word group line in normal memory unit and reference memory unit respectively applies specific voltage, and this moment, the bit line voltage of two mnemons was approximately 1V, compare the electric current of two mnemons then.For example erase and be confirmed to be the voltage that respectively applies 5V at the word group line of normal memory unit and reference memory unit.In the case, the electric current of normal memory unit should be greater than the electric current of reference memory unit, and the normal memory unit could be by the affirmation of erasing.Confirming and strict soft sequencing affirmation as for soft sequencing, is the bit line current of more all normal memories unit and the electric current of reference memory unit.Because the bit line current is the electric current summation of all mnemons on the bit line, all word group lines of whole mnemon array all will apply specific voltage, apply voltage to one word group line and be not only.
In sum, the method for erasing flash memory cluster of above embodiment can avoid deep layer excessively to erase, and efficient is higher than classic method.Method of the present invention uses multiple banner to remember the state of distinguishing to distinguish, and only needs an address counter, so method of the present invention can be saved circuit area.Said method can be used for erasing flash memory section and memory cluster.Indicate the memory district that banner A and banner B are arranged because the soft sequencing stage after erase phase only need handle, said method also can be saved the time in soft sequencing stage.
In addition, at the conservative erasing method in the inhomogeneous memory district inhomogeneous memory district of can erasing safely, avoid deep layer excessively to erase among the above embodiment.Above-mentioned conservatively erase sooner, and need not repair identical electric leakage memory district repeatedly after the erase pulses each time than classic method.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.
Claims (16)
1. flash memory section erasing method is characterized in that it comprises:
(a) at least one the memory district to a fast flash memory bank carries out a soft sequencing affirmation;
(b) a memory district fails to confirm by this soft sequencing if above-mentioned at least one memory is distinguished wherein, then
(b1) this memory district is carried out a slow sequencing;
(b2) this memory district being carried out a slow sequencing confirms;
(b3) if this memory district fails by this slow sequencing affirmation, then once again execution in step (b1) to (b3);
(c) above-mentioned at least one memory district is carried out the affirmation of erasing; And
(d) if above-mentioned at least one memory district wherein fails by this affirmation of erasing in a memory district, then this memory district is applied the pulse of erasing, get back to step (a) then.
2. flash memory section erasing method according to claim 1 is characterized in that the word group line voltage when the slow sequencing of wherein this slow sequencing and this is confirmed to carry out is 1V.
3. method for erasing flash memory cluster is characterized in that it comprises:
(a) one first subclass to a flash memory cluster applies one first erase pulses;
(b) this first subclass is carried out one first a soft sequencing affirmation or a strict soft sequencing affirmation;
(c) repeating step (a) with (b) up to one first pre-conditioned be true;
(d) one second subclass of this memory cluster is carried out one first affirmation of erasing;
(e) repeating step (a) to (d) up to one second pre-conditioned be true;
(f) three subsetss to this memory cluster close execution one second soft sequencing affirmation;
(g) a memory district fails to confirm by this second soft sequencing if these three subsetss close wherein, then
(g1) this memory district is carried out a slow sequencing;
(g2) this memory district being carried out a slow sequencing confirms;
(g3) if this memory district fails by this slow sequencing affirmation, then once again execution in step (g1) to (g3);
(h) these three subsetss are closed carry out one second affirmation of erasing; And
(i) if these three subsetss close wherein a memory district fails then this memory district to be applied one second erase pulses by this second affirmation of erasing, get back to step (f) then.
4. method for erasing flash memory cluster according to claim 3, it is characterized in that this first subclass wherein is combined into no banner A in this memory cluster and does not have all memory districts of banner B, this second subclass is combined into no banner B in this memory cluster and does not have all memory districts of banner C, these three subsetss are combined into all memory districts that this memory cluster acceptance of the bid is shown with banner C, above-mentioned banner A fails the memory district that confirms or should the soft sequencing of strictness confirm by this first soft sequencing in order to sign, banner B is in order to indicating by this first memory district of erasing and confirming, banner C is in order to indicate existing banner A and to fail by this first memory district of erasing and confirming.
5. method for erasing flash memory cluster according to claim 4, what it is characterized in that wherein carrying out in step (b) is that this first soft sequencing is confirmed.
6. method for erasing flash memory cluster according to claim 5 is characterized in that wherein step (b) more comprises:
If this first a subclass wherein memory district fails to confirm by this first soft sequencing, then indicate this memory district with banner A.
7. method for erasing flash memory cluster according to claim 6 it is characterized in that wherein this is first pre-conditioned for having applied this first erase pulses of a preset times, or each memory district of this memory cluster has indicated banner A or banner B.
8. method for erasing flash memory cluster according to claim 4 is characterized in that wherein step (b) uses a default initial word group line voltage to carry out the soft sequencing affirmation of this strictness.
9. method for erasing flash memory cluster according to claim 8 is characterized in that should default initial word group line voltage being 3V wherein.
10. method for erasing flash memory cluster according to claim 8 is characterized in that wherein step (b) more comprises:
If this first a subclass wherein memory district fails to confirm by the soft sequencing of this strictness, and when should the soft sequencing of strictness confirming that employed this word group line voltage is 0V, then indicate this memory district with banner A;
And step (d) more comprises:
If this second a subclass wherein memory district fails then will remember employed this word group line voltage of the soft sequencing affirmation of this strictness of distinguishing and reduce by a preset value by this first affirmations of erasing.
11. method for erasing flash memory cluster according to claim 10 is characterized in that wherein this preset value is 0.5V.
12. method for erasing flash memory cluster according to claim 10 is characterized in that wherein this first pre-conditionedly wherein fails to confirm by the soft sequencing of this strictness in a memory district for this first subclass.
13. method for erasing flash memory cluster according to claim 10, it is characterized in that wherein this first pre-conditionedly wherein fails to confirm by the soft sequencing of this strictness in a memory district for this first subclass, or this first erase pulses has been applied in a preset times.
14. method for erasing flash memory cluster according to claim 4 is characterized in that wherein step (d) more comprises:
If this second a subclass wherein memory district then indicates this memory district with banner B by this first affirmation of erasing; And
If indicating the memory district that banner A is arranged fails then to indicate this memory district with banner C by this first affirmation of erasing.
15. method for erasing flash memory cluster according to claim 4 is characterized in that wherein this second pre-conditioned each memory district for this memory cluster has all indicated banner B or banner C.
16. method for erasing flash memory cluster according to claim 3, it is characterized in that wherein this slow sequencing with should be slow the sequencing affirmation all use the word group line voltage of 1V.
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