CN100565908C - 由碳化硅制造的单片垂直结场效应晶体管和肖特基势垒二极管及其制造方法 - Google Patents

由碳化硅制造的单片垂直结场效应晶体管和肖特基势垒二极管及其制造方法 Download PDF

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CN100565908C
CN100565908C CNB2005800230290A CN200580023029A CN100565908C CN 100565908 C CN100565908 C CN 100565908C CN B2005800230290 A CNB2005800230290 A CN B2005800230290A CN 200580023029 A CN200580023029 A CN 200580023029A CN 100565908 C CN100565908 C CN 100565908C
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麦克尔·S·马佐拉
约瑟夫·N·梅里特
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Mississippi State University
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Abstract

本发明描述了一种将具有蚀刻且注入的栅极的自对准的垂直结场效应晶体管和集成的反向平行的肖特基势垒二极管组合在一起的开关元件。二极管的阳极连接到该器件级的晶体管的源极以降低由杂散电感引起的耗损。SBD阳极区中的SiC表面通过干法蚀刻被调节以实现低肖特基势垒高度，从而降低与SBD的接通电压相关的功率耗损。

Description

由碳化硅制造的单片垂直结场效应晶体管和肖特基势垒二极管及其制造方法
本申请要求2004年7月8日申请的美国临时专利申请第60/585,881号的利益。在此以引用参考的方式将该临时申请的全部内容并入在本申请中。
依照美国空军授予的F33615-01-D-2103，本发明在政府资助下做出。政府可能对本发明享有一定的权利。
技术领域
本发明一般地涉及功率场效应晶体管的领域，具体地说涉及用于功率切换应用的碳化硅结场效应晶体管的领域。
背景技术
碳化硅结场效应晶体管(JFET)非常适合于高电压和高功率切换应用比如DC至DC转换器。目前垂直SiC JFET是SiC MOSFET的比较具有吸引力的替代方案，这是因为较低的反型沟道层迁移率和较差的高温、高场可靠性的缘故[1]。MOSFET也具有一个增加了寄生电容的固有的内置的体型二极管，这种寄生电容又导致了切换耗损的增加。然而，这种内置的反向平行的p-n二极管在要求反向平行的续流二极管的电路方面比较有用。将二极管内置在开关中消除了由将开关的源极连接到分立二极管的阳极所要求的键合引起的杂散电感〔2〕。然而，不好的是，这种二极管是具有大量的存储电荷的p-n二极管，在该二极管从正向到反向偏压时必须清除该存储电荷。清除这种存储电荷增加了总的切换时间并降低了电路的工作频率。肖特基二极管并没有存储电荷的问题，并且可以比p-n二极管切换得快得多。
已经提出了将SBD(肖特基势垒二极管)与MOSFET〔2，3〕和双极型结晶体管〔4〕集成的其它方案。也已经提出了具有将SBD并入在共享的漂移区上的横向栅极的FET〔5〕，同时还提出了将SBD与埋入在III-V半导体上制造的平行栅极的垂直JFET结合的其它方案〔6〕。
然而，仍然还需要一种切换器件，这种切换器件具有MOSFET体型二极管的好处但没有与切换内置的p-n二极管相关的耗损。
发明内容
根据第一实施例，提供了一种包括垂直结场效应晶体管(JFET)和肖特基(Schottky)势垒二极管(SBD)的SiC半导体器件。该器件包括第一导电型的SiC半导体衬底层、设置在衬底层上的第一导电型的SiC漂移层、设置漂移层上的第一导电型的多个SiC源极区和在漂移层中形成的与第一导电型不同的第二导电型的多个SiC栅极区。第一导电型的材料可以是n型半导体材料，而第二导电型的材料可以是p型半导体材料。栅极区可以通过将第二导电型的掺杂剂离子注入在漂移层中形成。该器件进一步包括在与漂移层相对地与衬底层相邻以及与源极区和栅极区相邻的欧姆触点以形成JFET。该器件也包括肖特基结，该肖特基结包括与漂移层相邻的肖特基金属层。肖特基金属层在JFET的源极欧姆触点之上延伸以使肖特基金属与该器件的源极欧姆触点电接触。根据这种实施例，JFET的漏极也用作SBD的阴极，并且JFET的源极也用作SBD的阳极。
该器件进一步包括设置在肖特基金属层上和在漏极和栅极欧姆触点上的最终金属层。此外，该器件的漂移层可以包括设置在衬底上的第一导电型的漂移区和设置在漂移区之上的也是第一导电型的沟道区，其中源极区设置在沟道区上。沟道区可以具有比下面的漂移区更高的掺杂水平。
根据第二实施例，提供一种制造包括垂直结场效应晶体管(JFET)和肖特基势垒二极管(SBD)的SiC半导体器件的方法。根据本实施例的方法包括：
将第一掩模定位在第一导电型的SiC的源极层上，其中源极层与第一导电型的SiC漂移层相邻，其中漂移层与第一导电型的SiC衬底层相邻；
选择性地蚀刻穿过源极层并进入漂移层以形成由蚀刻区分隔的升高的源极区；
将第二导电型的掺杂剂注入到漂移层的被暴露部分中以使注入区是第二导电型的SiC；
清除第一掩模；
使该器件退火以激活掺杂剂；
将第二掩模定位在该器件的源极层上；
通过选择性地蚀刻穿过该器件的注入层以暴露第一导电型的材料，形成栅极区、肖特基阳极区以及可选择地形成边缘端部结构；
清除第二掩模；
将电介质材料淀积在该器件的被暴露的蚀刻表面上；
蚀刻电介质材料以暴露源极区；
选择性地蚀刻穿过在栅极区之上的电介质材料以暴露注入的材料；
将金属淀积在暴露的源极区和栅极区以分别形成源极欧姆触点和栅极欧姆触点；
与漂移层相对地将金属淀积在衬底上以形成漏极欧姆触点；
选择性地蚀刻穿过在肖特基阳极区之上的电介质以暴露第一导电型的材料；
将肖特基金属层淀积在肖特基阳极区中并与源极欧姆触点接触；
将金属层淀积在肖特基金属层和栅极欧姆触点上以形成电接触焊盘；
与漂移层相对地在衬底上形成金属层以形成漏极欧姆触点；和
在漏极欧姆触点上形成金属层以形成漏极电接触焊盘；
其中该器件包括包含源极、栅极和漏极的JFET和包含阴极和阳极的SBD，其中JFET的漏极也用作SBD的阴极，其中JFET的源极也用作SBD的阳极。
第一导电型的材料可以是n型半导体材料，第二导电型的材料可以是p型半导体材料。根据进一步的实施例，源极层比下面的漂移层更重地掺杂。此外，漂移层可以包括设置在衬底上的第一导电型的漂移区和设置在所述漂移区上的同样为第一导电型的沟道区，其中源极区设置在沟道区上。沟道区可以具有比下面的漂移区更高的掺杂水平。
以上阐述的方法可以进一步包括在阳极区中进一步蚀刻以清除其中剩余的注入的材料。这样，可以形成具有适合的较低的肖特基势垒高度的器件。
根据第三实施例，提供一种制造包括垂直结场效应晶体管(JFET)和肖特基势垒二极管(SBD)的SiC半导体器件的方法，该方法包括：
将第一掩模定位在第一导电型的SiC的源极层上，其中源极层与第一导电型的SiC漂移层相邻，其中漂移层与第一导电型的SiC衬底层相邻；
选择性地蚀刻穿过源极层并进入漂移层以形成由蚀刻区分隔的升高的源极区；
将第二掩模定位在暴露的漂移(层)部分上；
将第二导电型的掺杂剂注入到漂移层的被暴露部分中以使注入区是第二导电型的SiC，其中由第二掩模屏蔽的漂移层部分形成肖特基阳极区；
清除第一和第二掩模；
使该器件退火以激活掺杂剂；
将第三掩模定位在该器件的源极层和注入的漂移层部分上；
通过选择性地蚀刻穿过该器件的注入层以暴露第一导电型的材料，形成栅极区以及可选择地形成边缘端部结构；
清除第三掩模；
将电介质材料淀积在该器件的被暴露的蚀刻表面上；
蚀刻电介质材料以暴露源极区；
选择性地蚀刻穿过在栅极区之上的电介质材料以暴露注入的材料；
将金属淀积在暴露的源极区和栅极区上以分别形成源极欧姆触点和栅极欧姆触点；
与漂移层相对地将金属淀积在衬底上以形成漏极欧姆触点；
选择性地蚀刻穿过在SBD阳极区之上的电介质材料以暴露第一导电型的材料；
将肖特基金属层淀积在肖特基阳极区中并与源极欧姆触点接触；
将金属层淀积在肖特基金属层和栅极欧姆触点上以形成电接触焊盘；
与漂移层相对地在衬底上形成金属层以形成漏极欧姆触点；和
在漏极欧姆触点上形成金属层以形成漏极电接触焊盘；
其中该器件包括包含源极、栅极和漏极的JFET和包含阴极和阳极的SBD，其中JFET的漏极也用作SBD的阴极，其中JFET的源极也用作SBD的阳极。
附图说明
附图1A-1D所示为根据本发明的一种实施例制造JFET的方法；
附图2所示为包括垂直沟槽JFET和集成反向平行肖特基二极管的器件的剖视图；
附图3A-3K所示制造包括垂直沟槽JFET和集成反向平行肖特基二极管的器件的第一方法；
附图4A-4K示出了制造包括垂直沟槽JFET和集成反向平行肖特基二极管的器件的第二方法，其中注入掩模用于在栅极注入步骤中防止肖特基阳极区的离子注入。
具体实施方式
本发明将沟槽VJFET与共享公共漂移区的集成的肖特基势垒二极管(SBD)结合在一起。如上文所述，将肖特基势垒二极管(SBD)与功率结场效应晶体管在单片上合并，形成了一种开关，这种开关具有MOSFET体型二极管的优点，同时没有与切换内置的p-n二极管相关的耗损。除了更快的反向恢复时间之外，SBD通常比p-n二极管具有低得多的接通电压。例如，对于钛SBD，典型的Von是大约0.8V，而对于SiC p-n二极管，典型Von是大约2.8伏。对于中等的电流密度，这对于在p-n上的SBD带来了低得多的功率耗损。
已经提出了用于SiC JFET的许多设计〔7-10〕。在此所描述的器件包括自对准的垂直JFET，这种JFET的基本结构与在美国专利申请第10/193,108(下文称为“’108申请”，出版为美国专利申请出版物2003/0034495A1，在此以引用参考的方式将其全部内容都并入在本申请中)中描述的注入的栅极结FET相同。这种注入的栅极VJFET与SBD结合，这个SBD的阳极形成在与JFET公共的漂移层上。SBD的阳极和JFET的源极通过金属焊盘电连接。JFET的漏极触点也还作为SBD的阴极。另一接触焊盘将JFET的栅极端子形成在欧姆触点上，该欧姆触点形成在指状源极的基底处的注入的p型层上。源极/阳极接触焊盘通过电介质层与栅极区隔离。
在’108申请中公开的技术可用于制造该器件的JFET部分。制造JFET的实例性方法在附图1A-1D中示出。如附图1A所示，提供了其上设置有相同导电型的漂移层32和源极层34的SiC衬底层30。附图显示掩模36设置在源极层34上。如附图1B所示，然后通过源极层34选择性地蚀刻源极特征(例如指状物)并通过掩模36中的开口38蚀刻进入漂移层32。如附图1C所示，相同的蚀刻掩模36然后可用作注入掩模以使用离子注入过程选择性地形成栅极区40。
在注入的栅极区40的形成之后，可以清除掩模36并将漏极触点42设置在衬底层30上。这个步骤在附图1D中示出。此外，如附图1D所示，栅极欧姆触点44可以设置在注入栅极区40上，并且源极欧姆触点46可以设置在源极层34的未蚀刻的部分上以形成该器件。
如下文更详细地阐述，在该器件的JFET部分的制造中使用的上文描述的某些步骤也可用于该器件的SBD部分的制造中。
附图2所示为根据本发明的一种实施例包括JFET和SBD的器件的剖视图。如附图2所示，栅极欧姆触点不仅在较大面积接触焊盘之下，而且也还在指状源极之间延伸。用于延长栅极指状物的长度的欧姆触点在某些应用中是理想的但不是必须的。
附图2也示出了台面保护环边缘端部。这种形式的边缘端部在制造和功能方面类似于在美国专利第6,693,308号(下文称为“’308专利”，该专利的全部内容以引用参考的方式并入在本申请中)中所描述的端子。然而，在’308专利中所述的器件中，保护环被蚀刻成外延生长的p型层，而注入的p型层在附图2中示出。也可使用包括(但不限于)JTE、场板或隔离该器件的台面的其它形式的边缘端部替代被蚀刻的保护环。
如附图2所示，该器件具有高度掺杂n型(n+)的顶部外延层(即盖层)。与这个层相邻的是具有比用于形成沟道区的上文描述的n+盖更低地掺杂的n型层。与沟道相邻的是n型漂移层或区。漂移区可以具有与沟道区相同或更低的掺杂浓度。如果使用相同的掺杂水平，则漂移和沟道区可以由单层形成。与漂移区相邻的是另一n+层，它将形成漏极触点的基础。这个层可以是在其上外延生长其它的层的n型衬底。
根据进一步的实施例包括JFET和SBD的器件可以通过下文概述的方法制造。这个方法在附图3A-3K中示出。如附图3A所示，提供了包括半导体衬底50、漂移层52、沟道层54和源极或盖层58的多层结构。如上文所阐述，可替换地，多层结构可以包括单个漂移层，而不是分离的漂移层和沟道层。
在界定指状源极的区域上对离子注入/蚀刻掩模56进行构图(附图3B)。
SiC被干蚀刻到延伸过n+盖层并通过一些或整个沟道区的深度(如果利用了不同的沟道区)或者进入形成该器件的沟道/漂移区的单层中。这在附图3C中示出。
然后对试样注入p型掺杂剂以将暴露的SiC 60的顶层从n型转换为p型(附图3D)。
剥离注入/蚀刻掩模并对晶片进行退火以使注入的掺杂剂电激活(未示)。
然后以用于界定该器件的栅极区以及保护环(如果应用保护环的话)的干蚀刻掩模62对晶片进行构图(附图3E)。从左边暴露场区和SBD阳极区64。
将被暴露的SiC向下蚀刻经过p+注入区的基体，直到相邻的器件不通过所说的p-层66电连接(附图3F)。
剥离上述蚀刻掩模62，并淀积和/或处理电介质68以使得指状源极的顶部上的电介质厚度比在指状物之间并在场中的电介质的厚度薄得多(附图3G)。
蚀刻掉电介质直到指状源极的顶部露出，同时在其它任何地方留下足够量的氧化物(附图3H)。
对栅极焊盘窗口进行构图并向下蚀刻到p+栅极区70(附图3H)。
然后淀积并退火适合的金属或金属叠层以在该器件的源极、栅极和漏极(72，74和76)上形成欧姆触点。
对SBD阳极窗口78进行构图并向下蚀刻氧化物直到n型沟道54(如图所示)或漂移区52(未示)(附图3J)。然后进一步蚀刻被暴露的SiC以从肖特基阳极区中清除任何注入的“尾部”或残余注入损伤。残余p型掺杂剂或注入损伤可能增加形成在该表面上的SBD的接通电压。
然后将肖特基势垒金属80形成在SBD阳极窗口和源极触点(72)上(附图3J)。然后可以将源极/阳极和栅极(82，84)的最终接触焊盘金属淀积在晶片的顶部上(附图3K)。可以同时淀积用于源极、栅极和阳极的接触焊盘金属。
然后淀积背侧最终金属88(附图3K)。
在附图4A-4K中示出了制造包括JFET和SBD的器件的变型方法。如附图4A所示，提供了包括半导体衬底50、漂移层52、沟道层54和源极或盖层58的多层结构48。虽然没有示出，可替换地，多层结构可包括包含单个区的漂移层而不是分离的漂移区和沟道区。在界定指状源极的区域上对离子注入/蚀刻掩模56构图(附图4B)。SiC被干蚀刻到延伸过n+盖层并通过一些或全部沟道区(如果利用不同的沟道区的话)的厚度或者进入形成该器件的沟道/漂移区(未示)的单层(附图4C)。从附图4C中可以看出，掩模57被定位在沟道层上的蚀刻的材料上(或者在漂移层上，如果不存在沟道层的话)。掩模57将用于界定肖特基阳极区64。然后给试样注入p型掺杂剂以将暴露的SiC 60的顶层从n型转换到p型(附图4D)。从附图4D中可以看出，肖特基阳极掩模57防止沟道层54被注入在肖特基阳极区64中。注/蚀刻掩模56和肖特基阳极掩模57然后被剥离，并对晶片进行退火以使注入的掺杂剂电激活(未示)。然后通过用于界定该器件的栅极区和保护环(如果利用保护环的话)的干蚀刻掩模62对晶片构图(附图4E)。从左边暴露器件的场区。此外，SBD阳极区64可以从左边被暴露或者屏蔽63。被暴露的SiC向下蚀刻经过p+注入区的基体，直到相邻的器件不通过所说的p-层66电连接(附图4F)。SBD阳极的未注入的沟道层(54)在这个蚀刻步骤中可以被蚀刻掉以暴露下面的漂移区。可替换地，暴露的沟道层可以保留在肖特基阳极区中。然后剥离蚀刻掩模62(和可选择地，63)，并淀积和/或处理电介质68以使得指状源极的顶部上的电介质厚度比在指状物之间和场中的电介质厚度薄得多(附图4G)。蚀刻掉电介质直到指状源极的顶部暴露出来，同时在其它的任何地方留下大量的氧化物(附图4H)。栅极焊盘窗口被构图和向下蚀刻到p+栅极区70(附图4H)。然后对适合的金属或金属叠层进行淀积和退火以在器件的源极、栅极和漏极上形成欧姆触点(72，74和76)(附图4I)。SBD阳极窗口78被构图，氧化物被向下蚀刻到n型沟道54(如图所示)或者在SBD阳极区中的漂移区52(未示)(附图4J)。然后将肖特基势垒金属80形成在SBD阳极窗口中和源极触点(72)上(附图4J)。
肖特基金属可以被淀积在如附图4K所示的沟道层54上。可替换地，肖特基金属可以被淀积在下面的漂移区上(未示)。在沟道层上形成的肖特基二极管一般具有比包括形成在漂移区上的肖特基二极管的类似器件更低的接通电压，但具有更高的反向泄漏。该器件的特定的性能要求可以指示使用哪种方法。肖特基金属在肖特基阳极的外围上可以与一部分注入的材料重叠，只要注入的材料不电连接到JFET的注入栅极即可。然后可以将用于源极/阳极和栅极(82，84)的最终接触焊盘金属淀积在晶片的顶部上(附图4K)。可以同时淀积源极、栅极和阳极的接触焊盘金属。
附图3和4所示为可用于制造如附图2所示的包括垂直结场效应晶体管(JFET)和肖特基势垒二极管(SBD)的器件的基本过程。可以增加其它的细节并且可以重新排列某些步骤的顺序以获得该器件。
下文描述各种实施例。
根据第一实施例，提供一种包括垂直结场效应晶体管(JFET)和肖特基势垒二极管(SBD)的SiC半导体器件。该器件包括第一导电型的SiC半导体衬底层、设置在衬底层上的第一导电型的SiC漂移层、设置在漂移层上的第一导电型的多个SiC源极区和在漂移层上形成的与第一导电型不同的第二导电型的多个SiC栅极区。栅极区可以通过在n型漂移层中的p型掺杂剂的离子注入形成。该器件进一步包括与漂移层相对地与衬底层相邻以及与源极和栅极区相邻的欧姆触点以形成JFET。该器件也包括包含与漂移层相邻的肖特基金属层的肖特基结。肖特基金属层可以在JFET的源极欧姆触点之上延伸以使肖特基金属接触该器件的源极欧姆触点。该器件进一步包括设置在肖特基金属层上和在漏极和栅极欧姆触点上的最终金属层。根据这种实施例，JFET的漏极也用作SBD的阴极，JFET的源极也用作SBD的阳极。漂移层可以包括设置在衬底上的第一导电型的漂移区和设置在漂移区上的也是第一导电型的沟道区，其中源极或盖层设置在沟道区上。根据这种实施例，沟道区可以具有比下面的漂移区更高的掺杂水平。根据本实施例的实例性器件在附图2中示出。
根据进一步的实施例，提供了一种制造包括JFET和SBD的SiC半导体器件的方法。根据这种实施例的方法包括：
将第一掩模定位在第一导电型的SiC的源极层上，其中源极层与第一导电型的SiC漂移层相邻，其中漂移层与第一导电型的SiC衬底层相邻；
选择性地蚀刻穿过源极层并进入漂移层以形成由蚀刻区分开的升高的源极区；
将第二导电型的掺杂剂注入到漂移层的被暴露部分中以使注入区是第二导电型的SiC；
清除第一掩模；
使该器件退火以激活掺杂剂；
将第二掩模定位在该器件的源极层上；
通过选择性地蚀刻穿过该器件的注入层以暴露第一导电型的材料，形成栅极区、肖特基阳极区以及可选择地形成边缘端部结构；
清除第二掩模；
将电介质材料淀积在该器件的被暴露的蚀刻表面上以使得在升高的源极区上的电介质材料更薄；
蚀刻电介质材料以暴露源极区；
选择性地蚀刻穿过在栅极区之上的电介质材料以暴露注入的材料；
将金属淀积在暴露的源极区和栅极区上以分别形成源极欧姆触点和栅极欧姆触点；
与漂移层相对地将金属淀积在衬底上以形成漏极欧姆触点；
选择性地蚀刻穿过在SBD阳极区之上的电介质以暴露第一导电型的材料；
将肖特基金属层淀积在SBD阳极中并与源极欧姆触点接触；
将金属层淀积在肖特基金属层和栅极欧姆触点上以形成电接触焊盘；
与漂移层相对地在衬底上形成金属层以形成漏极欧姆触点；和
在漏极欧姆触点上形成金属层以形成漏极电接触焊盘；
其中该器件包括包含源极、栅极和漏极的JFET和包含阴极和阳极的SBD，其中JFET的漏极也用作SBD的阴极，JFET的源极也用作SBD的阳极。
根据进一步的实施例，第一导电型的材料是n型半导体材料，第二导电型的材料是p型半导体材料。根据进一步的实施例，源极层比下面的漂移层更重地掺杂。此外，漂移层可以包括设置在衬底上的第一导电型的漂移区和设置在所述漂移区上的同样为第一导电型的沟道区，其中源极层设置在沟道区上。沟道区可以具有比下面的漂移区更高的掺杂水平。
如上文所阐述的方法可以进一步包括在阳极区中的附加蚀刻，以清除其中剩余的注入的材料。这样，可以形成具有适合的较低的肖特基势垒高度的器件。
适合于掺杂SiC的施主材料包括氮和磷。氮是优选的施主材料。适合于掺杂碳化硅的受主材料包括硼和铝。铝是优选的受主材料。然而，上文的材料仅仅是实例性的，可以使用能够被掺杂到碳化硅中的任何施主和受主材料。
可以改变该器件的各种层的掺杂水平和厚度，以生产具有用于特定应用的所需特性的器件。除非另有说明之外，重掺杂对应于1018原子·cm-3或更大的掺杂剂浓度，轻掺杂对应于5×1016原子·cm-3或更小的掺杂剂浓度，中度掺杂对应于5×1016原子·cm-3和1018原子·cm-3之间的掺杂剂浓度。
器件的漂移层可以是以施主材料轻掺杂的(即n-掺杂的)SiC层，衬底层可以是以施主材料重掺杂的(即n+掺杂的)SiC层。此外，源极区可以是n+掺杂的SiC，栅极区可以是p或p+掺杂的SiC。
SiC漂移层、沟道层和源极层的掺杂可以在这些层中的每个层在SiC衬底上外延生长的过程中原地执行。SiC层可以通过在本领域中公知的任何外延生长方法形成，包括CVD、分子束和升华外延。掺杂的SiC层可以在外延生长的过程中通过原地掺杂形成，其中掺杂剂原子在生长的过程中并入到碳化硅中。
虽然前文的说明书通过为说明目的提供的实例教导了本发明的原理，但是应该理解的是本领域普通技术人员通过阅读本说明书可以在形式和细节上进行各种修改而不脱离本发明的真实范围。
参考文献
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Claims (25)

1.一种包括垂直结场效应晶体管和肖特基势垒二极管的SiC半导体器件，该SiC半导体器件包括：
第一导电型的SiC半导体衬底层；
设置在所述衬底层上的第一导电型的SiC漂移层；
设置在所述漂移层上的第一导电型的多个SiC源极区；
在所述漂移层中形成的与第一导电型不同的第二导电型的多个SiC栅极区；
包括与所述漂移层相邻的肖特基金属层的肖特基结；以及
与所述漂移层相对地与衬底层相邻以及与所述源极区和栅极区相邻的欧姆触点；
其中所述肖特基金属层在与所述源极区相邻的欧姆触点之上延伸以使肖特基金属和与所述源极区相邻的欧姆触点电接触，并且
所述垂直结场效应晶体管的漏极也用作所述肖特基势垒二极管的阴极，所述垂直结场效应晶体管的源极也用作所述肖特基势垒二极管的阳极。
2.权利要求1的SiC半导体器件，其中第一导电型的材料是n型半导体材料，第二导电型的材料是p型半导体材料。
3.权利要求1的SiC半导体器件，其中所述栅极区是通过在所述漂移层中离子注入第二导电型的掺杂剂而形成的。
4.权利要求1的SiC半导体器件，其中进一步包括设置在所述肖特基金属层上和所述漏极和栅极欧姆触点上的最终金属层。
5.权利要求1的SiC半导体器件，其中所述漂移层包括设置在所述衬底上的第一导电型的漂移区和设置在所述漂移区上的同样为第一导电型的沟道区，其中所述源极区设置在所述沟道区上。
6.权利要求5的SiC半导体器件，其中所述沟道区具有比下面的漂移区更高的掺杂水平。
7.权利要求1的SiC半导体器件，其中所述漂移层具有5×1016原子·cm-3或更小的掺杂剂浓度。
8.权利要求1的SiC半导体器件，其中所述衬底层具有1018原子·cm-3或更大的掺杂剂浓度。
9.权利要求1的SiC半导体器件，其中所述源极区具有1018原子·cm-3或更大的掺杂剂浓度。
10.权利要求1的SiC半导体器件，其中所述栅极区具有1018原子·cm-3或更大的掺杂剂浓度。
11.权利要求1的SiC半导体器件，其中所述栅极区具有在5×1016原子·cm-3和1018原子·cm-3之间的掺杂剂浓度。
12.权利要求1的SiC半导体器件，其中
所述漂移层具有5×1016原子·cm-3或更小的掺杂剂浓度；
所述衬底层具有1018原子·cm-3或更大的掺杂剂浓度；
所述源极区具有1018原子·cm-3或更大的掺杂剂浓度；和
所述栅极区具有至少5×1016原子·cm-3的掺杂剂浓度。
13.一种制造包括垂直结场效应晶体管和肖特基势垒二极管的SiC半导体器件的方法，包括：
将第一掩模定位在第一导电型的SiC的源极层上，其中源极层与第一导电型的SiC漂移层相邻，所述漂移层与第一导电型的SiC衬底层相邻；
选择性地蚀刻穿过所述源极层并进入所述漂移层以形成由蚀刻区分开的升高的源极区；
将第二导电型的掺杂剂注入到所述漂移层的暴露部分中，以使注入区是第二导电型的SiC；
清除第一掩模；
使该器件退火以激活掺杂剂；
将第二掩模定位在该器件的源极层上；
通过选择性地蚀刻穿过该器件的所述注入区以暴露第一导电型的材料，形成栅极区、肖特基阳极区以及可选择地形成边缘端部结构；
清除第二掩模；
将电介质材料淀积在该器件的被暴露的蚀刻表面上以使所述电介质在升高的源极区上更薄；
蚀刻所述电介质材料以暴露所述源极区；
选择性地蚀刻穿过在栅极区之上的电介质材料以暴露所述注入区的材料；
将金属淀积在暴露的源极区和栅极区以分别形成源极欧姆触点和栅极欧姆触点；
与所述漂移层相对地将金属淀积在衬底上以形成漏极欧姆触点；
选择性地蚀刻穿过在肖特基势垒二极管阳极区之上的电介质材料以暴露第一导电型的材料；
将肖特基金属层淀积在所述肖特基阳极区中并使之与所述源极欧姆触点接触；
将金属层淀积在所述肖特基金属层和栅极欧姆触点上以形成电接触焊盘；
与所述漂移层相对地在衬底上形成金属层以形成漏极欧姆触点；和
在所述漏极欧姆触点上形成金属层以形成漏极电接触焊盘；
其中该器件包括包含源极、栅极和漏极的垂直结场效应晶体管和包含阴极和阳极的肖特基势垒二极管，其中垂直结场效应晶体管的漏极也用作肖特基势垒二极管的阴极，垂直结场效应晶体管的源极也用作肖特基势垒二极管的阳极。
14.权利要求13的方法，其中第一导电型的材料是n型半导体材料，第二导电型的材料是p型半导体材料。
15.权利要求13的方法，其中所述源极层比下面的漂移层被更重地掺杂。
16.权利要求13的方法，其中所述漂移层包括设置在衬底上的第一导电型的漂移区和设置在所述漂移区上的同样为第一导电型的沟道区，其中所述源极区设置在所述沟道区上。
17.权利要求16的方法，其中所述沟道区具有比下面的漂移区更高的掺杂水平。
18.权利要求13的方法，进一步包括在所述阳极区中进行蚀刻以清除其中剩余的被注入的材料。
19.权利要求13的方法，其中
所述漂移层具有5×1016原子·cm-3或更小的掺杂剂浓度；
所述衬底层具有1018原子·cm-3或更大的掺杂剂浓度；
所述源极区具有1018原子·cm-3或更大的掺杂剂浓度；和
所述栅极区具有至少5×1016原子·cm-3的掺杂剂浓度。
20.一种制造包括垂直结场效应晶体管和肖特基势垒二极管的SiC半导体器件的方法，包括：
将第一掩模定位在第一导电型的SiC的源极层上，其中源极层与第一导电型的SiC漂移层相邻，所述漂移层与第一导电型的SiC衬底层相邻；
选择性地蚀刻穿过所述源极层并进入所述漂移层以形成由蚀刻区分开的升高的源极区；
将第二掩模定位在所述漂移层被暴露的部分上；
将第二导电型的掺杂剂注入到所述漂移层的被暴露部分中以使注入区是第二导电型的SiC，其中所述漂移层的由第二掩模屏蔽的部分形成肖特基阳极区；
清除第一和第二掩模；
使该器件退火以激活掺杂剂；
将第三掩模定位在该器件的源极层和被注入的漂移层部分上；
通过选择性地蚀刻穿过该器件的所述注入区以暴露第一导电型的材料，形成栅极区以及可选择地形成边缘端部结构；
清除第三掩模；
将电介质材料淀积在该器件的被暴露的蚀刻表面上；
蚀刻电介质材料以暴露所述源极区；
选择性地蚀刻穿过在所述栅极区之上的电介质材料以暴露所述注入区的材料；
将金属淀积在暴露的源极区和栅极区上以分别形成源极欧姆触点和栅极欧姆触点；
与所述漂移层相对地将金属淀积在衬底上以形成漏极欧姆触点；
选择性地蚀刻穿过在肖特基势垒二极管阳极区之上的电介质材料，以暴露第一导电型的材料；
将肖特基金属层淀积在肖特基阳极区中并与所述源极欧姆触点接触；
将金属层淀积在所述肖特基金属层和栅极欧姆触点上以形成电接触焊盘；
与所述漂移层相对地在衬底上形成金属层以形成漏极欧姆触点；和
在所述漏极欧姆触点上形成金属层以形成漏极电接触焊盘；
其中该器件包括包含源极、栅极和漏极的垂直结场效应晶体管和包含阴极和阳极的肖特基势垒二极管，其中垂直结场效应晶体管的漏极也用作肖特基势垒二极管的阴极，垂直结场效应晶体管的源极也用作肖特基势垒二极管的阳极。
21.权利要求20的方法，其中第三掩模覆盖所述肖特基阳极区。
22.权利要求20的方法，其中第三掩模不覆盖所述肖特基阳极区，其中形成栅极区以及可选择地形成边缘端部结构的步骤包括在所述肖特基阳极区中蚀刻所述漂移层。
23.权利要求20的方法，其中所述漂移层包括设置在所述衬底上的第一导电型的漂移区和设置在所述漂移区上的同样为第一导电型的沟道区，其中所述源极区设置在所述沟道区上。
24.权利要求23的方法，其中所述肖特基金属层被淀积在该器件的肖特基阳极区中的沟道区上。
25.权利要求24的方法，其中所述肖特基金属层被淀积在该器件的肖特基阳极区中的漂移区上。
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