CN100570844C - A kind of multi-chip IC package - Google Patents
A kind of multi-chip IC package Download PDFInfo
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- CN100570844C CN100570844C CNB2004100159724A CN200410015972A CN100570844C CN 100570844 C CN100570844 C CN 100570844C CN B2004100159724 A CNB2004100159724 A CN B2004100159724A CN 200410015972 A CN200410015972 A CN 200410015972A CN 100570844 C CN100570844 C CN 100570844C
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2924/151—Die mounting substrate
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- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The invention discloses a kind of multi-chip IC package and structure thereof, method comprises step: adopt the carrier of metal lead wire frame as the encapsulation of multicore sheet; The employing silicon chip to form the silicon chip substrate, is provided with the wiring of chip interconnect as substrate on substrate; On metal lead wire frame, put silicon chip as substrate; On substrate, stack a plurality of chips that will encapsulate; The a plurality of chips that will encapsulate are adopted the gold threads interconnection or be connected on the silicon chip substrate; With gold thread the silicon chip substrate is connected with metal lead wire frame again; With chip, substrate, metal lead wire frame plastic packaging in one.Using such method and obtain encapsulating structure correspondingly and broken through the multicore sheet and can only adopt the present situation of BGA Package form in system in package has realized the packing forms of metal pins.Also reduced simultaneously manufacturing technique requirent and packaging cost, also widened the function of the multichip IC after the encapsulation neatly substrate.
Description
Technical field
The present invention relates to the encapsulation of integrated circuit (IC) chip, more specifically refer to a kind of multi-chip IC package.
Background technology
At present, in to the integrated circuit (IC) chip encapsulation, a plurality of bare chips are interconnected as system, and " system in package (the SIP) " scheme that is assembled in the single encapsulation comes into one's own day by day.Though " SOC (system on a chip) (SOC) " scheme can and be manufactured on the single nude film a plurality of chip functions designs, have " system in package (SIP) " too in the advantage that provides aspect circuit board packing density and the reliability, but compare with " system in package (SIP) ", " SOC (system on a chip) (SOC) " scheme exists the design cycle long, research and development expense height, be difficult to circuit integrated limitations of entering such as high frequency, high pressure, therefore " system in package (SIP) " must not develop rapidly owing to there is not above shortcoming.
" system in package " be integrated with mostly CPU, ' a plurality of functions such as RAM, ROM, I/O, the complicated interconnection in the system between the multicore sheet must realize by substrate, the printed circuit board (PCB) of the effect of substrate and common installation electronic devices and components is identical.
In Chip Packaging, the substrate of " system in package " all adopts glass epoxy printed board so far, and just littler, thinner than common printed substrate, it is meticulousr to connect up.In existing tens of kinds of encapsulation technologies commonly used, be broadly divided into two classes:
The first kind is to adopt the scheme of metal (copper, nickel) lead frame, as DIP, TSOP, QFP, PLCC etc., this type of scheme, with metal lead wire frame as chip carrier, chip 1 links by gold thread 2 and metal lead wire frame 3 and outwards draws (see figure 1), and capsulation material 4 is with its sealing.
Second class is to adopt the scheme of nonmetal pin, as ball grid array (BGA), as chip carrier, chip 1 links to each other with printed substrate 5 by gold thread 2 this type of scheme with miniature printed wiring board, and draw (see figure 2) by the soldered ball 6 of bottom, and with capsulation material 4 with its sealing.Its advantage is to draw soldered ball to be distributed on the floor space, can only draw on side with frame pin and compare, and has the density height, size is little, can arrange a large amount of pins.
In the encapsulation of multicore sheet,, can only place silicon chip on the metal framework, and not allow to place miniature printed wiring board for the restriction of temperature coefficient match.Therefore " system in package " is interconnect substrates owing to adopting miniature printed wiring board so far, and (1 is chip among Fig. 4, and 2 is the gold thread that connects just to have only employing ball grid array (BGA) packing forms, 5 is printed substrate, 6 is soldered ball, and 4 is capsulation material), and do not allow to adopt the metal pins packing forms.This has just limited to the range of application of " system in package " chip, and its limitation is that the complete system plant that much can assemble the metal pins chip does not have equipment and the ability that the chip that adopts BGA Package is installed; Simultaneously a large amount of low side electronic products does not wish to adopt the chip of BGA Package for the consideration that reduces packing density, chip cost and manufacturing technique requirent yet.How to solve the problems referred to above that exist in the encapsulation of multicore sheet, perplexing the people in the industry always.
Summary of the invention
The objective of the invention is at multicore sheet encapsulation exist above-mentioned all to adopt miniature printed wiring board be substrate, can only realize the problem of BGA Package, a kind of multi-chip IC package and structure thereof are proposed, so that the integrated circuit scope of application after the encapsulation of multicore sheet is more wide.
To achieve these goals, the present invention adopts following technical scheme:
This multi-chip IC package may further comprise the steps:
A adopts the carrier of metal lead wire frame as the encapsulation of multicore sheet;
B, adopt silicon chip as substrate forming the silicon chip substrate, and the wiring of chip interconnect is set on the silicon chip substrate;
C puts the silicon chip substrate on metal lead wire frame;
D stacks a plurality of chips that will encapsulate on the silicon chip substrate;
E adopts the gold threads interconnection with a plurality of chips that will encapsulate or is connected on the silicon chip substrate;
F is connected the silicon chip substrate with gold thread again with metal lead wire frame;
G, with chip, silicon chip substrate, metal lead wire frame plastic packaging in one.
This multichip IC encapsulating structure comprises a plurality of chips, substrate, metal lead wire frame, capsulation material, described substrate adopts silicon sheet material to form the silicon chip substrate, at the silicon chip substrate wiring of chip interconnect is set, the silicon chip substrate places within the metal lead wire frame top; Described a plurality of chip places on the silicon chip substrate, between chip and the chip, be connected by gold thread between chip and the silicon chip substrate; Also be connected between described silicon chip substrate and the metal lead wire frame by gold thread; Described capsulation material is packaged in one with a plurality of chips, silicon chip substrate, metal lead wire frame.
In technique scheme of the present invention, silicon chip is placed in metal lead wire frame as substrate, and on the silicon chip substrate, stack a plurality of chips that will encapsulate, a plurality of chips adopt gold thread to be connected on the substrate, with gold thread the silicon chip substrate is connected with metal lead wire frame again, and with chip, silicon chip substrate, metal lead wire frame plastic packaging in one.Resulting thus multichip IC encapsulating structure adopts ball grid array package structure to compare with tradition, has the following advantages:
1, broken through the multicore sheet and can only adopt the present situation of BGA Package form, realized the packing forms of metal pins in system in package.
2, also greatly reduce manufacturing technique requirent to substrate.
3, adopt silicon chip to make substrate and can realize the unapproachable more complicated system interconnection of printed substrate.
4, adopt silicon chip will use printed substrate as the substrate cost far below routine as the cost of substrate.
5, widened the function of the multichip IC after the encapsulation neatly by increasing the mask number of plies.
Description of drawings
Fig. 1 a and Fig. 1 b are respectively conventional metals lead frame single-chip package structure and analyse and observe and elevational schematic view.
The ball grid array single-chip package structure that Fig. 2 a and Fig. 2 b are respectively traditional is analysed and observe and elevational schematic view.
Fig. 3 is traditional ball grid array multichip packaging structure cross-sectional schematic.
Fig. 4 is the encapsulating structure cross-sectional schematic of multicore sheet of the present invention.
Embodiment
Multi-chip IC package of the present invention may further comprise the steps:
A adopts the carrier of metal lead wire frame as the encapsulation of multicore sheet;
B, adopt silicon chip as substrate forming the silicon chip substrate, and the wiring of chip interconnect is set on the silicon chip substrate;
C puts the silicon chip substrate on metal lead wire frame;
D stacks a plurality of chips that will encapsulate on the silicon chip substrate;
E adopts the gold threads interconnection with a plurality of chips that will encapsulate or is connected on the silicon chip substrate;
F is connected the silicon chip substrate with gold thread again with metal lead wire frame;
G, with chip, silicon chip substrate, metal lead wire frame plastic packaging in one.
In the described steps d, when on the silicon chip substrate, stacking a plurality of chip, a plurality of chips can be stacked one deck or which floor.
When a plurality of chips that stack on the silicon chip substrate stack to one deck, will interconnect with gold thread with the chip of one deck, or chip is being connected on the silicon chip substrate with gold thread;
When a plurality of chips that stack on the silicon chip substrate stacked to which floor, the last layer chip all adopted gold thread to be connected on the silicon chip substrate or on the chip of lower floor.
The annexation that stacks altogether on the silicon chip substrate between what layer chip, each layer how much chip of placement and the chip is decided on the concrete integrated circuit of required making.Chip all will be received on the silicon chip substrate after connecting, and then by gold thread silicon chip substrate and metal lead wire frame is coupled together but in general.
See also shown in Figure 4 according to the packaged multichip IC encapsulating structure of said method of the present invention, in this structure, comprise a plurality of chips 1, metal lead wire frame 3, capsulation material 4, substrate 7, described substrate 7 adopts silicon sheet material to form the silicon chip substrate, the wiring of chip interconnect is set on silicon chip substrate 7, and silicon chip substrate 7 places in the metal lead wire frame 3; Described a plurality of chip 1 places on the silicon chip substrate 7, is connected by gold thread 2 between chip 1 and the silicon chip substrate 7; Also be connected between silicon chip substrate 7 and the metal lead wire frame 3 by gold thread 2; Described capsulation material 4 is packaged in one with a plurality of chips 1, metal lead wire frame 3, silicon chip substrate 7.
Described a plurality of chip 1 is one deck or which floor is stacked and placed on the silicon chip substrate 7.
When a plurality of chips stacked on the silicon chip substrate 7 are one deck, interconnect by gold thread with the chip 1 of one deck, or chip 1 is connected on the silicon chip substrate 7 by gold thread 2;
When a plurality of chips 1 stacked on the silicon chip substrate 7 stack to which floor, last layer chip 1 adopt gold thread 2 to be connected on the silicon chip substrate 7 or the chip 1 of lower floor on.
The advantage of said method of the present invention and structure is described below:
Adopt the substrate of silicon chip, thereby make " system in package " break through the present situation that can only adopt the BGA Package form, realized the packing forms of metal pins as " system in package ".
Adopt silicon chip as substrate, not only make " system in package " to realize the metal pins packing forms, also greatly reduce manufacturing technique requirent substrate.In fact the miniature printed wiring board that substrate adopts at present belongs to identical technology and technology with the circuit board of common installation electronic devices and components, live width that its common process can be accomplished and line-spacing are 4 Mills (100um), and substrate is below 3 Mills (75um) to the requirement of live width and line-spacing, the technological limits that has surpassed printed substrate, therefore its cost and technology difficulty have all increased greatly, and its cost will account for the 40%-50% of BGA Package total cost usually.And live width that the silicon chip common process can be accomplished and line-spacing are that 0.6urn (6 cun wafers) is to 1.2um (4 cun wafers), even the silicon wafer-based printed line is wide and the density of line-spacing has improved 50 demultiplications to 1.5um than printed substrate, great technology affluence degree is also arranged, so can guarantee high qualification rate easily.Because the wiring density of silicon chip improves more than 50 times than printed substrate, therefore adopt silicon chip to make substrate and can realize the unapproachable more complicated system interconnection of printed substrate simultaneously.
Aspect the substrate cost; to be higher than printed substrate though it is generally acknowledged silicon chip unit are cost; but in fact; the substrate that Chip Packaging is used; miniature printed wiring board cost will be far above conventional printed substrate; adopting silicon chip to do the cost of substrate simultaneously will be far below custom integrated circuit; chip cost is to increase progressively according to the number of plies that adds the mask in man-hour; for the substrate silicon chip; only need two-layer wiring; comprise that interlayer metal via hole and protective layer only need 4 layers of mask to get final product, the silicon chip that therefore is used for substrate is cheaply more over half than miniature printed wiring board reality.When this external substrate cost allows, can increase functional substrate neatly by increasing the mask number of plies, as adding resistance, simple logic or high voltage conversion etc.
In order to be illustrated more clearly in both difference, also can consult following table, to carry out the performance comparison after substrate adopts miniature printed wiring board respectively and adopts silicon chip:
In concrete encapsulating structure, known to aforementioned, the annexation that stacks altogether on the silicon chip substrate between what layer chip, each layer how much chip of placement and the chip is decided on the concrete integrated circuit of required making.In embodiment illustrated in Figure 5, stacked two layers of chip on the silicon chip substrate altogether, the last layer chip has three, and one deck adjacent with substrate has two, and one deck chip adjacent with the silicon chip substrate all has gold thread to be connected on the silicon chip substrate separately.Interconnect earlier between three chip blocks of last layer, and then be connected on the substrate with gold thread.Can understand at an easy rate, the encapsulating structure of different integrated circuits should comprise the chip of different function and quantity, and chip is stacked in the number of plies on the silicon chip substrate and the annexation between each chip.The main core of the present invention is to adopt silicon chip to carry various chips as substrate and encapsulate.Those of ordinary skill in the art will be appreciated that, above embodiment is used for illustrating the present invention, and be not to be used as limitation of the invention, as long as in connotation scope of the present invention, all will drop in the scope of claims of the present invention variation, the modification of the above embodiment.
Claims (3)
1, a kind of multi-chip IC package is characterized in that, this method may further comprise the steps:
A adopts the carrier of metal lead wire frame as the encapsulation of multicore sheet;
B, adopt silicon sheet material as substrate forming the silicon chip substrate, and the wiring of chip interconnect is set on the silicon chip substrate;
C puts the silicon chip substrate on metal lead wire frame;
D stacks a plurality of chips that will encapsulate on the silicon chip substrate;
E adopts the gold threads interconnection with a plurality of chips that will encapsulate or is connected on the silicon chip substrate;
F is connected the silicon chip substrate with gold thread again with metal lead wire frame;
G, with chip, silicon chip substrate, metal lead wire frame plastic packaging in one.
2, multi-chip IC package as claimed in claim 1 is characterized in that:
In the described steps d, when on the silicon chip substrate, stacking a plurality of chip, a plurality of chips can be stacked one deck or which floor.
3, multi-chip IC package as claimed in claim 1 or 2 is characterized in that:
When a plurality of chips that stack on the silicon chip substrate stack to one deck, will interconnect with gold thread with the chip of one deck, or chip is being connected on the silicon chip substrate with gold thread;
When a plurality of chips that stack on the silicon chip substrate stacked to which floor, the last layer chip all adopted gold thread to be connected on the silicon chip substrate or on the chip of lower floor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100159724A CN100570844C (en) | 2004-01-19 | 2004-01-19 | A kind of multi-chip IC package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100159724A CN100570844C (en) | 2004-01-19 | 2004-01-19 | A kind of multi-chip IC package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1649115A CN1649115A (en) | 2005-08-03 |
| CN100570844C true CN100570844C (en) | 2009-12-16 |
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| CNB2004100159724A Expired - Fee Related CN100570844C (en) | 2004-01-19 | 2004-01-19 | A kind of multi-chip IC package |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102074540B (en) * | 2010-11-26 | 2013-01-09 | 天水华天科技股份有限公司 | Matrix dual in-line package (DIP) lead frame, integrated circuit (IC) packages based on frame and production method of IC packages |
| CN102944709A (en) * | 2011-08-16 | 2013-02-27 | 北京天中磊智能科技有限公司 | Electric meter module structure realized by adopting multi-chip system-level packaging technology and packaging method thereof |
| CN102368484A (en) * | 2011-10-11 | 2012-03-07 | 常熟市广大电器有限公司 | Multichip integrated circuit packaging structure |
| CN103296014A (en) * | 2012-02-28 | 2013-09-11 | 刘胜 | Fan-out wafer level semiconductor chip three-dimensional stacking packaging structure and technology |
| JP6162643B2 (en) * | 2014-05-21 | 2017-07-12 | 三菱電機株式会社 | Semiconductor device |
| CN105895588A (en) * | 2014-12-30 | 2016-08-24 | 华天科技（西安）有限公司 | Multi-component, copper frame and substrate-mixed installed encapsulation structure and preparation method thereof |
| US9818727B2 (en) | 2015-03-09 | 2017-11-14 | Mediatek Inc. | Semiconductor package assembly with passive device |
-
2004
- 2004-01-19 CN CNB2004100159724A patent/CN100570844C/en not_active Expired - Fee Related
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