CN100573899C - The embedded phase change ram of self-aligned and manufacture method thereof - Google Patents
The embedded phase change ram of self-aligned and manufacture method thereof Download PDFInfo
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- CN100573899C CN100573899C CNB2007101082899A CN200710108289A CN100573899C CN 100573899 C CN100573899 C CN 100573899C CN B2007101082899 A CNB2007101082899 A CN B2007101082899A CN 200710108289 A CN200710108289 A CN 200710108289A CN 100573899 C CN100573899 C CN 100573899C
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Abstract
The invention discloses a kind of integrated circuit with in-line memory, it comprises substrate and a plurality of conductor layer, these conductor layers is set in order to connect each element of integrated circuit.Intermediate layer in a plurality of conductor layers comprises first electrode with upper surface, second electrode with upper surface and the insulating component between first and second electrode.Lead bridge location on the intermediate layer, between first and second electrode, across the insulating component place, wherein this is led bridge and comprises programmable resistance storage medium, for example phase-change material.Conductor in one deck at least in a plurality of conductor layers is positioned on the intermediate layer and is connected to and leads bridge.
Description
The party of joint study contract
New York IBM, Taiwan Wang Hong Internaional, Inc and technology company of German Infineon (Infineon Technologies A.G) are the party of joint study contract.
Related application data
The application and the U.S. of submitting on June 17th, 2005 continue partly that application is relevant, and the application number of this application is 11/155,067, and denomination of invention is " THIN FILM FUSE PHASECHANGE RAM AND MANUFACTURING METHOD ".
Technical field
The present invention relates to use the high-density memory device of phase-change storage material, comprise material and other material, and relate in order to make the method for this device based on chalcogenide.
Background technology
Applied in the writable disc widely with the storage medium that becomes the basis mutually.These materials include at least two kinds of solid-state phases, comprise that as major part be amorphous solid-state phase, and the solid-state phase that is substantially crystalline state.Laser pulse is used for writable disc, switching in mutually at two kinds, and reads the optical property of this material after phase transformation.
As this phase-change storage material of chalcogenide and similar material, can be applicable to electric current in the integrated circuit by applying its amplitude, and cause the crystalline phase conversion.Generally speaking amorphous feature is that its resistance is higher than crystalline state, and this resistance value can measure easily and indicate in order to conduct.This specific character then causes uses programmable resistor material with interest such as formation Nonvolatile memory circuits, and this circuit can be used for the arbitrary access read-write.
Be converted to crystalline state from amorphous state and be generally the low current step.Be converted to amorphous state (below be called as replacement (reset)) from crystalline state and be generally high electric current step, it comprises that an of short duration high current density pulse is to melt or to destroy crystalline texture, thereafter this phase-change material cooling fast, the process that suppresses phase transformation makes that the partial phase change structure is maintained in amorphous state at least.Under the perfect condition, causing phase-change material to be converted to amorphous reset current amplitude from crystalline state should be low more good more.Desire reduces the required reset current amplitude of resetting, can reach by size that lowers the phase change material element in internal memory and the contact area that reduces electrode and this phase-change material, therefore can apply less absolute current value and reach higher current density at this phase change material element.
A kind of method of this field development is devoted to form small hole on integrated circuit structure, and uses micro-programmable resistance material to fill these small holes.The patent of being devoted to this small hole comprises: United States Patent (USP) the 5th, 687, No. 112 " Multibit Single Cell Memory Element Having Tapered Contact ", invention people of bulletin were Ovshinky on November 11st, 1997; In No. the 5th, 789,277, the United States Patent (USP) of on August 4th, 1998 bulletin " Method of Making Chalogenide[sic] Memory Device ", invention people is Zahorik etc.; United States Patent (USP) the 6th in bulletin on November 21st, 2000,150, No. 253 " Controllable Ovonic Phase-Change Semiconductor Memory Deviceand Methods of Fabricating the Same ", invention people are Doan etc.
When making these devices and desire with very little yardstick and satisfy the volume production storage device, during required strict state-variable, then can suffer from problem.A kind of memory cell (memory cell) structure with small size and low reset current preferably is provided, and in order to make the method for this structure, the strict state-variable specification when it can satisfy the volume production storage device.More preferably, provide a kind of fabrication schedule and structure, itself and manufacturing peripheral circuit compatibility on same integrated circuit.
Summary of the invention
According to a first aspect of the invention, a kind of memory device is provided, comprise: a substrate, it comprises the integrated circuit member, comprise a plurality of conductor layers, these conductor layers are in order to being connected to the described integrated circuit component of small part, and described a plurality of conductor layers comprise ground floor and are positioned at special layer on this ground floor; Should comprise first electrode with upper surface, second electrode, the insulating component between this first electrode and this second electrode by special layer with upper surface; Lead bridge, it is between this first and second electrode and across this insulating component place, and this is led bridge and has first side and second side, and with this first side contacts this upper surface to this first and second electrode, wherein this is led bridge and has storage medium, and this storage medium has at least two kinds of solid-state phases; And conductor, being arranged in one decks at least of described a plurality of conductor layers, this conductor is positioned on this special layer and contact is led bridge to this.
According to a second aspect of the invention, provide a kind of integrated circuit, having comprised: Semiconductor substrate; A plurality of circuit elements, it has a plurality of terminals, these terminals are included in the doped region in this Semiconductor substrate, and this Semiconductor substrate comprises having in order to the outer peripheral areas of the functional circuit elements of deal with data and the array region with access circuit element, and this access circuit element is used for the programmable memory cell array; A plurality of conductor layers, these conductor layers are connected to this array region in order to what will be arranged in this outer peripheral areas to the described functional circuit elements of small part, and described a plurality of conductor layers comprise and are positioned at the ground floor on this Semiconductor substrate and are positioned at special layer on this ground floor; Should comprise electrode pair array by special layer, wherein each in this electrode pair array comprises first electrode with upper surface, second electrode with upper surface, insulating component between this first electrode and this second electrode to electrode; The bridge array of leading able to programme, between this first and second electrode of leading this counter electrode centering of bridge arrangement in this special layer in this array, across this insulating component place, this is led bridge and has first side and second side, and with this first side contacts this upper surface to this first and second electrode, and wherein this is led bridge and comprises storage medium, and this storage medium has at least two kinds of solid-state phases; And a plurality of conductors, its be arranged in described a plurality of conductor layers one deck at least this array region and be positioned on this special layer, these conductors are connected to this each described bridge of leading of leading in the bridge array able to programme as bit line.
According to a third aspect of the invention we, provide a kind of in order to make the method for memory element, comprise: form a plurality of circuit elements in Semiconductor substrate, these circuit elements have a plurality of terminals, these terminals comprise the doped region that is arranged in this Semiconductor substrate, and this Semiconductor substrate comprises having in order to the outer peripheral areas of the functional circuit elements of deal with data and the array region with access circuit element, and this access circuit element is used for the programmable memory cell array; Form a plurality of conductor layers, these conductor layers are connected to this array region in order to what will be arranged in this outer peripheral areas to the described element of small part, and described a plurality of conductor layers comprise and are positioned at the ground floor on this Semiconductor substrate and are positioned at special layer on this ground floor; Should be included in this array region by special layer, it has upper surface and comprises electrode pair array, this electrode pair array comprises corresponding first electrode and second electrode and is positioned at this first and second interelectrode corresponding insulating component, wherein this first and second electrode and this insulating component extend to this upper surface of this special layer, and this insulating component has width between this upper surface of this first and second electrode; Form bridge of memory material array this upper surface at this special layer, this leads the bridge of leading that the bridge array comprises each electrode pair of use in this electrode pair array, this first and second electrode that its contact is corresponding, and extension is across this insulating component of correspondence, this is led bridge and comprises the storage medium film with first side and second side, and with this first side contacts this first and second electrode to correspondence, this is led bridge definition and is positioned at this first and second interelectrode current path across this insulating component place, this current path length is defined by this width of this insulating component, and wherein this storage medium has at least two kinds of solid-state phases; And form patterned conductive layer and lead on the bridge at this, and form between described first electrode and this patterned conductive layer of crosspoint array in this electrode pair array, the corresponding contact of this second electrode contact to this crosspoint array wherein.
The present invention describes a kind of phase-change random access storage (PCRAM) device, and it is applicable to the volume production integrated circuit.Technology described herein comprises memory element, and it comprises first electrode with top side, second electrode with top side and the insulating component between first electrode and second electrode.Insulating component has a thickness between first and second electrode, near the top side of first electrode and the top sides of second electrode.Film is led bridge across insulating component, and the definition electrode between the path between first and second electrode, across the insulating component place.Across path between the electrode of insulating component, have a path, its thickness by insulating component is defined.For convenience of description, this is led bridge and can be considered structure as fuse.Yet for phase transition storage, its not similar fuse, but having comprised chalcogenide materials or similar material with at least two kinds of solid-state phases, described two kinds of solid-state phases can be by applying electric current betwixt or apply voltage between first and second electrode and reversibly bring out.
The volume that is subjected to the storage medium of phase transformation can be very small, and by the thickness (path of x axle) of insulating component, in order to form the film thickness (y axle) of leading bridge and to lead that the width (z axle) perpendicular to path is defined in the bridge.In an embodiment, the thickness of insulating component and lead the thickness of the film storage medium of bridge in order to formation is defined by the thickness of thin-film technique, is not limited in order to form two pattern process of this memory cell.The width of leading bridge is less than minimum feature size F, and this characteristic size F is peculiar by employed photoetching process when the material layer of the patterning embodiment of the invention.In one embodiment, the width of leading bridge utilizes the photoresist pruning technique to define, wherein mask pattern in order to definition photoetching photoresist structure on this chip, it has minimum feature size F, and this photoresist structure utilizes isotropic etching to prune to reach the characteristic size less than F.Photoresist structure through pruning then is used to shift the insulation material layer of this narrower pattern to the storage medium.Simultaneously, page or leaf can use other technology to form the narrow line of material in the one deck in integrated circuit.Therefore, have the phase-change memory cell of simple structure, can reach the purpose of very small reset current and low power consuming, and be easy to make.
In the embodiment of technology of the present invention, provide memory cell array.In this array, a plurality of electrode members and the insulating component between electrode member form electrode layer on integrated circuit.This electrode layer has upper surface, and it is smooth in fact surface in certain embodiments of the invention.Between the paired electrode member, lead bridge, on the upper surface of electrode layer, form electrode member across corresponding a plurality of films of insulating component.First electrode from electrode layer, the film that passes through the electrode layer upper surface are led bridge and are arrived the current path of second electrode in the electrode layer, are formed among each memory cell in this array.
In the present invention, the circuit under the electrode layer in the integrated circuit utilizes knownly to form in order to the technology that forms logical circuit and storage array circuit, for example complementary metal oxide semiconductor (CMOS) technology.In one embodiment, for example transistorized insulation device has under at least one in electrode pair of a terminal second electrode, between second electrode of the memory cell of a conductor in this transistorized terminal and this array, forms connection simultaneously.According to exemplary embodiments, the circuit under electrode layer comprises many bias lines (for example common source conductor) and a plurality of insulation device.A plurality of insulation devices have first terminal, second terminal that is coupled to a bias line in these many bias lines and extend to second terminal and first electrode between conductor, this first electrode is arranged in the electrode layer of a corresponding stored unit of this array.In addition, in the circuit under electrode layer, provide many word lines.Those word lines system in the array each row and be coupled to the insulation device of memory cell, make that the control signal may command memory cell on the word line is connected to many bias lines along each row of correspondence.In one embodiment of the invention, many bias lines are arranged and are in close proximity to row corresponding paired in this array, and in a plurality of insulation device, are coupled to two row insulation devices of corresponding paired column of memory cells, are coupled to the shared bias line in many bias lines.
Embodiment described herein is integrated into the embedded storage array on the integrated circuit, and this integrated circuit has one, two, three or multilevel metallization, perhaps has other patterning conductor layer.In such embodiments, substrate comprises integrated circuit component, comprises a plurality of conductor layers, and it is in order to connect the subelement at least in these elements.A plurality of conductor layers comprise ground floor and special layer, and this special layer is positioned on the ground floor, and between the ground floor in a plurality of patterning conductor layer (or bottom) and one deck at last (or top layer).Should comprise first electrode with upper surface, second electrode with upper surface and the insulating component between first electrode and second electrode by special layer, wherein special conductor layer comprises the storage organization electrode layer.Simultaneously, insulating component utilizes self-aligned technology and is formed on the sidewall of first electrode structure.Bridge of memory material is formed on the special conductor layer, also contacts to first electrode and second electrode across insulating component.
In addition, in an array implement example of the present invention, the circuit that is positioned on the electrode layer comprises multiple bit lines.Be arranged in embodiment on the electrode layer at bit line, the electrode member in the electrode layer is as first electrode of memory cell, and is shared and makes the unitary electrode member that first electrode with two memory cell of delegation is provided in this array.Similarly, in one embodiment of the invention, multiple bit lines in the array each row and arrange, and two consecutive storage units in corresponding row share a contact point structure, with contact to this first electrode.
The present invention also describes a kind of method of making memory element.The method comprises that this substrate comprises the circuit that utilizes the FEOL manufacturing in the center pattern conductor layer of formation electrode layer on substrate.Electrode layer in this method has upper surface.This electrode layer comprises the insulating component between first electrode and second electrode and first and second electrode in each phase-change memory cell to be formed.First and second electrode and insulating component extend to the upper surface of electrode layer, and insulating component has a thickness at the upper surface place of first and second electrode, as above-mentioned phase-change memory cell structure.This method also comprises and forms bridge of memory material on the upper surface of electrode layer, across the insulating component place of each memory cell to be formed.This is led bridge and comprises the storage medium film, and it has first side and second side, and this film utilizes its first side and contacts to first and second electrode.This leads between bridge definition electrode the path between first and second electrode, across the insulating component place, and the path in path between electrode is defined by the thickness of insulating component.In the embodiment of this method, the access structure on electrode layer is to lead on the bridge and form forming to contact between first electrode and the patterned conductive layer at this by forming patterned conductive layer.
In the embodiment of this manufacture method, this electrode layer is formed by following a plurality of step:
Form dielectric layer on substrate;
Form first conductive layer on dielectric layer;
Etched pattern in first conductive layer, this pattern comprise that zone between the lamination that exposes this substrate and the lamination that is positioned on the substrate comprise the remainder of dielectric layer and the remainder of first conductive layer, and this lamination has sidewall;
Form the side wall dielectric layer on this lamination and etching sidewall dielectric layer to form on the sidewall of sidewall spacer at lamination;
Form second conductive layer on the zone between lamination, sidewall spacer and the lamination; And
Utilize cmp or other method to grind this second conductive layer, to define this electrode layer, wherein this sidewall spacer is exposed to upper surface and is used as insulating component, the part of first conductive layer in lamination is exposed to upper surface and as first electrode, and the zone between lamination and second conductive layer that is exposed to upper surface are partly as second electrode.
In an embodiment of this manufacture method, this bridge of memory material is utilized following a plurality of step manufacturings:
Form storage material layer on the upper surface of electrode layer;
Form one deck photoresist material on storage material layer;
Utilize this photoresist material layer of photoetching process patterning, with the definition list structure;
The width of pruning this list structure is narrower with definition, the photoresist material strips through pruning is on storage material layer;
The part of in the etching storage material layer, not protected by this narrower photoresist material strips is to form the storage medium bar; And
Patterning storage medium bar is led bridge to define this.
Described in the invention leads the method for bridge in order to formation, is used for the memory cell of PCRAM, and can be in order to make the very small bridge of leading of other function.Have the very small nanosecond science and technology device of leading bridge construction, utilize material beyond the phase-change material such as metal, dielectric, organic material, semiconductor etc. and form.
Below describe structure of the present invention and method in detail.Description of contents chapters and sections purpose of the present invention is not to be to define the present invention.The present invention is defined by claims.Such as embodiments of the invention, feature, purpose and advantage etc. can see through following explanation claims and fully understanding of accompanying drawing acquisition.
Description of drawings
Fig. 1 illustrates the embodiment that the phase change memory device film is led bridge;
The phase change memory device film that Fig. 2 illustrates Fig. 1 is led the current path in the bridge;
The phase change memory device film that Fig. 3 illustrates among Fig. 1 is led the active area of bridge;
The phase change memory device film that Fig. 4 illustrates among Fig. 1 is led the size of bridge;
Fig. 5 illustrates the structure of a pair of phase change memory device, comprises being positioned at the access circuit under the electrode layer and being positioned at bit line on the electrode layer;
Fig. 6 is the plane graph that the structure among Fig. 5 is shown;
Fig. 7 is the schematic diagram that storage array is shown, and it comprises phase change memory device;
Fig. 8 is the calcspar that includes the integrated circuit (IC)-components of thin film phase change storage array and other circuit;
Fig. 9 is the profile of substrate, and it includes from the access circuit of FEOL manufacturing, and this substrate is by in order to the method for the phase change memory device structure of shop drawings 5 and make;
Figure 10 is the initial step profile in order to the technology of the electrode layer that forms Fig. 5;
Figure 11 A and 11B are step plane graph and the profile that illustrates in order to the structure of patterning Figure 10, wherein form the polar stack in the electrode layer of Fig. 5 structure;
Figure 12 illustrates in order to form the corresponding step profile of side wall insulator on the polar stack in Figure 11 B;
Figure 13 illustrates in order to form the corresponding step profile of one deck conductor material on the structure of Figure 12;
Figure 14 illustrates in order to the corresponding step profile of the conductor material among grinding Figure 13 with side wall insulator;
Figure 15 illustrates in order to form phase change material film layer and the structural corresponding step profile of protection cover layer at Figure 14;
Figure 16 A and 16B illustrate plane graph and the profile that carries out patterning at the phase change material film layer among Figure 15, have wherein formed the strip photoresist on phase-change material;
Figure 17 A and 17B are plane graph and the profile that illustrates in order to the phase change material film layer among patterning Figure 15, show that wherein strip photoresist among etch figures(s) 16A and the 16B is to form narrower strip photoresist;
Figure 18 A and 18B illustrate according to the photoresist pattern among Figure 17 A and the 17B and carry out the plane graph and the profile of the phase change material strip after the etching at the phase change material film layer;
Figure 19 A and 19B illustrate plane graph and the profile that carries out patterning at the phase change material strip among Figure 18 A and the 18B, and it leads bridge on electrode layer in order to form phase-change material;
Figure 20 A and 20B illustrate pattern according to Figure 19 A and 19B to carry out plane graph and the profile that phase-change material after the etching is led bridge;
Figure 21 is illustrated in the structure shown in Figure 20 A and the 20B (comprise electrode layer and phase-change material lead bridge) to go up the step profile that forms dielectric fill layer;
Figure 22 A and 22B are illustrated in to form conductive plug in the dielectric fill layer to contact plane graph of leading bridge and the profile to Figure 21 structure;
Figure 23 illustrates in order to form the step profile of patterned conductive layer structure on the structure of Figure 22 A and 22B;
Figure 24 A-24E illustrates the alternative techniques in order to the beveled electrode layer, corresponding to technology shown in Figure 14;
Figure 25 A and 25B illustrate in order to make the first step that one group of technology of bridge and electrode structure is led in the self-aligned storage, and it has used the mask pruning technique;
Figure 26 A and 26B illustrate in order to make second step that one group of technology of bridge and electrode structure is led in the self-aligned storage, and it has used the mask pruning technique;
Figure 27 A and 27B illustrate in order to make the third step that one group of technology of bridge and electrode structure is led in the self-aligned storage, and it has used the mask pruning technique;
Figure 28 A and 28B illustrate in order to make the first step that one group of technology of bridge and storage organization is led in the self-aligned storage, and it has utilized leads bridge sidewall mask;
Figure 29 A and 29B illustrate in order to make second step that one group of technology of bridge and storage organization is led in the self-aligned storage, and it has utilized leads bridge sidewall mask;
Figure 30 A and 30B illustrate in order to make the third step that one group of technology of bridge and storage organization is led in the self-aligned storage, and it has utilized leads bridge sidewall mask;
Figure 31 A and 31B illustrate in order to make the 4th step that one group of technology of bridge and storage organization is led in the self-aligned storage, and it has utilized leads bridge sidewall mask;
Figure 32 A and 32B illustrate in order to make the 5th step that one group of technology of bridge and storage organization is led in the self-aligned storage, and it has utilized leads bridge sidewall mask;
Figure 33 illustrates in order to make the 6th step that one group of technology of bridge and storage organization is led in the self-aligned storage, and it has utilized leads bridge sidewall mask;
Figure 34 A and 34B illustrate the first step in order to one group of technology making bridge of memory material, and it has used mosaic technology;
Figure 35 A and 35B illustrate second step in order to one group of technology making bridge of memory material, and it has used mosaic technology;
Figure 36 illustrates the third step in order to one group of technology making bridge of memory material, and it has used mosaic technology;
Figure 37 illustrates the 4th step in order to one group of technology making bridge of memory material, and it has used mosaic technology;
Figure 38 illustrates the 5th step in order to one group of technology making bridge of memory material, and it has used mosaic technology;
Figure 39 A and 39B illustrate the 6th step in order to one group of technology making bridge of memory material, and it has used mosaic technology;
Figure 40 illustrates the first step in order to one group of technology making bridge of memory material, and it has used alternative mosaic technology;
Figure 41 A and 41B illustrate second step in order to one group of technology making bridge of memory material, and it has used alternative mosaic technology;
Figure 42 A and 43B illustrate the third step in order to one group of technology making bridge of memory material, and it has used alternative mosaic technology;
Figure 43 A and 43B illustrate the 4th step in order to one group of technology making bridge of memory material, and it has used alternative mosaic technology;
Figure 44 A and 44B illustrate the 5th step in order to one group of technology making bridge of memory material, and it has used alternative mosaic technology;
Figure 45 illustrates the 6th step in order to one group of technology making bridge of memory material, and it has used alternative mosaic technology;
Figure 46 illustrates the 7th step in order to one group of technology making bridge of memory material, and it has used alternative mosaic technology;
Figure 47 illustrates in order to form narrow material to lead the first step of one group of technology of bridge, and it utilizes bilateral sidewall mask process;
Figure 48 illustrates in order to form narrow material and leads second step of one group of technology of bridge, and it utilizes bilateral sidewall mask process;
Figure 49 illustrates in order to form narrow material and leads the third step of one group of technology of bridge, and it utilizes bilateral sidewall mask process;
Figure 50 illustrates in order to form narrow material and leads the 4th step of one group of technology of bridge, and it utilizes bilateral sidewall mask process;
Figure 51 illustrates in order to form narrow material and leads the 5th step of one group of technology of bridge, and it utilizes bilateral sidewall mask process;
Figure 52 illustrates in order to form narrow material and leads the 6th step of one group of technology of bridge, and it utilizes bilateral sidewall mask process;
Figure 53 illustrates in order to form narrow material and leads the 7th step of one group of technology of bridge, and it utilizes bilateral sidewall mask process;
Figure 54 A and 54B illustrate in order to form narrow material and lead the 8th step of one group of technology of bridge, and it utilizes bilateral sidewall mask process;
Figure 55 illustrates the first step in order to the dual-damascene technics of the electrode layer that forms memory element of the present invention;
Figure 56 illustrates second step in order to the dual-damascene technics of the electrode layer that forms memory element of the present invention;
Figure 57 illustrates the third step in order to the dual-damascene technics of the electrode layer that forms memory element of the present invention;
Figure 58 illustrates the 4th step in order to the dual-damascene technics of the electrode layer that forms memory element of the present invention;
Figure 59 illustrates the 5th step in order to the dual-damascene technics of the electrode layer that forms memory element of the present invention;
Figure 60 illustrates the 6th step in order to the dual-damascene technics of the electrode layer that forms memory element of the present invention;
Figure 61 illustrates the 7th step in order to the dual-damascene technics of the electrode layer that forms memory element of the present invention;
Figure 62 illustrates the 8th step in order to the dual-damascene technics of the electrode layer that forms memory element of the present invention;
Figure 63 illustrates the 9th step in order to the dual-damascene technics of the electrode layer that forms memory element of the present invention;
Figure 64 illustrates the tenth step in order to the dual-damascene technics of the electrode layer that forms memory element of the present invention;
Figure 65 illustrates the 11 step in order to the dual-damascene technics of the electrode layer that forms memory element of the present invention;
Figure 66 illustrates the alternative view of the structure of Figure 65;
Figure 67 illustrates the first step in order to the FEOL that forms the self-aligned contact, and it has implemented the storage organization of invention;
Figure 68 illustrates second step in order to the FEOL that forms the self-aligned contact, and it has implemented the storage organization of invention;
Figure 69 illustrates the third step in order to the FEOL that forms the self-aligned contact, and it has implemented the storage organization of invention;
Figure 70 illustrates the 4th step in order to the FEOL that forms the self-aligned contact, and it has implemented the storage organization of invention;
Figure 71 illustrates the 5th step in order to the FEOL that forms the self-aligned contact, and it has implemented the storage organization of invention;
Figure 72 illustrates the array structure of the storage organization that uses Figure 71;
Figure 73 illustrates in order to manufacturing has a step in the alternate embodiment of in-line memory of many conductor layers;
Figure 74 illustrates in order to a step in the alternate embodiment of making in-line memory, and it is included in the electrode trenches etching among the interlevel dielectric layer;
Figure 75 illustrates in order to a step in the alternate embodiment of making in-line memory, comprises the result along shape deposition insulation film;
Figure 76 illustrates in order to a step in the alternate embodiment of making in-line memory, is included in the deposition and the planarization results of the electrode member in the interlevel dielectric layer;
Figure 77 illustrates in order to a step in the alternate embodiment of making in-line memory, comprises phase-change material layers and the tectal deposition results of protection;
Figure 78 illustrates in order to a step in the alternate embodiment of making in-line memory, comprises the patterning of phase-change material layers, leads bridge with the definition phase transformation;
Figure 79 illustrates in order to a step in the alternate embodiment of making in-line memory, comprises the result that the deposition interlayer dielectric is filled;
Figure 80 illustrates in order to a step in the alternate embodiment of making in-line memory, is included in the result that interlayer dielectric forms patterned conductor among filling;
Figure 81 illustrates in order to be defined in the mask layout of the electrode trenches among Figure 74;
Figure 82 illustrates in order to the phase transformation among definition Figure 78 and leads the mask layout of bridge;
Figure 83 illustrates the mask layout in order to the definition via hole, and this via hole is in order to contact the electrode to Figure 80.
Embodiment
The present invention's thin film phase change memory cell, the formed array of this memory cell and in order to make the method for this memory cell are done detailed narration with reference to Fig. 1-83.
Fig. 1 illustrates the basic structure of memory cell 10, comprises the bridge of memory material 11 that is positioned on the electrode layer, and it comprises first electrode 12, second electrode 13 and the insulating component 14 between first electrode 12 and second electrode 13.As shown in the figure, first and second electrode 12,13 has upper surface 12a and 13a.In the same manner, also has upper surface 14a.In this embodiment, upper surface 12a, the 13a of these structures in electrode layer, 14a have defined the smooth in fact upper surface of electrode layer.Bridge of memory material 11 is positioned on the flat upper surfaces of electrode layer, make first electrode 12 with lead between the bridge 11 and second electrode 13 with lead contacting between the bridge 11, reached by the bottom side of leading bridge 11.
Fig. 2 is illustrated in first electrode 12, leads the current path 15 between the bridge 11 and second electrode 13, and it is formed by memory cell structure.The execution mode of access circuit can be with multiple structure contact to first electrode 12 and second electrode 13, operation with the control store unit, make it to be programmed and will lead bridge 11 and be set in one of two kinds of solid-state phases that these two kinds of solid-state phases can be utilized storage medium and reversibly implement.For example, use contains the phase-change storage material of chalcogenide, this memory cell can be set to high relatively Resistance states, wherein this to lead bridge at least a portion in current path be amorphous state, or this memory cell can be set to low relatively Resistance states, wherein this to lead bridge at least a portion in current path be crystalline state.
Fig. 3 is illustrated in the active channel 16 of leading in the bridge 11, and wherein active channel is in the phase-change memory cell, material brought out with in two kinds of solid-state zones of switching in mutually at least.Be understandable that this active channel 16 can be made very smallly, reduce in order to bring out the needed current amplitude of phase transformation.
Fig. 4 illustrates the significant dimensions of memory cell 10.The length L of active channel (x axle) is defined by the thickness of insulating component 14 between first electrode 12 and second electrode 13.This length L can be controlled by the thickness of the insulation wall 14 among the control store unit embodiment.In exemplary embodiments, the thickness of insulation wall 14 can utilize film deposition techniques and form the thin sidewalls dielectric in the side of polar stack and form.Therefore, in the embodiment of memory cell, has channel length L less than 100nm.In other embodiments, channel length L is 40nm or following.In other embodiments, this channel length is less than 20nm.Be understandable that, channel length even can be much smaller than 20nm, the demand of its visual application-specific is reached as film deposition techniques such as technique for atomic layer deposition and utilize.
Similarly, in memory cell embodiment lead bridge thickness T (y axle) can be very small.Leading the bridge thickness T can be formed on the upper surface of first electrode 12, insulation wall 14 and second electrode 13 by using film deposition techniques.Therefore, in memory cell embodiment, leading the bridge thickness T is below the 50nm.In the embodiment of other memory cell, leading bridge thickness is below the 20nm.In other embodiments, leading the bridge thickness T is below the 10nm.Scrutablely be, lead the bridge thickness T even can utilize as technique for atomic layer deposition etc. and less than 10nm, demand on application-specific is decided, as long as this thickness can make and leads the purpose that bridge is carried out its memory element, promptly have at least two kinds of solid-state phases and reversibly brought out by electric current or the voltage that is applied between first and second electrode.
As shown in Figure 4, it is also very small to lead bridge width W (z axle).In a preferred embodiment, this leads the bridge width W less than 100nm.In certain embodiments, leading the bridge width is below the 40nm.
The embodiment of memory cell comprise with become mutually the basis storage medium was constituted leads bridge 11, phase-change material can comprise that chalcogenide is material and other material on basis.Chalcogenide comprises any in following four kinds of elements: oxygen (O), sulphur (S), selenium (Se) and tellurium (Te), the part of VI family on the forming element periodic table.Chalcogenide comprises chalcogen and more electropositive element or combined with radical is got.The chalcogen compound alloy comprises chalcogen compound is combined with other material such as transition metal etc.The chalcogen compound alloy generally includes the element that is selected from the periodic table of elements the 6th hurdle more than, for example germanium (Ge) and tin (Sn).Usually, more than one compound in the column element under the chalcogen compound alloy comprises: antimony (Sb), gallium (Ga), indium (In) and silver (Ag).Many with become mutually the basis storage medium be described in the technological document, comprise following alloy: gallium/antimony, indium/antimony, indium/selenium, antimony/tellurium, germanium/tellurium, germanium/antimony/tellurium, indium/antimony/tellurium, gallium/selenium/tellurium, tin/antimony/tellurium, indium/antimony/germanium, silver/indium/antimony/tellurium, germanium/tin/antimony/tellurium, germanium/antimony/selenium/tellurium and tellurium/germanium/antimony/sulphur.In germanium/antimony/tellurium alloy family, can attempt large-scale alloying component.This composition can following feature formula be represented: Te
aGe
bSb
100-(a+b)
A researcher has described the most useful alloy and has been, the average tellurium concentration that is comprised in deposition materials is far below 70%, typically be lower than 60%, and the tellurium content range in the alloy of general type is from minimum 23% to the highest by 58%, and best between 48% to 58% tellurium content.It is about 5% that the concentration of germanium is higher than, and its average range in material generally is lower than 50% from minimum 8% to the highest by 30%.Best, the concentration range of germanium is between 8% to 40%.Remaining main component then is an antimony in this composition.Above-mentioned percentage is atomic percent, and it is 100% for all constituent elements adds up.(Ovshinky ' 112 patents, hurdle 10～11) comprises Ge by the specific alloy that another researcher assessed
2Sb
2Te
5, GeSb
2Te
4, and GeSb
4Te
7(Noboru Yamada, " Potential of Ge-Sb-Te Phase-change Optical Disksfor High-Data-Rate Recording ", SPIE v.3109, pp.28-37 (1997)) more generally, transition metal such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt) and above-mentioned mixture or alloy, can combine with germanium/antimony/tellurium to form phase-change alloy, it includes programmable electrical resistance property.The specific example of spendable storage medium, as described in Ovshinsky ' 112 patent intermediate hurdles 11-13, its example is gone into reference in this series.
Phase-change alloy can be first configuration state of general noncrystalline state and be to switch between second configuration state of general crystalline solid state at material according to its sequence of positions in the active channel zone of this unit.These alloys are at least Bistable.This vocabulary " amorphous " is in order to censuring more inordinate relatively structure, and it is than monocrystalline property more out of order, and has detectable feature as than the higher resistance value of crystalline state.This vocabulary " crystalline state " is in order to censuring structure relatively more orderly, and therefore it include for example lower than the amorphous state resistance value of detectable feature than amorphous state orderliness more.Typically, phase-change material can switch to all detectable different conditions between complete crystalline state and the complete amorphous state by electricity.Other is subjected to the change of amorphous state and crystalline state and comprises atom order, free electron density and activation energy among the material spy that influences.This material is changeable to become different solid-state or changeable becoming by two or more solid-state formed mixtures, provides from amorphous state to the grey exponent part between the crystalline state.Electrical property in this material also may change thereupon.
Phase-change alloy can switch to another phase from a kind of phase by applying electric pulse.The previous observation point out, short, pulse is by a relatively large margin tended to phase with phase-change material and changed over and be roughly amorphous state.Long, tend to phase with phase-change material than the pulse of low amplitude and change over and be roughly crystalline state.Short, the energy in the pulse is enough big by a relatively large margin, therefore is enough to destroy the bond of crystalline texture, enough simultaneously shortly therefore can prevent that atom is arranged in crystalline state once more.Do not having under the situation of inappropriate experiment, can determine to be specially adapted to the suitable pulsed quantity varied curve of specific phase-change alloy.At the further part of this paper, this phase-change material is with the GST designate, and we also need understand simultaneously, also can use the phase-change material of other type.Described in this article a kind of material that is applicable among the PCRAM is Ge
2Sb
2Te
5
Other the programmable storage medium that can be used among other embodiment of the present invention comprises doping N
2GST, Ge
xSb
y, or other decide the material of resistance with the conversion of different crystalline states; Pr
xCa
yMnO
3, PrSrMnO
3, ZrO
x, TiO
x, NiO
x, WO
x, the SrTiO through mixing
3Or other utilizes electric pulse to change the material of resistance states; Or other uses electric pulse to change the material of resistance states; TCNQ (7,7,8,8-tetracyanoquinodimethane), PCBM (methanofullerene 6,6-phenyl C61-butyric acid methyl ester), TCNQ-PCBM, Cu-TCNQ, Ag-TCNQ, C
60-TCNQ, TCNQ or any other polymeric material of mixing with other material, it includes the bistable controlled with electric pulse or multistablely decides Resistance states.
Four kinds of resistive of then simple description.First kind is chalcogenide materials, for example Ge
xSb
yTe
z, x: y: z=2 wherein: 2: 5, or other composition is x:0～5; Y:0～5; Z:0～10.GeSbTe with nitrogen, silicon, titanium or other element doping also can be used.
A kind of example methodology in order to the formation chalcogenide materials is utilized PVD sputter or magnetron (Magnetron) sputtering way, and its reacting gas is that argon gas, nitrogen and/or helium, pressure are 1mTorr to 100mTorr.This deposition step generally at room temperature carries out.Length-width ratio is that 1～5 collimater (collimater) can be inserted performance in order to improve it.Insert performance in order to improve it, also can use tens of extremely Dc biases of hundreds of volts.On the other hand, it also is feasible merging use Dc bias and collimater simultaneously.
Can be optionally in a vacuum or deposit after annealing in the nitrogen environment and handle, with the crystalline state of improvement chalcogenide materials.The temperature of this annealing in process is typically between 100 ℃ to 400 ℃, and annealing time is then less than 30 minutes.
The thickness of chalcogenide materials is decided along with the design of cellular construction.Generally speaking, thickness can have phase-change characteristic greater than the chalcogenide of 8nm, makes this material represent bistable at least Resistance states.
Second kind of storage medium that is suitable in the invention process profit is super giant magnetoresistance (CMR) material, for example Pr
xCa
yMnO
3, x: y=0.5 wherein: 0.5, or other composition is x:0～1; Y:0～1.The super giant magnetic resistance that includes Mn oxide also can be used.
In order to form the example methodology of super giant magnetic resistance, utilize PVD sputter or magnetron sputtering way, its reacting gas is that argon gas, nitrogen and/or helium, pressure are 1mTorr to 100mTorr.The temperature of this deposition step can be decided on post-treatment condition between room temperature to 600 ℃.Length-width ratio is that 1～5 collimater (collimater) can be inserted performance in order to improve it.Insert performance in order to improve it, also can use tens of extremely Dc biases of hundreds of volts.On the other hand, it also is feasible merging use Dc bias and collimater simultaneously.Can apply tens of Gausses (Gauss) to the magnetic field between 1 Te Sila (tesla, 10,000 Gausses), to improve its magnetic knot crystalline state.
Can be optionally in a vacuum or deposit after annealing in nitrogen or the oxygen/nitrogen hybird environment and handle, to improve the crystalline state of super giant magnetic resistance.The temperature of this annealing in process is typically between 400 ℃ to 600 ℃, and annealing time is then less than 2 hours.
The thickness of super giant magnetic resistance is decided along with the design of memory cell structure.Thickness can be used as core material between the super giant magnetic resistance of 10nm to 200nm.YBCO (YBACuO
3, a kind of high-temperature superconductor material) and resilient coating is used to improve the crystalline state of super giant magnetic resistance usually.The super giant magnetic resistance of deposition that is deposited on of this YBCO carries out before.The thickness of YBCO is between 30nm to 200nm.
The third storage medium is dual element compound, for example Ni
xO
y, Ti
xO
y, Al
xO
y, W
xO
y, Zn
xO
y, Zr
xO
y, Cu
xO
yDeng, x: y=0.5 wherein: 0.5, or other composition is x:0～1; Y:0～1.In order to form the example methodology of this storage medium, utilize PVD sputter or magnetron sputtering way, its reacting gas is that argon gas, nitrogen and/or helium, pressure are 1mTorr to 100mTorr, its target metal oxide is as Ni
xO
y, Ti
xO
y, Al
xO
y, W
xO
y, Zn
xO
y, Zr
xO
y, Cu
xO
yDeng.This deposition step generally at room temperature carries out.Length-width ratio is that 1～5 collimater can be inserted performance in order to improve it.Insert performance in order to improve it, also can use tens of extremely Dc biases of hundreds of volts.In the time of if necessary, it also is feasible merging use Dc bias and collimater simultaneously.
Can be optionally in a vacuum or deposit after annealing in nitrogen environment or the oxygen/nitrogen hybird environment and handle, distribute with the oxygen atom in the improvement metal oxide.The temperature of this annealing in process is typically between 400 ℃ to 600 ℃, and annealing time is then less than 2 hours.
A kind of substituting formation method is utilized PVD sputter or magnetron sputtering way, its reacting gas is argon gas/oxygen, argon gas/nitrogen/oxygen, pure oxygen, helium/oxygen, helium/nitrogen/oxygen etc., pressure is 1mTorr to 100mTorr, and its target metal oxide is as Ni, Ti, Al, W, Zn, Zr, Cu etc.This deposition step generally at room temperature carries out.Length-width ratio is that 1～5 collimater can be inserted performance in order to improve it.Insert performance in order to improve it, also can use tens of extremely Dc biases of hundreds of volts.In the time of if necessary, it also is feasible merging use Dc bias and collimater simultaneously.
Can be optionally in a vacuum or deposit after annealing in nitrogen environment or the oxygen/nitrogen hybird environment and handle, distribute with the oxygen atom in the improvement metal oxide.The temperature of this annealing in process is typically between 400 ℃ to 600 ℃, and annealing time is then less than 2 hours.
Another kind of formation method uses high-temperature oxydation system (for example high temperature furnace pipe or rapid thermal treatment (RTP)) to carry out oxidation.This temperature between 200 ℃ to 700 ℃, with pure oxygen or nitrogen/oxygen mixed gas, carry out under at pressure for number mTorr to atmospheric pressure.The time of carrying out can be from several minutes to a few hours.Another method for oxidation is a plasma oxidation.Less radio-frequency or direct voltage source plasma and pure oxygen or argon gas/oxygen mixed gas or argon gas/nitrogen/oxygen mixed gas are the oxidation of carrying out the metal surface under the 1mTorr to 100mTorr, for example Ni, Ti, Al, W, Zn, Zr, Cu etc. at pressure.This oxidization time was from extremely several minutes several seconds.Oxidizing temperature, is decided on the degree of plasma oxidation to about 300 ℃ from room temperature.
The 4th kind of storage medium is polymeric material, for example is doped with the TCNQ of copper, carbon 60, silver etc., or the PCBM-TCNQ mixed polymer.A kind of formation method utilizes thermal evaporation, electron beam evaporation or molecular beam epitaxy system (MBE) to evaporate.Solid-state TCNQ and alloy ball are at the independent indoor coevaporation that carries out.This solid-state TCNQ and alloy ball place tungsten ship or tantalum ship or ceramic ship.Then apply big electric current or electron beam,, make these material mixing and being deposited on the wafer with the fusing reactant.Do not use reactive chemical or gas herein.This deposition is 10 at pressure
-4Torr to 10
-10Carry out under the Torr.Wafer temperature is between room temperature to 200 ℃.
Can be optionally in a vacuum or deposit after annealing in the nitrogen environment and handle, with the component distributing of improvement polymeric material.Typically between room temperature to 300 ℃, annealing time is then less than 1 hour for the temperature of this annealing in process.
Another kind of in order to the technology of formation one deck based on the storage medium of polymer, use rotary coating machine and TCNQ solution through mixing, rotating speed is lower than 1000rpm.After rotary coating, this wafer leaves standstill (typically at room temperature, or be lower than 200 ℃ temperature) enough time in order to solid-state formation.This time of repose can between several minutes to a couple of days, apparent temperature and formation condition and decide.
Fig. 5 illustrates the structure of PCRAM unit.These unit are formed on the Semiconductor substrate 20.For example the insulation system of shallow trench isolation dielectric (STI) (not shown) etc. has been isolated paired memory cell access transistors row.This access transistor is used as drain terminal with n type terminal 26 as common source zone and n type terminal 25,27 among P type substrate 20. Polysilicon word line 23,24 grids as access transistor.The dielectric fill layer (not shown) is formed on the polysilicon word line.This layer is the conductive structure of patterning, comprises common source line 28, and its contact is to the source region 26, and row in the array and as common source line.Embolism structure 29,30 contacts respectively to drain terminal 25,26.The upper surface that packed layer (not shown), common source line 28 and embolism structure 29,30 all have general planar perhaps is suitable as the substrate that forms electrode layer 31.
Film bridge of memory material 36 (for example GST) is positioned at a side on the electrode layer 31, forms first memory cell across insulative sidewall 35a, and film bridge of memory material 37 (for example GST) are positioned at opposite side on the electrode layer 31, form second memory cell across insulated gate 35b simultaneously.
The dielectric fill layer (not shown) is positioned at film leads on the bridge 36,37.Dielectric fill layer comprises silicon dioxide, polyimides, silicon nitride or other dielectric packing material.In an embodiment, this packed layer comprises quite good heat and electrical insulator, provides to lead good heat of bridge and electric insulating effect.Tungsten plug 38 contacts to electrode member 33.Include the patterned conductive layer 40 of metal or other electric conducting material (being included in the bit line in the array structure), be positioned on the dielectric fill layer, and contact to embolism 38 and lead the access of the memory cell of bridge 36 and 37 for corresponding to film to set up.
Fig. 6 is illustrated in the structure on the Semiconductor substrate 20 among Fig. 5, presents in the mode of Butut.Therefore, the arrangement of word line 23,24 is parallel to common source line 28 in fact, the common source line in the memory cell array and arranging.Embolism 29,30 contacts the terminal of the access transistor to the Semiconductor substrate and the bottom side of electrode member 32,34 respectively.Film bridge of memory material 36,37 is positioned on the electrode member 32,33,34, and insulated gate 35a, 35b separate these electrode members.Embolism 38 contact is to leading the electrode member 33 between bridge 36 and 37 and the bottom side of the metal bit line under patterned conductive layer 40 41 (being transparent) in Fig. 6.Metal bit line 42 (nontransparent) is also shown among Fig. 6, to emphasize the array layout of this structure.
In operation, corresponding to the access of the memory cell of leading bridge 36, be to control signal to word line 23 and reach by applying, word line 23 is coupled to film with common source line 28 via terminal 25, embolism 29 and electrode member 32 and leads bridge 36.Electrode member 33 is coupled to the bit lines in patterned conductive layer via contact embolism 38.Similarly, corresponding to the access of the memory cell of leading bridge 37, be to control signal to character line 24 and reach by applying one.
Scrutable is can use multiple different materials in the structure of Fig. 5 and 6.For example, can use copper metallization.The metallization of other type such as aluminium, titanium nitride and tungstenic material etc. also can be used.Simultaneously, also can use as non-metallic conducting materials such as polysilicon through mixing.Employed electrode material in described embodiment is preferably titanium nitride or tantalum nitride.Perhaps, this electrode can be TiAlN or aluminium nitride tantalum, maybe can comprise the element that is selected from more than in following group: titanium (Ti), tungsten (W), molybdenum (Mo), aluminium (Al), tantalum (Ta), copper (Cu), platinum (Pt), iridium (Ir), lanthanum (La), nickel (Ni) and ruthenium (Ru) and by alloy that above-mentioned element constituted.Insulated gate 35a, 35b can be the dielectric of silicon dioxide, silicon oxynitride, silicon nitride, aluminium oxide or other low-k between electrode.Perhaps, insulating barrier can comprise and is selected from following group element more than one between electrode: silicon, titanium, aluminium, tantalum, nitrogen, oxygen and carbon.
Fig. 7 is the schematic diagram that storage array is shown, the description that it can be done with reference to figure 5 and 6 and implementing.Therefore, the label among Fig. 7 is corresponding to the label in Fig. 5 and 6.Scrutable is that the array structure shown in Fig. 7 can utilize other cellular construction and implement.In the explanation of Fig. 7, common source line 28, word line 23, with word line 24, be parallel to Y-axis haply.Bit line 41 and 42 is parallel to X-axis haply.Therefore, Y decoder and word line driver in square 45 are coupled to word line 23,24.X decoder in square 46 and one group of sensing amplifier then are coupled to bit line 41,42.Common source line 28 is coupled to the source terminal of access transistor 50,51,52,53.The grid of access transistor 50 is coupled to word line 23.The grid of access transistor 51 is coupled to word line 24.The grid of access transistor 52 is coupled to word line 23.The grid of access transistor 53 is coupled to word line 24.The drain electrode of access transistor 50 is coupled to electrode member 32 and leads bridge 36 with connection, leads 36 on bridge and then is coupled to electrode member 33.Similarly, the drain electrode of access transistor 51 is coupled to electrode member 34 and leads bridge 37 with connection, leads 37 on bridge and then is coupled to electrode member 33.Electrode member 33 is coupled to bit line 41.Convenient for diagram, electrode member 33 is positioned at diverse location with bit line 41.Be understandable that in other embodiments, different memory cell are led bridge can use different electrode members.Access transistor 52 and 53 also is coupled to corresponding memory cell on bit line 42.As seen, common source line 28 is shared by two array storage units among the figure, and row are wherein arranged along Y-axis.Similarly, electrode member 33 is shared by two memory cell of delegation in the array, and the row in array then is to arrange along X-axis.
Fig. 8 is the simplification calcspar according to the integrated circuit of the embodiment of the invention.Integrated circuit 75 comprises storage array 60, and it utilizes thin film phase change memory cell and is based upon on the Semiconductor substrate.Column decoder 61 is coupled to many word lines 62, and each row in the storage array 60 and arranging.Row decoder 63 is coupled to multiple bit lines 64, these bit lines in the storage array 60 each row and arrange, and read and programming data in order to the multiple-grid utmost point memory cell from array 60.The address provides to row decoder 63 and column decoder 61 from bus 65.Sensing amplifier and data among square 66 are read in (daa-in) circuit, are coupled to row decoder 63 via data/address bus 67.Data from the integrated circuit substrate 75 input/output end port or from other inside or the external data sources of integrated circuit 75, the data input structure to square 66 is provided via Data In-Line road 71.In described embodiment, this integrated circuit comprises other circuit 74, is supported as general processor or proprietary application circuit or with the thin film phase change memory cell array and the integrate module of system single chip (system on a chip) function can be provided.The sensing amplifier of data from square 66 be via DOL Data Output Line road 72, and be sent to the input/output end port of integrated circuit 75, or be sent to integrated circuit 75 inner or other outside data purposes.
Use bias voltage to arrange the controller of status mechanism 69 in the present embodiment, the control bias voltage is arranged the application of service voltage 68, for example reads, programmes, wipes, erase-verifying and programming affirmation voltage etc.This controller can use known dedicated logic circuit.In alternate embodiment, this controller comprises general processor, and it can be applicable in the same integrated circuit, this integrated circuit computer program and control the operation of this device.In another embodiment, this controller uses the combination of dedicated logic circuit and general processor.
Fig. 9 is illustrated in the structure 99 after the FEOL, forms the standard CMOS element in an illustrated embodiment, and it is corresponding to the word line in the array shown in Figure 7, source electrode line and access transistor.In Fig. 9, source electrode line 106 covers the doped region 103 in the Semiconductor substrate, and wherein doped region 103 is corresponding to the source terminal of second access transistor on right side among first access transistor in left side among the figure and the figure.In this embodiment, source electrode line 106 extends to the upper surface of structure 99.In other embodiments, this source electrode line also not exclusively extends to the surface.Doped region 104 is corresponding to the drain electrode of this first access transistor.Include the word line of polysilicon 107 and silicide cover layer 108, as the grid of this first access transistor.Dielectric layer 109 is positioned on this polysilicon 107 and the silicide cover layer 108.Embolism 110 these these doped regions 104 of contact, and the surface of conductive path to this structure 99 is provided, and be connected to the memory cell electrode in the aftermentioned mode.Doped region 105 is as the drain terminal of second access transistor.Include the grid of the word line of polysilicon lines 111 and silicide lid (not indicating) as this second access transistor.Embolism 112 contacts to doped region 105 and the upper surface of conductive path to structure 99 is provided, and is connected to the memory cell electrode in mode described later.Isolated groove 101,102 with this link to embolism 110 and 112 double transistor structure, separate with adjacent double transistor structure.On the doped region 115 in left side, word line polysilicon 117 and embolism 114 are shown.On right side doped region 116, word line polysilicon 118 and embolism 113 are shown.Structure 99 in Fig. 9 provides in order to form the substrate of memory cell device, comprises first and second electrode and bridge of memory material, the following detailed description in detail.
Figure 10 illustrates the next step of this technology, and the thin dielectric layer 120 comprising silicon nitride (SiN) or other material are arranged is formed on the surface of structure 99.Then, the conductive electrode material layer 121 as titanium nitride (TiN) is formed on the dielectric layer 120.
Figure 11 A and 11B illustrate the next step of this technology, and wherein conductive electrode layer 121 and dielectric layer 120 are patterned with definition polar stack 130,131,132 (131a in 11A figure, 132a, 133a) on the surface of structure 99.In one embodiment, polar stack is defined by the mask lithography step, and the photoresist layer that this step produces patterning then carries out known dimensional measurement and determining step, and follows titanium nitride and the silicon nitride of etching in order to cambium layer 121 and 120.This lamination has sidewall 133 and 134.
Figure 12 illustrates the next step of this technology, wherein dielectric sidewall 140,141,142,143 earlier by form with the sidewall of this lamination and lamination along the thin film dielectric layer (not shown) of shape on the sidewall of lamination 130,131,132, follow this thin film dielectric layer of anisotropic ground etching so that it is removed between the lamination and the zone of stack surface, and residual being formed on the sidewall.In this implementation of processes example, comprise silicon nitride or other dielectric substance, for example silicon dioxide, silicon oxynitride, aluminium oxide etc. in order to the material that forms sidewall 140,141,142,143.
Figure 13 illustrates the next step of this technology, and wherein second electrode material layer 150 is formed on lamination 130,131,132 and the sidewall 140,141,142,143.This electrode material layer 150 comprises titanium nitride or other suitable electric conducting material, for example tantalum nitride, aluminium alloy, copper alloy, the polysilicon through mixing etc.
Figure 14 illustrates the next step of this technology, and wherein second electrode material layer 150, sidewall 140,141,142,143 and lamination 130,131,132 are subjected to etching and complanation, to define electrode layer on the substrate that structure 99 is provided.The embodiment of grinding technics comprises chemical mechanical milling tech, then carries out brush cleaning and liquid or gas cleaning procedure, as known in the art.Electrode layer comprises electrode member 160,161,162, and the insulating component between electrode member 163,164.Electrode layer in described embodiment has smooth in fact upper surface.In this embodiment, the part-structure of insulating component 163,164 also extends under the electrode member 161, and electrode member 161 and source electrode line are isolated.Can use different materials in electrode member and insulating component in other illustration structure.
Figure 15 illustrates the next step of this technology, and wherein thin film phase change storage material layer 170 is formed on the substantial planar surface of electrode layer.The sputter that this storage medium utilization does not aim at carries out under 250 ℃.When employed phase-change storage material is Ge
2Sb
2Te
5The time, the film thickness that is generated is about below 60 nanometers.It is the flat surfaces of about 40 nanometers that embodiment involves whole wafer sputter one layer thickness.In certain embodiments, the thickness of thin layer 170 is less than 100nm, and more preferably is below the 40nm.In the embodiment of memory element, the thickness of thin layer 170 is less than 20nm, for example 10nm.After forming thin layer 170, form protection cover layer 171.This protection cover layer is included in silicon dioxide or other dielectric substance of formed low temperature depositing on the thin layer 170.This protection cover layer 171 is preferably good electricity and heat insulator, and protects storage medium can not expose in subsequent step, and for example the photoresist strip step may injure this storage medium.This technology involves and forms the low-temperature substrate dielectric, utilizes to be lower than 200 ℃ technology as temperature and to form for example silicon nitride layer or silicon dioxide layer.One of technology that is fit to applies silicon dioxide for plasma enhanced chemical vapor deposition (PECVD).Form after this protection cover layer 171, can utilize as high density plasma CVD method high temperature technologies such as (HDPCVD), and apply dielectric fill layer on storage medium.
Figure 16 A and 16B illustrate the next step of this technology, wherein form photoresist layer 180 and patterning in mask lithography technology, to define banded photoresist 180a, 180b on thin layer 170 and protection cover layer 171.Shown in Figure 16 A, insulating component 163,164 is exposed between banded photoresist 180a, the 180b.According to employed photoetching process, this band shape photoresist is thin more good more.For example, the width of this band shape photoresist equals the minimum feature size F of employed photoetching process, and wherein in current mask lithography technology, the minimum feature size of technology can be the order of magnitude of 0.2 micron, 0.14 micron or 0.09 micron.Obviously, this implementation of processes example can reach narrower minimum feature size along with improving of photoetching process.
Figure 17 A and 17B illustrate the next step of this technology, and wherein banded photoresist 180a, the 180b of Figure 16 A are through pruning, to form narrower banded photoresist 190a, 190b.Shown in Figure 17 B, the thickness of the photoresist 190 through pruning is also less than the thickness of the photoresist layer among Figure 16 B 180.In one embodiment, this band shape photoresist is pruned with isotropic etching, and it has used technologies such as reactive ion etching.This etch process is trimmed to littler live width with banded photoresist.In the embodiment of narrower banded photoresist 190a, 190b, its width is less than 100nm.In other embodiment of narrower banded photoresist 190a, 190b, its width is below the 40nm.The photoresist pruning utilizes the oxide plasma and waits tropism ground etching photoresist, and then in the photoetching process of 0.09 micron (90 nanometer) minimum feature size, its width and thickness is trimmed to about 40nm.In alternate embodiment, the silicon nitride of hard mask layer such as one deck low temperature depositing or silicon dioxide etc. can place the bottom of photoresist pattern, to avoid storage medium being caused the etching injury when the photoresist divesting technology.
Figure 18 A and 18B illustrate the next step of this technology; wherein more shaped like narrow photoresist 190a, 190b as etching mask; simultaneously carry out the photoetching etching,, no matter whether protect cover layer 201 to define banded storage medium 200a, 200b at the film storage material layer.As shown in the figure, banded storage medium 200a, 200b extend across insulating component 163,164 and the electrode member in electrode layer.In this implementation of processes example, storage medium comprises the GST chalcogenide materials, and utilizes as chloride or reactive fluorochemical ion etching and carry out etching.
Figure 19 A and 19B illustrate the next step of this technology, wherein form another photoresist layer 210,211,212 and patterning, with definition photoresist structure 210a, 210b, 211a, 211b, 212a, 212b.This cellular construction is corresponding to paired memory cell, and is as described below.This cellular construction is wideer than banded storage medium 200a, 200b, because its width equals the width that employed photoetching process (for example photomask photoetching process) can reach, and not through pruning.Therefore, width in certain embodiments equals the minimum feature size F in order to the photoetching process that forms this layer.
Figure 20 A and 20B illustrate the next step of this technology, wherein photoresist structure 210a, 210b, 211a, 211b, 212a, 212b are as etching mask, by etched trench 225,226 for the isolation dielectric structures of structure 99 and be etched between each row unit perpendicular to the groove 227 of word line, and definition unit structure (being 220a, 220b, 221a, 221b, 222a, 222b in Figure 20 A, is 220,221,222 in Figure 20 B).This cellular construction 220a comprises first electrode member 215, second electrode member 216 and third electrode member 217.Insulating component 163 is separated first electrode member 215 and second electrode member 216.Insulating component 164 is separated first electrode member 215 and third electrode member 217.Bridge of memory material 218 is positioned on electrode member 215,216,217 and the insulating component 163,164, to set up two memory cell on structure 220.
Figure 21 illustrates the next step of this technology, and the dielectric fill layer 230 that wherein has a flat upper surfaces is formed on the electrode structure and inserts gap and groove between electrode structure.In an embodiment of this technology, packed layer 230 utilizes high density plasma CVD (HDPCVD) to deposit, then carry out cmp and forms afterwards with cleaning.Dielectric fill layer can comprise silicon dioxide, silicon nitride and other insulating material, preferably has good heat and electrical insulation property.
In certain embodiments, outside dielectric fill layer or replace dielectric fill layer, and provide for the thermal insulation structure of leading bridge.In one embodiment, this thermal insulation structure is before applying dielectric fill layer, and the cover layer by forming heat insulator is being led on the bridge (218), and optionally is being positioned on the electrode layer and forms.The representative materials of heat insulator layer comprises the material that following element combinations forms: silicon, carbon, oxygen, fluorine and hydrogen.Be suitable as the heat insulator of thermal insulation cap rock, comprise silicon dioxide, hydrogen-oxygen carborundum, polyimides, polyamide and fluorocarbon polymer, it selects reason to be because the thermal conductivity of these materials is lower than the thermal conductivity that deposits the dielectric fill layer on it.When the material on it was silicon dioxide, this partiting thermal insulation material should have the thermal conductivity that is lower than silicon dioxide, or was lower than about 0.014J/cm*degK*Sec.Many low-k materials (low-K) can be used as isolated material, and the permittivity of low-k material is lower than the permittivity of silicon dioxide.Other is suitable as the tectal material of thermal insulation, comprises fluorinated silica, silsesquioxane (silsesquioxane), poly-cyclenes ether (polyarylene ether), Parylene (parylene), fluoropolymer, fluoride amorphous carbon, class diamond carbon, poriness silicon oxide, mesoporosity (mesoporous) silica, porousness silsesquioxane, porousness polyimides and porousness cyclenes ether.In other specific embodiment, thermal insulation structure comprises and is positioned at the dielectric filling part, is formed on and leads on the bridge 218 so that the gas filling cavity of thermal insulation effect to be provided.The single or multiple lift structure can provide thermal insulation and electric insulating effect.
Figure 22 A and 22B illustrate the next step of this technology, and wherein the via hole (not shown) carries out etching in packed layer 230, arrives electrode material by storage medium and packed layer.This via etch technology can be utilized single anisotropic etch process and etching packed layer and storage material layer perhaps use two process, earlier etching packed layer, the etching storage material layer with second etch chemistries again with first etch chemistries.After via hole forms, insert via hole with tungsten metal or other electric conducting material, contact the embolism 240 (240a among Figure 21 A, 240b), 241,242 of first electrode member (for example member 215) to the electrode structure with formation, to be electrically connected with circuit on the electrode layer.In this implementation of processes example, via hole, as known in the art, is inserted with tungsten metal or other suitable electric conducting material as substrate with diffusion barrier layer and/or adhesion layer again.This structure is then carried out planarization with cmp, and carries out cleaning.At last, apply " cleaning " etch process, to form clean structure.
Figure 23 illustrates the next step of this technology, wherein forms patterned conductive layer 250 and contacts embolism to the packed layer, and the required bit line of memory element and other conductor are provided, and produces the structure shown in Fig. 5.In this implementation of processes example, use the copper alloy inlaid metallization process, wherein deposit fluorine silex glass (FSG) on exposed surface and form patterned conductive layer, then form default photoresist pattern.Then implement to be etched with the fluorine silex glass that removes exposure, then deposition substrate and inculating crystal layer are in this pattern.Then implementing copper electroplates to fill this pattern.After plating, carry out annealing steps, and then carry out grinding technics.Other embodiment can use Solder for Al-Cu Joint Welding technology, or other known metallization process.
Figure 24 A-24E illustrates the alternative techniques that produces the structure of Figure 14 in order to the structure of grinding Figure 13.Shown in Figure 24 A, the structure of Figure 13 is filled 260 covering of layer, for example photoresist or polysilicon etc., and it has covered second electrode material layer 150.Figure 24 A also illustrates this technology to the influence on the peripheral circuit outside the storage array.Especially, first electrode material layer 261 is along having covered peripheral circuit and any side wall construction on peripheral circuit.Similarly, packed layer also covers on the layer 261.
Figure 24 B illustrates the next step of this technology, wherein packed layer 260 is etched and via method planarizations such as cmps, arrive the upper surface 272 of the upper surface 270 of second electrode material layer 150 and first electrode material layer 261 and across array itself and peripheral circuit, stay noggin piece 271 and rise between the part two of second electrode material layer 150.
Figure 24 C illustrates the next step of this technology, second electrode material layer (for example titanium nitride) anisotropic etch-back optionally wherein, arrive approximately the same horizontal plane with the ideal surfaced of electrode layer, stay noggin piece 271 and be positioned at electrode material burr on noggin piece both sides and the insulating component.Then, shown in Figure 24 D, optionally the etching noggin piece stays the burr 290,291,292 in second electrode material layer.
Figure 24 E illustrates last step of this technology, wherein implements cmp with this structure of planarization, stay smooth in fact surface 300 in array region and smooth in fact surface 301 in outer peripheral areas, as the structure of Figure 14.The similar structures that label in Figure 14 is specified is included among Figure 24 E, but repeats no more.
By the described alternate embodiment of Figure 16 A-16B to 20A-20B, be illustrated among Figure 25 A-25B and Figure 26 A-26B in order to the technology that forms electrode structure and bridge of memory material.Structure shown in Figure 25 B, comprise the formed access circuit element of FEOL, comprise drain region 104,105, the common source zone 103 in the Semiconductor substrate in the Semiconductor substrate, be arranged in word line 107,111 and contact embolism 110,112 on the channel region of Semiconductor substrate, wherein contact between second electrode that embolism extends in the memory cell in drain terminal 104,105 and the electrode layer, as preceding detailed description.According to described technology, in electrode layer, carry out the patterning of electrode, simultaneously bridge of memory material patterning in self-aligned technology.Therefore, when the step of set-up dirgram 25A-25B, electrode layer forms according to the described mode of Fig. 4.The electrode layer in this stage comprises first electrode member 400, and it extends in the list structure perpendicular to the direction of the page in substrate, and on the bottom 401 of insulating component, between the insulated gate 402,403.Simultaneously, the electrode layer in this stage comprises two second electrode members 404,405, its in the substrate perpendicular to the direction of the page, be positioned at outside the insulated gate 402,403 and extend to the parallel strip structure, insulated gate 402,403 is separated first and second electrode members.After forming electrode layer, form storage material layer 406 and protection cover layer 407, describe as Figure 15.Then, as shown in the figure, deposition photoresist layer 408 and patterning are to define the pattern of two groups of memory cell, and it comprises from first electrode member that is positioned at central authorities of member 400 formation and from second electrode that is positioned at the left side of member 404 formation and second electrode that is positioned at the right side that forms from member 405.Utilize the pattern shown in Figure 25 A, cover layer 407, storage material layer 408 and electrode layer are etched, and with the definition polar stack, wherein the remainder of the remainder of electrode layer (404,400,405) and storage material layer 406 is aligned with each other.
In the described next step of Figure 26 A-26B, make and prune technology with photoresist, the photoresist layer 408 among the 25A such as ground etch figures(s) such as tropism such as its grade is to form narrower etching mask 409 on storage material layer 406 and protection cover layer 407.
In the described next step of Figure 27 A-27B, protection cover layer 407 is carried out etching with storage material layer 406 according to narrower etching mask 409.Then divest photoresist layer, stay narrow bridge of memory material, it has inferior photoetching width, and self-aligned is to electrode member 400,404,405.
The described technology of Figure 25 A-25B to 27A-27B can be applied in other field and makes the narrow line structure of self-aligned.
In another substitute technology, inferior photoetching is led bridge and can be utilized as the described technology of Figure 28 A-28B to Figure 33 and form.Figure 28 A-28B illustrates the first step of this technology, and it is similar to Figure 25 A and the described step of 25B.Indicate similar label among the figure, similar element then repeats no more.In Figure 28 A-28B, zoomed-in view with show memory cell between insulating element 420,421, and a plurality of patterns 408 in the explanation photoresist layer.Therefore, as shown in the figure, photoresist layer utilizes a photoetching process and patterning, with the position of definition bridge of memory material on electrode layer.
In the next step shown in Figure 29 A-29B, photoresist pattern 408 is subjected to isotropic etching and prunes its width, to form narrower pattern 430.Then, utilize by pattern 430 defined narrower etching masks storage material layer 406 and cover layer 407 are carried out etching, and divest photoresist, stay the structure shown in Figure 30 A-30B.
Shown in Figure 30 A-30B, include the narrow bridge of leading of storage medium lamination 436 and cover layer 437, place on first electrode member 400, and second electrode member 404 is positioned at its left side, second electrode member 405 is positioned at its right side.This is led bridge and extends across insulating component 402 and 403.
In as Figure 31 A and the described next step of 31B, side wall construction 438 is formed on storage medium lamination 436 and the cover layer 437, its by materials such as deposition one deck such as silicon nitride earlier on this structure, then this layer is carried out anisotropic etching, forms after staying sidewall 438.Storage medium lamination 436, cover layer 437 and sidewall 438 combinations form the new etching mask in the electrode layer, and it is wideer than leading bridge, and self-aligned is to leading bridge.
Shown in Figure 32 A-32B, electrode layer utilizes the sidewall etch mask and etching removes material downwards to dielectric fill layer 440, and stays electrode structure in electrode layer, and its self-aligned is to narrow bridge and the insulating component 402,403 of leading of storage medium.
As shown in figure 33, dielectric is filled 441 and is applied on this structure, and is filled in the groove between electrode structure and the bridge of memory material.The structure that is generated can be used to form in via hole and embolism and the metallized technology, and via hole and embolism are in order to contact to electrode layer.
Figure 34 A-34B illustrates to Figure 46 bridge of memory material is implemented in alternative techniques on the electrode layer, and it uses embedding technique and can protect storage medium can not expose during with the photoresist strip step in the photoresist coating.First embedding technique uses in the technology that is begun in Figure 34 A-34B.Figure 34 A-34B has shown the structure of Figure 14, it comprises the structure (having indicated 103-107,110-112,420,421 among the figure) of FEOL, and electrode layer comprises second electrode member 404 in first electrode member 400, left side, second electrode member 405 on right side, electrode layer extends along the direction of vertical page with strip, as mentioned above.First embodiment according to embedding technique is formed on the electrode layer as dielectric layers such as silicon dioxide 500, has then covered layer 500 as cover layers such as silicon nitride 501.Photoresist 502 coating and patternings are treated etched groove position 503 to be defined in the layer 500,501, and then the surface of exposing cover layer 501, and across the insulated gate 402,403 of memory cell.
In the next step shown in Figure 35 A-35B, layer 500 and 501 is etched, and divests photoresist, stays the groove 504,505 in layer 500 and 501, and these grooves extend to the surface of electrode layer.
Then, as shown in figure 36, the structure of Figure 35 B is carried out single-minded selective etch in dielectric layer 500, stay on the sidewall 507 of protruding outstanding portion 506 in dielectric layer 500 of cover layer 501.At the etching of silicon dioxide layer 500, can comprise Wet-type etching as dilution or buffered hydrofluoric acid with silicon nitride layer 501.Then, as shown in figure 37, the deposition storage material layer stays the bottom of list structure 508 at groove on this structure, and layer 509 is on cover layer 501.Storage material layer can't be formed on the sidewall 507, because be subjected to the covering of protruding outstanding portion 506.
In next group step, remove part 509 and the cover layer 501 of storage medium on cover layer 501, and groove is filled and cover storage medium bar 508 with dielectric, this structure then is flattened and forms dielectric layer 512, as shown in figure 38.Figure 39 A-39B illustrates next step, wherein applies photoresist on dielectric layer 512, and patterning is to define the Butut of first electrode 514, second electrode 515,516 and bridge of memory material 511,513.Dielectric layer 512, storage medium and electrode metal layer fill 420 according to the dielectric that the pattern of photoresist mask 520 is etched under it.Then implement the groove 510 that follow-up technology is generated to fill up, groove 510 is around electrode, and the formation contact then applies bit line on this structure, as the described technology of Figure 21 to 23 to first electrode 514.
Figure 10 illustrates the initial step in order to the alternative embedding technique that forms bridge of memory material.This technology is behind formation FEOL structure (as 103-107, the 110-112,420,421 that schemes to be indicated) and electrode layer, electrode layer comprises first electrode member 400, at second electrode member 404 in left side and at second electrode member 405 on right side, electrode layer extends along the direction of the page that hanging down into strips, as above describes in detail.In this alternative techniques, the formed sacrifice layer 450 of polysilicon or other material is deposited on the electrode layer.
Shown in Figure 41 A-41B, apply one deck photoresist and patterning, with definition mask 451, mask is positioned at desire from the position of the electrode structure to be formed of electrode member 400,404,405 formation.Photoresist layer then is subjected to anisotropic etching to form narrower mask arrangement 452, shown in Figure 42 A-42B.This narrower mask arrangement 452 is led bridge 453 on electrode layer to define narrow expendable material, shown in Figure 43 A-43B then as etching mask.
Then, apply side wall construction 454 and lead on the bridge 453 at sacrifice, as the etching mask of the electrode structure in the electrode layer, electrode layer comprises electrode member 400,404,405 and insulating component 402,403.
Figure 44 A-44B illustrates utilization and leads bridge 453 and sidewall 454 as the result of etching mask with the etched electrodes layer by sacrifice, produces to extend downward dielectric and fill 440 groove 455, and isolated electrode structure.After the etching, expendable material is led bridge 453 and is removed, and stays side wall construction 454 and forms storage material layer 460, and it covers side wall construction 454 and inserts in the groove 455, as shown in figure 45.
As shown in figure 46, the structure that is generated is ground, and to remove layer 460 top, stays part 461 on electrode structure and the part 462 in the groove 455.Then apply dielectric filling 464 and carry out planarization, to form structure as shown in figure 46, it can be used for forming in via hole, contact embolism and the metallized processing procedure, as mentioned above.
Figure 47 to Figure 54 A-54B illustrates another in order to form the alternate embodiment of the technology of narrow line of material on substrate, and it can be used to make bridge of memory material on electrode layer, as described herein.As seen, this technology is from providing substrate 600 and material layer 601 in Figure 47, and material layer comprises aforesaid storage medium.The protection cover layer can be included in the material layer 601.As the sacrificial material layer 602 of silicon dioxide, silicon nitride, polysilicon etc., be formed on the layer 601.Then apply photoresist layer and patterning, to provide etching mask 603 on sacrifice layer 602.In above-mentioned embodiment in order to the manufacturing bridge of memory material, etching mask 603 can utilize perpendicular to the width of the page and define, and this width equals the length of storage medium on electrode.Etching mask 603 is used in the etch sacrificial layer 602, is then divested to form structure as shown in figure 48, and its middle level 601 has sacrifice layer 604, and its pattern is defined by etching mask 603, comprises rank wall 605.
Figure 49 illustrates the next step of this technology, wherein form as the side-wall material 606 of silicon nitride, silicon dioxide or polysilicon etc. on sacrificial patterned 604 and material layer 601.Then as shown in figure 50, side-wall material layer 606 is also optionally formed sidewall 607 by anisotropic etching.Then utilize with sidewall etch identical etching technique or other at layer 604 and cover layer (if having) etch compounds selectively, and etched material layer 601 and stop at substrate 600, make the edge 608 of layer 601 be positioned under the side wall construction 607, extend the rank wall 605 that surmounts sacrificial patterned 604.
Figure 51 illustrates next step, and wherein formerly on the generating structure, the material of layer 609 is identical with the material of side wall construction 607 for cambium layer 609.Then implement planarization to remove the part of layer 609 on sacrifice layer 604, the surface 610 of exposing sacrifice layer 604 is for subsequent etch technology, shown in Figure 52.As seen, layer 608 edge is positioned under the sidewall that still exists, and sidewall material in this embodiment is identical with layer 609, and assimilates with the remainder of layer 609 in fact.Optionally, layer 609 deposition and planarisation step can be omitted, and side wall construction 607 gives over to etching mask after removing sacrifice layer 604, as described in the explanation of Figure 53.
Figure 53 illustrates the optionally result of etch sacrificial layer 604, stay the remainder of side wall construction 607 and (optionally) layer 609, and layer 601 extends under the sidewall edge of layer 609.
Figure 54 A-54B illustrates and utilizes the sidewall mask technique and form time step of the narrow line of material in edge.Illustrate at Figure 54 A and to remove the top view of layer after 601 parts of not protected by material 609; comprise layer 609 and the narrow line of material at 608 places at the edge; the layer 601 of the narrow line of material under the edge forms (in fact it is positioned under layers 609 the edge, shown in Figure 54 B).
Figure 54 B is an end view, and the edge 608 in its middle level 601 is protected on substrate 600 by material 609.Utilize this method, can form the narrow line of material, for example be used as the narrow line of the storage medium of leading bridge in the invention described above memory cell structure, it has inferior photoetching width and inferior photoetching thickness, and the two thickness by film defines.
Figure 55-65 illustrates and utilizes structure and the technology of dual-damascene structure in electrode layer.In dual damascene (DD) structure, dielectric layer is formed in two horizontal plane patterns, and wherein first horizontal pattern has defined the groove of conductor lines, and second horizontal line has then defined in order to be connected to its via hole of structure down.This via hole and groove can utilize two lithography steps and define.Groove typically is etched to first degree of depth, and via hole is etched to second degree of depth and generates the opening that descends structure to it in order to contact.After via hole and groove are etched, use deposition step and with metal or other electric conducting material filled vias and groove.After the filling, the excess material that is deposited on the groove outside can be utilized the cmp program and remove, and reaches smooth, as to have embedded conductor dual-damascene structure.
Shown in Figure 55, in dual-damascene technics, be generally dielectric material layer 651 and be formed on the FEOL structure, and as the one deck that is embedded by mosaic electrode.This mosaic technology comprises the first patterning photoresist layer 652, and it is positioned on the layer 651, shown in Figure 56.The first patterning photoresist layer 652 has defined the position that will be etched into groove 653,654,655 in layer 651, it is corresponding to the electrode member position in the mosaic electrode structure.
Utilize patterning photoresist layer 652 as mask, layer 651 is etched to first degree of depth, this degree of depth and incomplete penetrated bed 651, and formed shallow trench 656,657,658, shown in Figure 57.Then, the second patterning photoresist layer 659 is formed on the layer 651.The second patterning photoresist layer 659 has defined with electrode member and has contacted position 660,661 to embolism 110,112.Utilize the second patterning photoresist layer 659 as mask, and etch layer 651 and be penetrated into embolism 110,112 fully in shallow trench 656,657,658, to form deep trench 662,663, shown in Figure 59.
The two channeled layer 651 that generated to be filling as the metal of copper or copper alloy, and are applied with suitable adhesion as known in the art and barrier layer, to form the layer 664 shown in Figure 60.Shown in Figure 61, implement cmp or other step to remove the part that metal level 664 down extends to dielectric layer 651, generate electrode layer with dual-damascene structure, wherein have electrode structure 665,666,667. Electrode structure 665 and 667 has the contact that extends downward embolism 110 and 112, and electrode structure 666 is then isolated with source electrode line 106.
In the next step shown in Figure 62, storage material layer 668 is formed on the electrode layer 651 with protection cover layer 669.The patterning photoresist layer that includes mask 670 and 671 is formed on the protection cover layer 669, shown in Figure 63.Mask 670 and 671 has defined the position of the bridge of memory material of memory cell.Then implement etching step,, stay bridge of memory material 672,673 to remove not masked 670,671 layers of being protected 669 and storage material layer 668.Lead bridge 672 and extend to electrode structure 666, across insulating component 674 from electrode structure 665.The thickness of insulating component 674 has defined the length in path between the electrode that passes through bridge of memory material 672.Lead bridge 673 and contact to electrode structure 666, across insulating component 675 from electrode structure 667.The thickness of insulating component 675 has defined the length in path between the electrode that passes through bridge of memory material 673.
Shown in Figure 65, defined and led after the bridge 672,673, apply dielectric and fill (not shown) and planarization.Follow in dielectric is filled, on the electrode member 666 via etch.This via hole is inserted with the embolism as tungsten, to form conductive plug 676.Patterned metal layer is with definition bit line 677, and bit line 677 contacts to embolism 676, and arranges along each right row of memory cell, and its structure is shown in Figure 65.
Figure 66 illustrates the structure that is generated by dual damascene electrode layer technology, and wherein the dielectric substance among Figure 65 is removed from electrode layer 651, to obtain preferable graphic extension effect.As shown in the figure, electrode structure 665,667 extends downwards and touches tungsten plug 110,112, and electrode structure 666 is then isolated with source electrode line 106.In Figure 66, can see the size and the layout of this unit simultaneously.Basic double memory cell structure can be according to this technology, and in the zone of about 8F*2F, carry out Butut (wherein F is the minimum feature size of photoetching process), photoetching ground shifts pattern from mask and makes on the device to waiting, and makes the thickness of insulating component between this device and definition electrode and lead the bridge width across electrode with this.In this layout, most of 8F length is in order to make embolism 110,112 needed alignment errors.
Figure 67-72 illustrates in order to make the alternate embodiments that this has the FEOL structure of self-aligned contact via hole, and via hole allows the less footmark in the memory cell Butut in order to contact to electrode layer.This technology comprises carries out Butut to a plurality of parallel wires, utilize as polysilicon and the tectal mode of silicide and make, and the formation injection zone is to provide source electrode and drain terminal between parallel wire.Figure 67 illustrates the profile of the structure that is produced by these processing steps, and wherein parallel wire 801-806 is positioned on the Semiconductor substrate, and has doped region 807-813, and these doped regions have defined source electrode and drain terminal between lead 801-806.In the embodiment shown, lead 802,803 and 805,806 word lines as access transistor.801,804 in lead is used as bias line, to prevent the counter-rotating between source electrode 809 and drain terminal 808 and 810.Therefore, lead 801,804 be insulated wire with isolated transistor, replace the insulated trench among the previous embodiment.Therefore, as shown in the figure, the Butut length of basic double memory cell structure can narrow down to about 6F, and it utilizes self-aligned contact structures technology and finishes, shown in Figure 68-71.
The first step of this self-aligned contact structures process implementing example is in order to form packed layer 820 on parallel wire 801-806, shown in Figure 68.Then packed layer 820 utilizes the photoetching process etching, with the position of definition source electrode line 821,822 and embolism 823～827.The alignment error tolerance value of photoetching process in this technology is by obtaining parallel wire compensation, as known in the art as the self-aligned etching mask.In dielectric fill layer 820 groove filled by electric conducting material, tungsten plug material for example is with definition embolism 833-837 and source electrode line 831,832, shown in Figure 70.
Then shown in Figure 71, the formation utilization of electrode layer shown in Figure 11 A-11B technology and reach, it on and form the pattern structure that comprises silicon nitride layer 120 and titanium nitride layer 121, provide electrode structure with source electrode line 831 isolation.Figure 71 can understand the yardstick of this electrode structure, and its middle level 120 and 121 allows the less Butut of memory cell structure between between the 2F to 3F.In order to the balance between the technology that forms electrode layer and bridge of memory material, implement according to above-mentioned technology.
Figure 72 is the schematic diagram of storage array, is similar to Fig. 7, has wherein added shielding wire, and the by way of example of this array is shown in Fig. 5-6, and increase is as the correction of the self-aligned contact structures of Figure 71.Therefore, the reference number of each element of Figure 72 is corresponding to the structure of Fig. 7.Be understandable that the array structure among Figure 72 can utilize other cellular construction and implement.In Figure 72, common source line 28, word line 23,24 are roughly parallel and arrange along Y-axis.Code wire 801,804 also is to be parallel to Y direction.Bit line 41,42 is roughly parallel and arrange along X-axis.Therefore, Y-axis decoder and word line driver are coupled to word line 23,24.Bias generator is coupled to lead 801,804, and it can apply earthing potential or other current potential etc., to isolate this pair cellular construction.X-axis decoder and one group of sensing amplifier are coupled to bit line 41,42.Common source line 28 is coupled to the source terminal of access transistor 50-53.The grid of access transistor 50 is coupled to word line 23.The grid of access transistor 51 is coupled to word line 24.The grid of access transistor 52 is coupled to word line 23.The grid of access transistor 53 is coupled to word line 24.The drain electrode of access transistor 50 is coupled to electrode member 32 and leads bridge 36 with connection, leads 36 on bridge and then is coupled to electrode member 33.Similarly, the drain electrode of access transistor 51 is coupled to electrode member 34 and leads bridge 37 with connection, leads 37 on bridge and then is coupled to electrode member 33.Electrode member 33 is coupled to bit line 41.Convenient for diagram, electrode member 33 is positioned at diverse location with bit line 41.Be understandable that in other embodiments, different memory cell are led bridge can use different electrode members.Access transistor 52 and 53 also is coupled to corresponding memory cell on bit line 42.As seen, common source line 28 is shared by two array storage units among the figure, and row are wherein arranged along Y-axis.Similarly, electrode member 33 is shared by two memory cell of delegation in the array, and the row in array then is to arrange along X-axis.Code wire 801,804 is biased into closed condition with transistor 850-853, prevents that electric current from flowing between drain terminal and adjoining memory cell.
Figure 73-80 illustrates in order to make another has each step that the memory element embodiment of bridge is led in phase transformation.Described embodiment is fit to make in-line memory on integrated circuit, and it comprises the multilevel metallization layer or is arranged to the interior multi-layered patterned conductor that connects each element on this device.Figure 73 illustrates Semiconductor substrate 899, and it has array region and outer peripheral areas, the two by such as the isolation structure 898 of dielectric filling groove etc. separation.This substrate comprises the integrated circuit member, and it has terminals such as doped region in Semiconductor substrate.In outer peripheral areas, include functional circuit member in order to deal with data.In array region, include the access circuit member of programmable memory cell array.Shown in Figure 73, in array region, include doped region 103,104,105, it corresponds respectively to common source terminal, first drain region and second drain region of access structure, as above describes in detail.Word line 107,111 is in order to be coupled to common source line 106 with terminal 103,104 or terminal 103,105, as mentioned above.Conductive plug 110,112 is arranged with the patterned conductor 903,904 in the metal layer 900 that respectively terminal 104,105 is connected thereto.
Doped region 950,951,952 is to be configured to the transistor of functional circuit with grid 953,954 in outer peripheral areas.Conductive plug 955,956,957 is arranged with the patterned conductor in the metal layer 900 that terminal 950,951,952 is connected thereto 905,906.
In described embodiment, comprise second patterning conductor layer 902.This patterning conductor layer comprises the interlayer dielectric filling, and it comprises etching stopping layer 901.For example this interlevel dielectric layer 902 can comprise silicon dioxide or the doping silicon dioxide that one deck is above, and etching stopping layer 901 can comprise silicon nitride.Patterned conductor is included within interlayer dielectric fills, the conductor 909 that comprises the conductor 907,908 that contacts the conductor 903,904 to the array region and contact the conductor 906 to the outer peripheral areas.
Figure 74 illustrates the etched result of patterning groove, and it is in order to definition groove, for example groove in the array region 910.This groove extends between the conductor component 907,908, and exposes sidewall 911,912.The etching of this groove stops at etching stopping layer 901.Though groove only is shown among Figure 74, in memory element array, etching has a large amount of grooves.After the etching, divested in order to the photoresist layer that defines this pattern.
Figure 75 illustrates the suitable shape deposition results of insulating barrier 913.Insulating barrier comprises silicon dioxide or other insulating material, and it utilizes plasma enhanced chemical vapor deposition or other known technology and deposits.In exemplary embodiments, the thickness of insulating barrier 913 makes and to cover thickness on the sidewall 911,912 between about 10 nanometer to 30 nanometers.
Figure 76 illustrates and utilizes as technology such as copper metallization and plated metal, then utilize technology such as cmp to carry out the result of etch-back.The structure that is generated comes out the surface 914,916 of insulating barrier 913 on sidewall 911,912, also exposes electrode member 915, wherein surface 914,916 coplines of the surface of insulating component 915 and conductor component 907,908 and insulating barrier 913.Simultaneously, the surface 917 of conductor component 909 also is exposed after etch back process.In other embodiments, electrode member 915 can use tungsten, aluminium, titanium nitride, tantalum nitride or other electric conducting material.
Figure 77 illustrates with technology such as sputters and sediment phase change material layer 918 and with the result as deposition techniques one deck protective material layers 919 such as low temperature chemical vapor deposition (for example silicon nitride, silicon dioxide or other electrical insulating material etc.).Simultaneously, protective material layer 919 can have thermal insulation and electric insulating effect, and can comprise electric insulation and heat-insulating composite material.
Figure 78 illustrates the patterning of phase-change material, leads bridge 920,921 with the definition phase transformation, and it comprises phase-change material layers 918 and protective material layer 919 left material part 918a, 919a after pattern etched.This pattern etched can be utilized photoresist mask, hard mask or other technology and implement, and can utilize technology such as pruning and make this width of leading bridge under inferior lithographic dimension, describes in detail as previous embodiment.
Figure 79 is illustrated in phase transformation and leads the result who forms interlevel dielectric layer 922 on the outer peripheral areas of bridge and substrate.Figure 80 is illustrated in via etch and the patterning ditch trench etch in the packed layer 922, and the metal deposition in via hole and groove is to form the 3rd patterning conductor layer.In this embodiment, patterning conductor layer can be utilized known technologies such as dual-damascene technics, and is formed among the interlayer dielectric packed layer 922.The position of conductive plug 923,925 can utilize photoresist mask or other to define in order to the technology of define pattern.Similarly, in exemplary embodiments, patterned conductor 924,926 is utilized the photoresist photoetching and is defined.Conductor 924 is arranged to bit line in the array region of this device.Conductor 926 is used as the 3rd metal layer with each member of interior connection in peripheral circuit.
Figure 81-83 illustrates the Butut in order to one group of exemplary masks of the embolism of leading bridge, Figure 80 of the groove of definition Figure 74, Figure 78.In Figure 81, M2 zone 961-968 has confirmed the position of conductive plug, and this conductive plug is corresponding to the embolism 110,112 of four pairs of memory cell among Figure 73.In illustrative embodiments, the size in M2 zone is about 1.5F*2F, and wherein F is the minimum feature size in order to the Patternized technique (for example photoetching process) that defines this structure.Mask 1 regional 971-974 has confirmed the position of groove, and this groove is corresponding to the groove among Figure 74 910, and it overlaps onto regional 961-968 a little.In this embodiment, the size of Mask 1 regional 971-974 is about 2F*6F, and approximately overlapping to M2 zone 961-968 with 1F.The zone that is generated is about 7F*2F, and allows to have between each structure the distance of 1F, and the area of two cellular constructions then is about 8F*3F.Therefore, in the structure of Figure 81-83 representative, the area of each unit is about 12F
2Figure 82 illustrates Mask 2 regional 981-984, and it has confirmed to lead in order to the phase transformation among definition Figure 78 the mask position of bridge 920,921.The size in Mask 2 zones is about 1F*6F, and is positioned on electrode member and the insulating component (corresponding respectively to the member 915,914 and 916 of Figure 76).Figure 83 illustrates via area V2, and it has confirmed the position of via hole, and this via hole is in order to form the embolism 923 corresponding to Figure 80.The size of via area V2991-994 is about 2F*2F in illustrative embodiments.Via hole V2 zone 991-994 has defined the square region of quadrature to the Mask2 middle section, with phase change material strip separately with form separate lead bridge 920,921.The bridge size of leading that is generated is about 1F*2F.In alternate embodiment, the width that bridge is led in phase transformation can as above describe in detail less than 1F.
The described embodiment of Figure 73-83 has comprised the in-line memory on integrated circuit, and it comprises three layer pattern conductor layers, and has phase transformation and lead the central authorities that bridge is formed on patterned conductive layer.In other in-line memory product, may use patterning conductor layer more than three layers.According to this technology, phase transformation is led bridge and can be formed in arbitrary certain layer, comprises bottom and any intermediate layer on bottom.Each embodiment also can be configured to form phase transformation and leads bridge on last patterning conductor layer.
In the phase-change memory cell kind known to the applicant, most of by forming small hole and inserting phase-change memory cell, then form contact to the top electrode and the hearth electrode of this phase-change material and form.This small pore space structure is in order to reduce program current.The present invention has reduced program current and need not form small hole, therefore can reach technology controlling and process preferably.In addition, on the unit, there is no top electrode, avoid phase-change material to be subjected to potential damage in order to the technology that forms top electrode.
Unit described herein comprises two hearth electrodes and dielectric therebetween, and is positioned on the electrode, leads bridge across dielectric phase-change material.This hearth electrode and dielectric are in the electrode layer that is formed on FEOL CMOS logical construction or other functional circuit structure, provide and to support in-line memory and the functional circuit structure on single-chip easily, this chip can be given an example as SOC (system on a chip) (system on chip, SOC) device.
The advantage of embodiment of the present invention comprises that phase transition phenomena occurs in to lead bridge central authorities on the dielectric fill layer, but not occurs in the interface of leading between bridge and the electrode, and therefore better reliability degree is provided.Simultaneously, the electric current that is used in replacement and the programming operation is confined in the small volume, the localized heating effect that has allowed high current density and produced, and only need less reset current and lower replacement power consumption.Structure in embodiments of the present invention, two dimensions that allow this unit are defined by the thickness of film, reach preferable technology controlling and process under nanoscale.Only there is a dimension to define (this photoetching process is used the mask layer through pruning) in the unit, thereby avoided more complicated photoetching technique by photoetching process.
Though the present invention system is described with reference to preferred embodiment, will be appreciated that the present invention's creation is not subject to its detailed description by us.Substitute mode and revise pattern and in previous description, advise, and other substitute mode and modification pattern will be expected by those skilled in the art.Particularly, according to structure of the present invention and method, all have be same as in fact member of the present invention in conjunction with and reach the neither disengaging of identical result person spiritual category of the present invention in fact with the present invention.Therefore, all this substitute modes and revise pattern and be intended to drop among the category that appended claims and equivalent thereof of the present invention define.Any patent application of mentioning in preamble and printed text are all classified the reference of this case as.
Claims (21)
1, a kind of memory device comprises:
One substrate, it comprises the integrated circuit member, comprises a plurality of conductor layers, and these conductor layers are in order to being connected to the described integrated circuit component of small part, and described a plurality of conductor layers comprise ground floor and are positioned at special layer on this ground floor;
Should comprise first electrode with upper surface, second electrode, the insulating component between this first electrode and this second electrode by special layer with upper surface;
Lead bridge, it is between this first and second electrode and across this insulating component place, and this is led bridge and has first side and second side, and with this first side contacts this upper surface to this first and second electrode, wherein this is led bridge and has storage medium, and this storage medium has at least two kinds of solid-state phases; And
Conductor is arranged in one decks at least of described a plurality of conductor layers, and this conductor is positioned on this special layer and contact is led bridge to this.
2, device as claimed in claim 1, wherein this substrate comprises:
The insulation device, it forms semiconductor body element under this ground floor, and this insulation device comprises the terminal under this second electrode and extends through this ground floor at least and conductor between this terminal and this second electrode.
3, device according to claim 1, wherein the thickness of this insulating component is below 50 nanometers, and this is led bridge and comprises that thickness is that the following and width of 50 nanometers is the following films of 50 nanometers.
4, device as claimed in claim 1, wherein the thickness of this insulating component is below 20 nanometers, and this is led bridge and comprises that thickness is that the following and width of 20 nanometers is the following films of 20 nanometers.
5, device as claimed in claim 1, wherein this thickness of leading bridge is that 10 nanometers or following and its width are 10 nanometers or following.
6, device as claimed in claim 1, wherein this is led bridge and comprises top side and bottom side, and this first side is this bottom side.
7, device as claimed in claim 2, wherein this insulation device comprises transistor.
8. device as claimed in claim 2, wherein this terminal is included in the doped region in the Semiconductor substrate.
9, device as claimed in claim 2, wherein this insulation device comprises transistor, and this terminal is included in the doped region in the Semiconductor substrate, and it is as this transistorized source electrode or drain electrode, and adjacent to this doped region place, this device also comprises transistor grid structure on this Semiconductor substrate.
10, device as claimed in claim 1, wherein this insulating component comprises silicon nitride.
11, device as claimed in claim 1, wherein this storage medium comprise by germanium, antimony, with the formed composition of tellurium.
12, device as claimed in claim 1, wherein this storage medium comprises that at least two are selected from the composition that following group material is formed: germanium (Ge), antimony (Sb), tellurium (Te), indium (In), titanium (Ti), gallium (Ga), bismuth (Bi), tin (Sn), copper (Cu), palladium (Pd), plumbous (Pb), silver (Ag), sulphur (S) and gold (Au).
13, a kind of integrated circuit comprises:
Semiconductor substrate;
A plurality of circuit elements, it has a plurality of terminals, these terminals are included in the doped region in this Semiconductor substrate, and this Semiconductor substrate comprises having in order to the outer peripheral areas of the functional circuit elements of deal with data and the array region with access circuit element, and this access circuit element is used for the programmable memory cell array;
A plurality of conductor layers, these conductor layers are connected to this array region in order to what will be arranged in this outer peripheral areas to the described functional circuit elements of small part, and described a plurality of conductor layers comprise and are positioned at the ground floor on this Semiconductor substrate and are positioned at special layer on this ground floor;
Should comprise electrode pair array by special layer, wherein each in this electrode pair array comprises first electrode with upper surface, second electrode with upper surface, insulating component between this first electrode and this second electrode to electrode;
The bridge array of leading able to programme, between this first and second electrode of leading this counter electrode centering of bridge arrangement in this special layer in this array, across this insulating component place, this is led bridge and has first side and second side, and with this first side contacts this upper surface to this first and second electrode, and wherein this is led bridge and comprises storage medium, and this storage medium has at least two kinds of solid-state phases; And
A plurality of conductors, its be arranged in described a plurality of conductor layers one deck at least this array region and be positioned on this special layer, these conductors are connected to this each described bridge of leading of leading in the bridge array able to programme as bit line.
14, integrated circuit as claimed in claim 13, wherein the thickness of this insulating component is below 50 nanometers, and this leads bridge and comprise film, the thickness of this film is that following and its width of 50 nanometers is below 50 nanometers.
15, integrated circuit as claimed in claim 13, wherein the thickness of this insulating component is below 20 nanometers, and this is led bridge system and comprises that film, the thickness of this film are that following and its width of 20 nanometers is below 20 nanometers.
16, as claim the 13 described integrated circuits, wherein this thickness of leading bridge is that following and its width of 10 nanometers is below 10 nanometers.
17. the method in order to the manufacturing memory element comprises:
Form a plurality of circuit elements in Semiconductor substrate, these circuit elements have a plurality of terminals, these terminals comprise the doped region that is arranged in this Semiconductor substrate, and this Semiconductor substrate comprises having in order to the outer peripheral areas of the functional circuit elements of deal with data and the array region with access circuit element, and this access circuit element is used for the programmable memory cell array;
Form a plurality of conductor layers, these conductor layers are connected to this array region in order to what will be arranged in this outer peripheral areas to the described element of small part, and described a plurality of conductor layers comprise and are positioned at the ground floor on this Semiconductor substrate and are positioned at special layer on this ground floor;
Should be included in this array region by special layer, it has upper surface and comprises electrode pair array, this electrode pair array comprises corresponding first electrode and second electrode and is positioned at this first and second interelectrode corresponding insulating component, wherein this first and second electrode and this insulating component extend to this upper surface of this special layer, and this insulating component has width between this upper surface of this first and second electrode;
Form bridge of memory material array this upper surface at this special layer, this leads the bridge of leading that the bridge array comprises each electrode pair of use in this electrode pair array, this first and second electrode that its contact is corresponding, and extension is across this insulating component of correspondence, this is led bridge and comprises the storage medium film with first side and second side, and with this first side contacts this first and second electrode to correspondence, this is led bridge definition and is positioned at this first and second interelectrode current path across this insulating component place, this current path length is defined by this width of this insulating component, and wherein this storage medium has at least two kinds of solid-state phases; And
Form patterned conductive layer and lead on the bridge, and form between described first electrode and this patterned conductive layer of crosspoint array in this electrode pair array, wherein the corresponding contact of this second electrode contact to this crosspoint array at this.
18, method as claimed in claim 17, wherein this array region comprises many word lines and insulation device, described insulation device is controlled by the signal on described many word lines, and this patterned conductive layer comprises multiple bit lines.
19, method as claimed in claim 17, wherein two electrode pairs in this electrode pair array comprise the conductive member that is arranged in the same row, comprise first conductive member, it is as first second electrode in described two electrode pairs, second conductive member, all as first electrode, and the 3rd conductive member is used as second electrode in its second electrode pair in described two electrode pairs in described two electrode pairs for it.
20, method as claimed in claim 17, wherein this storage medium comprise by germanium, antimony, with the formed composition of tellurium.
21, method as claimed in claim 17, wherein this storage medium comprises that at least two are selected from the composition that following group material is formed: germanium (Ge), antimony (Sb), tellurium (Te), indium (In), titanium (Ti), gallium (Ga), bismuth (Bi), tin (Sn), copper (Cu), palladium (Pd), plumbous (Pb), silver (Ag), sulphur (S) and gold (Au).
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/424,749 | 2006-06-16 | ||
| US11/424,749 US8237140B2 (en) | 2005-06-17 | 2006-06-16 | Self-aligned, embedded phase change RAM |
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| Publication Number | Publication Date |
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| CN101090130A CN101090130A (en) | 2007-12-19 |
| CN100573899C true CN100573899C (en) | 2009-12-23 |
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| CN102024839B (en) * | 2009-09-11 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Phase change memory, isolation structure for memory unit and manufacturing method thereof |
| US8962411B2 (en) | 2012-08-09 | 2015-02-24 | Nanya Technology Corp. | Circuit pattern with high aspect ratio and method of manufacturing the same |
| US9564357B2 (en) * | 2014-01-24 | 2017-02-07 | Taiwan Semiconductor Manufacturing Company Limited | Method of forming semiconductor device using etch stop layer |
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| CN101090130A (en) | 2007-12-19 |
| TWI347672B (en) | 2011-08-21 |
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