CN100576353C - The wiring method of semiconductor memory - Google Patents
The wiring method of semiconductor memory Download PDFInfo
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- CN100576353C CN100576353C CN200710041097A CN200710041097A CN100576353C CN 100576353 C CN100576353 C CN 100576353C CN 200710041097 A CN200710041097 A CN 200710041097A CN 200710041097 A CN200710041097 A CN 200710041097A CN 100576353 C CN100576353 C CN 100576353C
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Abstract
The invention provides a kind of wiring method of semiconductor memory, semiconductor memory is provided, comprise Semiconductor substrate, be positioned at dielectric layer on the Semiconductor substrate-catch charge layer-dielectric layer three level stack structure and grid successively, and be positioned at dielectric layer-the catch source electrode and the drain electrode of charge layer-dielectric layer three level stack structure both sides in the Semiconductor substrate, comprise, apply first voltage at the grid of storer; Source electrode at storer applies second voltage; Drain electrode at storer applies tertiary voltage, and successively decreases gradually; Semiconductor substrate at storer applies the 4th voltage.Semiconductor memory of the present invention has reduced write-in disorder, has prevented the damage of storer, has reduced the write time, has increased write operation efficient.
Description
Technical field
The present invention relates to the wiring method of semiconductor memory, relate in particular to a kind of wiring method that contains the semiconductor memory of catching charge layer.
Background technology
Now, semiconductor memory is made of the memory cell array that comprises word line and bit line, and transistor is the basic composition unit of memory cell usually.Transistorized grid is as the word line of memory cell, and transistor drain is as the bit line of memory cell.In the time will carrying out write operation, write required voltage as long as on corresponding word line and bit line, apply for selected memory cell.Have a SONOS structure with a kind of, promptly the NROM memory cell of monox-silicon-nitride and silicon oxide grid structure is an example, and with reference to shown in Figure 1, silicon oxide layer 7, silicon nitride layer 6, silicon oxide layer 5 and grid 8 have constituted monox-silicon-nitride and silicon oxide grid structure 4.In the time will carrying out write operation for this NROM memory cell, write required voltage as long as on this NROM memory cell corresponding word lines and bit line, apply, grid 8 and drain electrode 2b just can obtain voltage, when carrying out write operation for memory cell, the source electrode 2a of NROM storer is connected to lower current potential or ground connection usually.Therefore, will produce transverse electric field at source electrode 2a and drain electrode in the raceway groove 3 between the 2b, simultaneously, because substrate 1 also is a ground connection usually, thereby grid 8 has a positive electricity pressure reduction with respect to substrate 1, also has a longitudinal electric field that is produced by grid 8 in raceway groove 3.And the electronics on the source electrode 2a will quicken under the effect of the longitudinal electric field that transverse electric field between leakage-source and grid 8 produces and form hot carrier to the motion of drain electrode 2b direction, during when the below of hot carrier process grid 8 and near drain electrode 2b, hot carrier will be attracted in the silicon nitride layer 6 of grid structure 4, thereby finishes the write operation for memory cell.
After the write operation of having finished for memory cell, all can come the present state in detection of stored unit usually by read operation.Continue with reference to shown in Figure 1, the general practice is to apply a small voltage on the source electrode 2a of NROM storer, for example applies the voltage of 1.5-1.7V on source electrode 2a, measures the electric current on the source electrode 2a then.If the electric current that records is almost nil, so just can think not have electric current in the raceway groove 3 between drain electrode 2b and source electrode 2a, just illustrate that the NROM storer is in to write completion status.And if the electric current that records demonstrates and has electric current in the raceway groove 3 between drain electrode 2b and source electrode 2a, carry out write operation for this memory cell once more with regard to needs so.
The industry method that is used for carrying out write operation has following several now: with reference to shown in Figure 2, have plenty of and keep on the word line pulse voltage constant, and on bit line, applying a less pulse voltage, the pulse voltage that puts on the bit line by continuous increase is carried out write operation for storer then; Reference is shown in Figure 3, has plenty of to apply a less pulse voltage on word line and bit line, comes storer is carried out write operation by the pulse voltage that increases gradually on word line and the bit line then; Also have plenty of the pulse voltage that keeps word line and/or bit line, carry out write operation by increasing pulse number or pulse width.For example, the patent No. a kind of method that writes for the NROM storer that has been 6873550 U.S. Patent Publication, comprise, on the grid of NROM storer, apply a voltage that increases gradually, in the drain electrode of NROM storer, apply a constant voltage, and the source ground of NROM storer is carried out write operation for the NROM storer.
Yet,, therefore all can cause the phenomenon of more serious " write-in disorder " because above-mentioned method is all carried out write operation by increasing pulse voltage gradually.So-called write-in disorder just is meant that when carrying out write operation for selected memory cell the common word line that it is adjacent or the memory cell of shared bit line are attracted to the electronics or the electronics on the substrate of source doping region in the silicon nitride layer of grid because the drain electrode of the grid of connection word line or connection bit line obtains voltage.Electronics in the silicon nitride layer that attracted to grid more for a long time, when just " write-in disorder " situation was serious, these memory cells that should not carry out write operation also can produce write operation, thereby cause the write error of storer.Therefore, how to reduce write-in disorder and become a urgent problem.
And, the existing method of write operation of carrying out is owing to the voltage that puts on word line or the bit line at first is all lower, usually need can make storer enter to write completion status by applying multiple pulses voltage, thereby the time of write operation is longer, efficient be lower.
In addition, the existing method of write operation of carrying out is because the continuous voltage that increases on the bit line, and the drain voltage of the memory cell of feasible connection bit line is also increasing, make that not only write-in disorder is more serious, and when voltage arrives to a certain degree greatly, be easy to cause the short circuit of source electrode and drain electrode, i.e. punchthrough effect, thus cause storage unit can't continue to finish to write.
So shortcoming of prior art existence: one is that the write-in disorder phenomenon is serious, and one is the short circuit that is easy to cause drain electrode and source electrode, damages device, and another is that the write time is slow, and efficient is low.
Summary of the invention
The problem that the present invention solves is that prior art semiconductor memory wiring method write-in disorder phenomenon is serious.
The problem that the present invention also solves is the short circuit that prior art semiconductor memory wiring method is easy to cause drain electrode and source electrode, damages storer.
For addressing the above problem, the invention provides a kind of wiring method of semiconductor memory, semiconductor memory is provided, comprise Semiconductor substrate, be positioned at dielectric layer on the Semiconductor substrate-catch charge layer-dielectric layer three level stack structure and grid successively, and be positioned at dielectric layer-catch the source electrode and the drain electrode of charge layer-dielectric layer three level stack structure both sides in the Semiconductor substrate, comprising:
Grid at semiconductor memory applies first voltage;
Source electrode at semiconductor memory applies second voltage;
Drain electrode at semiconductor memory applies tertiary voltage, and successively decreases gradually;
Semiconductor substrate at semiconductor memory applies the 4th voltage.
Optionally, wherein said first voltage keeps constant or begins to successively decrease from the magnitude of voltage of setting, and magnitude of voltage is 9-10V, tertiary voltage is threshold voltage poor of first voltage and semiconductor memory, the amplitude of described setting is 0.1V, and second voltage is 0-0.5V, and the 4th voltage is 0V.And described first voltage and tertiary voltage are all greater than the threshold voltage of semiconductor memory.
The present invention also provides a kind of wiring method of semicondctor storage array, semicondctor storage array is provided, each semiconductor memory comprises Semiconductor substrate, be positioned at dielectric layer on the Semiconductor substrate-catch charge layer-dielectric layer three level stack structure and grid successively, and be positioned at dielectric layer-catch the source electrode and the drain electrode of charge layer-dielectric layer three level stack structure both sides in the Semiconductor substrate, comprising:
The semiconductor memory of choosing in the semicondctor storage array writes;
Apply first voltage by a selected word line at the grid of semiconductor memory
Apply second voltage by a selected bit line at the source electrode of semiconductor memory;
Apply tertiary voltage by another selected bit line in the drain electrode of semiconductor memory, and successively decrease gradually;
Semiconductor substrate to semiconductor memory applies the 4th voltage;
Repeat above-mentioned steps, all semiconductor memories are finished and are write in semicondctor storage array.
Optionally, wherein said first voltage keeps constant or begins to successively decrease from the magnitude of voltage of setting, and magnitude of voltage is 9-10V, tertiary voltage is threshold voltage poor of first voltage and storer, the amplitude of described setting is 0.1V, and second voltage is 0-0.5V, and the 4th voltage is 0V.And described first voltage and tertiary voltage are all greater than the threshold voltage of semiconductor memory.
Compared with prior art, such scheme has the following advantages:
1. the wiring method of such scheme semiconductor memory is owing to reduce to put on voltage in the drain electrode gradually, makes that electric field also reduces gradually between the drain electrode-source electrode of memory cell of adjacent common word line or shared bit line, reduced write-in disorder.
2. the wiring method of such scheme semiconductor memory is owing to be the voltage that reduces gradually to put in the drain electrode, thereby effectively avoided the drain electrode that the increase owing to drain voltage causes and the short circuit of source electrode, prevented the damage of storer.
Description of drawings
Fig. 1 is a prior art memory construction synoptic diagram;
Fig. 2 is that first kind of wiring method of prior art storer applies the voltage synoptic diagram;
Fig. 3 is that second kind of wiring method of prior art storer applies the voltage synoptic diagram;
Fig. 4 is an embodiment of the invention memory construction ablation process synoptic diagram;
Fig. 5 is that the first embodiment of the invention memory-writing method applies the voltage synoptic diagram;
Fig. 6 is that the second embodiment of the invention storer writes the process synoptic diagram;
Fig. 7 is that the second embodiment of the invention memory-writing method applies the voltage synoptic diagram.
Embodiment
The wiring method of semiconductor memory of the present invention comes storer is carried out write operation by reducing to put on the voltage in the drain electrode gradually.
The present invention elaborates the wiring method of semiconductor memory of the present invention by two specific embodiments.
Embodiment 1, with reference to shown in Figure 4, the embodiment of the invention provides a kind of wiring method of semiconductor memory, a kind of NROM storer is provided, comprise Semiconductor substrate 10, the dielectric layer 13-that is positioned at successively on the Semiconductor substrate catches charge layer 14-dielectric layer 15 three level stack structures and grid 16, and is positioned at source electrode 11a and drain electrode 11b that dielectric layer 13-catches charge layer 14-dielectric layer 15 three level stack structure both sides in the Semiconductor substrate 10, comprising:
Drain electrode 11b at storer applies tertiary voltage, and successively decreases gradually;
Wherein, described Semiconductor substrate 10 can comprise the silicon or the SiGe (SiGe) of monocrystalline or polycrystalline structure, can also be to contain for example silicon or the SiGe that mix of N type or P type of dopant ion, and also can be silicon-on-insulator (SOI).
The three level stack structure that described dielectric layer 13-catches charge layer 14-dielectric layer 15 is preferably oxide-nitride-oxide layer, what described oxide skin(coating) was best is monox, also may comprise the nitride adulterant that for example silicon oxynitride and other can optimized device performance, described nitration case can be to be rich in for example oxygen etc. of adulterant that silicon, nitrogen and other can improve device performance, can also be hafnia, aluminium oxide etc., most preferred be silicon nitride.Described oxide-nitride-oxide layer is at present optimized to be monox-silicon-nitride and silicon oxide.
The source terminal 17a of semiconductor memory is connected on the source electrode 11a, and drain electrode holds 17b to be connected on the drain electrode 11b in succession, and substrate terminals 19 are connected on the Semiconductor substrate 10, and grid terminal 18 is connected on the grid 16.
In the present embodiment, with reference to shown in Figure 5, writing fashionable for the NROM storer, it is that first pulse voltage of 600ns is as grid voltage Vg that the grid 16 of NROM is applied pulse width, certainly the pulse width of this pulse voltage also can be 400ns or 800ns or the value between 400ns and 800ns, and the maintenance of the magnitude of voltage of described first pulse voltage is constant, generally get 9V or 10V or the value between 9V and 10V, 9.5V for example, certainly, first pulse voltage is also opened beginning from 9.5V and is successively decreased with the amplitude equal difference of each pulse voltage 0.1V, promptly come then second pulse, its magnitude of voltage is reduced to 9.4V, comes then the 3rd pulse, and its magnitude of voltage is reduced to 9.3V, certainly, first pulse voltage is not restricted to equal difference successively decreases, and the amplitude of successively decreasing is unequal also to be fine, and present embodiment is chosen equal difference and successively decreased just for more convenient operation; With substrate 10 ground connection of NROM, thereby underlayer voltage Vb is 0V; Source electrode 11a to NROM applies constant voltage as source voltage Vs, and this constant voltage can be 0V or 0.5V or the value between 0V and 0.5V, for example 0.3V; It is that the 3rd pulse voltage of 600ns is as drain voltage Vd that the drain electrode 11b of NROM is applied pulse width, certainly the pulse width of this pulse voltage also can be 400ns or 800ns or the value between 400ns and 800ns, and described the 3rd pulse voltage is 5.7V, and amplitude taper with each pulse voltage 0.1V, i.e. second pulse in the 3rd pulse voltage comes then, its magnitude of voltage is reduced to 5.6V, comes then in the 3rd pulse of the 3rd pulse voltage, and its magnitude of voltage is reduced to 5.5V.In addition, because when writing for the NROM storer, the general requirement is operated in the saturation region, therefore, voltage difference Vgs on grid 16 and the source electrode 11a is greater than the threshold voltage of storer, and the voltage difference Vds on drain electrode 11b and the source electrode 11a is also greater than the pinch-off voltage Vdsat of storer.Wherein, pinch-off voltage is meant drain electrode 11b when the drain electrode inversion layer charge is zero and the voltage difference on the source electrode 11a.Certainly, the NROM storer is not limited to be operated in the saturation region when writing, and this still needs to require to decide according to writing of reality.
Because the embodiment of the invention has applied very little voltage to source electrode 11a and the Semiconductor substrate 10 of NROM, therefore, strengthened between grid 16 and the Semiconductor substrate 10, and the voltage between source electrode 11a and the drain electrode 11b, not only strengthened the collision energy of electronics between source electrode 11a and drain electrode 11b, produce more thermoelectron, and bigger voltage difference also can produce more thermoelectron between grid 16 and the Semiconductor substrate 10, and, accelerate thermoelectron toward the migration velocity of catching charge layer 14, accelerated the electronics writing speed of NROM greatly.
And, at first applied a higher initial voltage in drain electrode on the 11b, according to repetition test, when the voltage on the drain electrode 11b and storer threshold voltage sum equaled voltage on the grid 16, the NROM storer can enter quickly and write completion status.This be because this moment the charge carrier generation rate the highest, injection rate IR is also maximum, so the NROM storer can enter the soonest and writes completion status.And the threshold voltage of NROM storer is generally 2.5-5.0V, be 9-10V according to the voltage that puts on the grid 16 again, when the initial voltage that applies on the drain electrode 11b is between 4.0-7.5V, NROM is entered quickly so and write completion status, and wherein preferable value is 5.7V.Therefore, applying higher voltage on the 11b in drain electrode just can just make this storer enter after 1-2 pulse to write completion status, just can make that the drain electrode and the electric field between the source electrode of memory cell of adjacent common word line or shared bit line is less and successively decrease gradually by the amplitude of 0.1V after this, thereby avoided the electronics in more raceway grooves to attracted to catching in the charge layer of grid structure, reduced write-in disorder.
The embodiment of the invention also provides a kind of wiring method of semicondctor storage array, NROM is provided array, same with reference to shown in Figure 4, each NROM storer comprises Semiconductor substrate 10, the dielectric layer 13-that is positioned at successively on the Semiconductor substrate 10 catches charge layer 14-dielectric layer 15 three level stack structures and grid 16, and be positioned at source electrode 11a and the drain electrode 11b that dielectric layer 13-catches charge layer 14-dielectric layer 15 three level stack structure both sides in the Semiconductor substrate 10, comprising:
The NROM storer of choosing in the NROM memory array writes;
Apply first voltage by a selected word line at the grid of NROM storer;
Apply second voltage by a selected bit line at the source electrode of NROM storer;
Apply tertiary voltage by another selected bit line in the drain electrode of NROM storer, and successively decrease gradually;
Semiconductor substrate to the NROM storer applies the 4th voltage;
Repeat above-mentioned steps, finish writing until all semiconductor memories of semicondctor storage array.
Wherein, described first voltage is 9-10V or successively decreases since a setting voltage value, for example begins amplitude taper with each pulse voltage 0.1V from 9.5V; Described second voltage is 0-0.5V; Described tertiary voltage is threshold voltage poor of first voltage and semiconductor memory, and the amplitude of setting is 0.1V; Described the 4th voltage is 0V; Described first voltage and tertiary voltage are that pulse width is the continuous impulse voltage of 400-800ns.
The method that writes for NROM storer in the NROM array is with the described method that writes for single NROM storer is identical before, here repeated description no longer just.
Embodiment 2, with reference to shown in Figure 6, the embodiment of the invention provides a kind of wiring method of semiconductor memory, a kind of NROM storer is provided, comprise Semiconductor substrate 100, the dielectric layer 106-that is positioned at successively on the Semiconductor substrate catches charge layer 107-dielectric layer 108 three level stack structures and grid 109, and is positioned at source electrode 103 and drain electrode 104 that dielectric layer 106-catches charge layer 107-dielectric layer 108 three level stack structure both sides in the Semiconductor substrate 100, comprising:
Wherein, described Semiconductor substrate 100 can comprise the silicon or the SiGe (SiGe) of monocrystalline or polycrystalline structure, can also be to contain for example silicon or the SiGe that mix of N type or P type of dopant ion, and also can be silicon-on-insulator (SOI).
The three level stack structure that described dielectric layer 106-catches charge layer 107-dielectric layer 108 is preferably oxide-nitride-oxide layer, what described oxide skin(coating) was best is monox, also may comprise the nitride adulterant that for example silicon oxynitride and other can optimized device performance, described nitration case can be to be rich in for example oxygen etc. of adulterant that silicon, nitrogen and other can improve device performance, can also be hafnia, aluminium oxide etc., most preferred be silicon nitride.Described oxide-nitride-oxide layer is at present optimized to be monox-silicon-nitride and silicon oxide.
The source terminal 110a of semiconductor memory is connected on the source electrode 103, and drain electrode holds 110b to be connected in the drain electrode 104 in succession, and substrate terminals 112 are connected on the Semiconductor substrate 100, and grid terminal 111 is connected on the grid 109.
In the present embodiment, with reference to shown in Figure 7, writing fashionable for the NROM storer, it is that first pulse voltage of 600ns is as grid voltage Vg that the grid 109 of NROM is applied pulse width, certainly the pulse width of this pulse voltage also can be 400ns or 800ns or the value between 400ns and 800ns, and described first pulse voltage maintenance is constant, generally get 9V or 10V or the value between 9V and 10V, 9.5V for example, certainly, first pulse voltage is also opened to begin the amplitude taper with each pulse voltage 0.1V from 9.5V, promptly come then second pulse, its magnitude of voltage is reduced to 9.4V, comes then the 3rd pulse, and its magnitude of voltage is reduced to 9.3V, certainly, first pulse voltage is not restricted to equal difference successively decreases, and the amplitude of successively decreasing is unequal also to be fine, and present embodiment is chosen equal difference and successively decreased just for more convenient operation; With substrate 100 ground connection of NROM, thereby underlayer voltage Vb is 0V; Source electrode 103 to NROM applies constant voltage as source voltage Vs, and this constant voltage can be 0V or 0.5V or the value between 0V and 0.5V, for example 0.3V; It is that the 3rd pulse voltage of 600ns is as drain voltage Vd that the drain electrode 104 of NROM is applied pulse width, certainly the pulse width of this pulse voltage also can be 400ns or 800ns or the value between 400ns and 800ns, and described the 3rd pulse voltage is 5.7V, and amplitude taper with each pulse voltage 0.1V, i.e. second pulse in the 3rd pulse voltage comes then, its magnitude of voltage is reduced to 5.6V, comes then in the 3rd pulse of the 3rd pulse voltage, and its magnitude of voltage is reduced to 5.5V.In addition, because when writing for the NROM storer, the general requirement is operated in the saturation region, therefore, voltage difference Vgs on grid 109 and the source electrode 103 is greater than the threshold voltage of storer, and drain 104 and source electrode 103 on voltage difference Vds also greater than the pinch-off voltage Vdsat of storer.Wherein, pinch-off voltage is meant drain electrode 104 when the drain electrode inversion layer charge is zero and the voltage difference on the source electrode 103.Certainly, the NROM storer is not limited to be operated in the saturation region when writing, and this still needs to require to decide according to writing of reality.
And in conjunction with Fig. 6 and shown in Figure 7, the embodiment of the invention also putting on the operation of carrying out a soft-erase between per two pulse voltages of drain electrode on 104, specifically comprises the steps, applies the 5th voltage at the grid 109 of storer; Source electrode 103 at storer applies the 6th voltage; Drain electrode 104 at storer applies the 7th voltage; Semiconductor substrate 100 at storer applies the 8th voltage.Wherein, the 8th voltage that applies on the Semiconductor substrate 100 and the 6th voltage that on source electrode 103, applies still with carry out pulse voltage and write fashionable identically, be respectively 0V and 0.3V; And the 5th voltage that applies on grid 109 will be lower than underlayer voltage, could make the constraint that accumulates in the electron detachment dielectric layer 106 on the dielectric layer 106 of three level stack structure that dielectric layer 106-catches charge layer 107-dielectric layer 108 come in the substrate 100 like this.Can make that like this threshold voltage of storer is more stable when twice pulse voltage writes.A preferable value of the 5th voltage in this enforcement on the grid 109 is-2V.And get 2V at the 7th voltage that drain electrode applies on 104, voltage is provided with the electronics that mainly prevents to catch in the charge layer 107 to be pulled Semiconductor substrate 100 too much herein.
Because the embodiment of the invention applies very little voltage to source electrode 103 and the Semiconductor substrate 100 of NROM, therefore, strengthened between grid 109 and the Semiconductor substrate 100, and source electrode 103 and the voltage between 104 of draining, not only strengthened electronics at source electrode 103 and the collision energy between 104 of draining, produce more thermoelectron, and bigger voltage difference also can produce more thermoelectron between grid 109 and the Semiconductor substrate 100, and, accelerate thermoelectron toward the migration velocity of catching charge layer 107, accelerated the electronics writing speed of NROM greatly.
And, at first applied a higher initial voltage in drain electrode on 103, according to repetition test, when the voltage in the drain electrode 103 and storer threshold voltage sum equaled voltage on the grid 109, NROM can enter quickly and write completion status.And the threshold voltage of NROM storer is generally 2.5-5.0V, be 9-10V according to the voltage that puts on the grid 109 again, when the initial voltage that applies in the drain electrode 103 is between 4.0-7.5V, NROM is entered quickly so and write completion status, and wherein preferable value is 5.7V.Therefore, applying higher voltage on 103 in drain electrode just can just make this storer enter after 1-2 pulse to write completion status, just can make that the drain electrode and the electric field between the source electrode of memory cell of adjacent common word line or shared bit line is less and successively decrease gradually by the amplitude of 0.1V after this, thereby avoided the electronics in more raceway grooves to attracted to catching in the charge layer of grid structure, reduced write-in disorder.
Further,, make that the threshold voltage of storer is more stable when twice pulse voltage writes, further reduced the influence of write-in disorder owing between twice pulse voltage for storer writes, carried out the operation of a soft-erase.
The embodiment of the invention also provides a kind of wiring method of semicondctor storage array, NROM is provided array, same with reference to shown in Figure 6, each NROM storer comprises Semiconductor substrate 100, the dielectric layer 106-that is positioned at successively on the Semiconductor substrate 100 catches charge layer 107-dielectric layer 108 three level stack structures and grid 109, and be positioned at source electrode 103 and the drain electrode 104 that dielectric layer 106-catches charge layer 107-dielectric layer 108 three level stack structure both sides in the Semiconductor substrate 100, comprising:
The NROM storer of choosing in the NROM memory array writes;
Apply first voltage by a selected word line at the grid of NROM storer;
Apply second voltage by a selected bit line at the source electrode of NROM storer;
Apply tertiary voltage by another selected bit line in the drain electrode of NROM storer, and the amplitude taper to set;
Semiconductor substrate to the NROM storer applies the 4th voltage;
Repeat above-mentioned steps, finish writing until all semiconductor memories of semicondctor storage array.
As selected NROM storer is that of the left side among Fig. 6, then the source terminal 110a with semiconductor memory is connected on the source electrode 103, drain electrode holds 110b to be connected in the drain electrode 104 in succession, and substrate terminals 112 are connected on the Semiconductor substrate 100, and grid terminal 111 is connected on the grid 109.And drain terminal 110c is floating empty, 105 just floating skies like this drain.
On the grid 109 of NROM storer, apply first voltage by selected word line,
Wherein, described first voltage is 9-10V or successively decreases since a setting voltage value, for example begins amplitude taper with each pulse voltage 0.1V from 9.5V; Described second voltage is 0-0.5V; Described tertiary voltage is the threshold voltage of first voltage-semiconductor memory, and the amplitude of setting is 0.1V; Described the 4th voltage is 0V; Described first voltage and tertiary voltage are that pulse width is the continuous impulse voltage of 400-800ns.
The method that writes for NROM storer in the NROM array is with the described method that writes for single NROM storer is identical before, here repeated description no longer just.
Effect for the wiring method of verifying semiconductor memory of the present invention, chosen and had dielectric layer equally-catch the PFROM of charge layer-dielectric layer three level stack structure as testing memory, on the wafer that comprises the PFROM storer, choose 33 crystal grain (die), and semiconductor memory wiring method and the semiconductor memory wiring method of the present invention of using prior art write test relatively.
The test result of using prior art semiconductor memory wiring method is as shown in table 1:
Table 1
The test result of the wiring method of application semiconductor memory of the present invention is as shown in table 2:
Table 2
As shown in Table 1 and Table 2, X and Y are representing the coordinate of crystal grain on wafer respectively, and umber of pulse then represents PFROM when being confirmed as good or losing efficacy, and has been written into the how many times pulse voltage altogether.As can be seen from Table 1, in 33 crystal grain being selected, be confirmed as good crystal grain and only have 4, therefore using the yield that prior art semiconductor memory wiring method writes detection only is 12%, and great majority have all write the pulse voltage more than 4 and just make storer enter to write completion status.And as can be seen from Table 2, in 33 crystal grain being selected, be confirmed as good crystal grain and have 31, therefore using the yield that semiconductor memory wiring method of the present invention writes detection is 94%, and the overwhelming majority has only write 1 pulse voltage and just makes storer enter to write completion status.So with respect to prior art, the efficient that writes of semiconductor memory wiring method of the present invention has all improved greatly with the yield that writes the wafer of detection.
In sum, the wiring method of semiconductor memory of the present invention is by putting on the semiconductor memory with bigger grid voltage and bigger drain voltage, and reduce to put on voltage in the drain electrode gradually, make that electric field also reduces gradually between the drain electrode-source electrode of memory cell of adjacent common word line or shared bit line, reduced write-in disorder.And, the wiring method of semiconductor memory of the present invention is owing to be to put on the semiconductor memory with bigger grid voltage and bigger drain voltage, increased the success ratio of write operation, avoided multiple write operations for storer, therefore reduce the write time, increased write operation efficient.Moreover, the wiring method of semiconductor memory of the present invention is owing to reduced write-in disorder, so when writing detection, avoided the problem of the out of memory that wiring method improperly causes, therefore improved the yield of product for the wafer that comprises storer.
Claims (28)
1. the wiring method of a semiconductor memory, semiconductor memory is provided, comprise Semiconductor substrate, be sequentially arranged in dielectric layer on the Semiconductor substrate-catch charge layer-dielectric layer three level stack structure and grid according to order from top to bottom, and in Semiconductor substrate, be positioned at dielectric layer-the catch source electrode and the drain electrode of charge layer-dielectric layer three level stack structure both sides, it is characterized in that, comprise
Grid at semiconductor memory applies first voltage;
Source electrode at semiconductor memory applies second voltage;
Drain electrode at semiconductor memory applies tertiary voltage, and successively decreases gradually;
Semiconductor substrate at semiconductor memory applies the 4th voltage.
2. the wiring method of semiconductor memory as claimed in claim 1 is characterized in that, described first voltage is 9-10V.
3. the wiring method of semiconductor memory as claimed in claim 1 is characterized in that, described first voltage begins to successively decrease gradually from arbitrary value between 9-10V.
4. the wiring method of semiconductor memory as claimed in claim 3 is characterized in that, described first voltage begins to successively decrease with the amplitude equal difference of 0.1V from arbitrary value between 9-10V.
5. the wiring method of semiconductor memory as claimed in claim 3 is characterized in that, described first voltage is greater than the threshold voltage of semiconductor memory.
6. the wiring method of semiconductor memory as claimed in claim 1 is characterized in that, described second voltage is 0-0.5V.
7. the wiring method of semiconductor memory as claimed in claim 1 is characterized in that, described tertiary voltage is threshold voltage poor of first voltage and semiconductor memory, and successively decreases with the amplitude equal difference of 0.1V.
8. the wiring method of semiconductor memory as claimed in claim 7 is characterized in that, described tertiary voltage is greater than the threshold voltage of semiconductor memory.
9. the wiring method of semiconductor memory as claimed in claim 1 is characterized in that, described the 4th voltage is 0V.
10. as the wiring method of claim 1 to 5 or 7 to 8 each described semiconductor memories, it is characterized in that described first voltage and tertiary voltage are that pulse width is the continuous impulse voltage of 400-800ns.
11. the wiring method of semiconductor memory as claimed in claim 10 is characterized in that, carries out the soft-erase operation between two pulse voltages, described soft-erase is operated and is further comprised,
Grid at storer applies the 5th voltage;
Source electrode at storer applies the 6th voltage;
Drain electrode at storer applies the 7th voltage;
Semiconductor substrate at storer applies the 8th voltage.
12. the wiring method of semiconductor memory as claimed in claim 11 is characterized in that, described the 5th voltage is-2V that described the 7th voltage is 2V.
13. the wiring method of semiconductor memory as claimed in claim 11 is characterized in that, described the 6th voltage is 0-0.5V.
14. the wiring method of semiconductor memory as claimed in claim 11 is characterized in that, described the 8th voltage is 0V.
15. the wiring method of a semicondctor storage array, semicondctor storage array is provided, each semiconductor memory comprises Semiconductor substrate, be sequentially arranged in dielectric layer on the Semiconductor substrate-catch charge layer-dielectric layer three level stack structure and grid according to order from top to bottom, and in Semiconductor substrate, be positioned at dielectric layer-the catch source electrode and the drain electrode of charge layer-dielectric layer three level stack structure both sides, it is characterized in that, comprise
The semiconductor memory of choosing in the semicondctor storage array writes;
Apply first voltage by a selected word line at the grid of semiconductor memory;
Apply second voltage by a selected bit line at the source electrode of semiconductor memory;
Apply tertiary voltage by another selected bit line in the drain electrode of semiconductor memory, and successively decrease gradually;
Semiconductor substrate to semiconductor memory applies the 4th voltage;
Repeat above-mentioned steps, all semiconductor memories are finished and are write in semicondctor storage array.
16. the wiring method of semicondctor storage array as claimed in claim 15 is characterized in that, described first voltage is 9-10V.
17. the wiring method of semicondctor storage array as claimed in claim 15 is characterized in that, described first voltage begins to successively decrease gradually from arbitrary value between 9-10V.
18. the wiring method of semicondctor storage array as claimed in claim 17 is characterized in that, described first voltage begins to successively decrease with the amplitude equal difference of 0.1V from arbitrary value between 9-10V.
19. the wiring method of semicondctor storage array as claimed in claim 17 is characterized in that, described first voltage is greater than the threshold voltage of semiconductor memory.
20. the wiring method of semicondctor storage array as claimed in claim 15 is characterized in that, described second voltage is 0-0.5V.
21. the wiring method of semicondctor storage array as claimed in claim 15 is characterized in that, described tertiary voltage is threshold voltage poor of first voltage-semiconductor memory, and successively decreases with the amplitude equal difference of 0.1V.
22. the wiring method of semicondctor storage array as claimed in claim 21 is characterized in that, described tertiary voltage is greater than the threshold voltage of semiconductor memory.
23. the wiring method of semicondctor storage array as claimed in claim 15 is characterized in that, described the 4th voltage is 0V.
24. the wiring method as claim 15 to 19 or 21 to 22 each described semicondctor storage arrays is characterized in that, described first voltage and tertiary voltage are that pulse width is the continuous impulse voltage of 400-800ns.
25. the wiring method of semicondctor storage array as claimed in claim 24 is characterized in that, carries out the soft-erase operation between two pulse voltages, described soft-erase is operated and is further comprised,
Grid at storer applies the 5th voltage;
Source electrode at storer applies the 6th voltage;
Drain electrode at storer applies the 7th voltage;
Semiconductor substrate at storer applies the 8th voltage.
26. the wiring method of semicondctor storage array as claimed in claim 25 is characterized in that, described the 5th voltage is-2V that described the 7th voltage is 2V.
27. the wiring method of semicondctor storage array as claimed in claim 25 is characterized in that, described the 6th voltage is 0-0.5V.
28. the wiring method of semicondctor storage array as claimed in claim 25, described the 8th voltage is 0V.
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| Application Number | Priority Date | Filing Date | Title |
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| CN200710041097A CN100576353C (en) | 2007-05-23 | 2007-05-23 | The wiring method of semiconductor memory |
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|---|---|---|---|
| CN200710041097A CN100576353C (en) | 2007-05-23 | 2007-05-23 | The wiring method of semiconductor memory |
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| CN101312072A CN101312072A (en) | 2008-11-26 |
| CN100576353C true CN100576353C (en) | 2009-12-30 |
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| CN112349328B (en) | 2020-10-21 | 2021-08-17 | 中天弘宇集成电路有限责任公司 | Programming method of charge trapping flash memory |
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